git.gag.com Git - debian/gnuradio/blob - usrp/fpga/inband_lib/register_io.v

   1 module register_io
   2         (clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, strobe_wr,
   3          rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, reg_2, reg_3,
   4      debug_en, misc, txmux);
   5
   6         input clk;
   7         input reset;
   8         input wire [1:0] enable;
   9         input wire [6:0] addr;
  10         input wire [31:0] datain;
  11         output reg [31:0] dataout;
  12         output wire [15:0] debugbus;
  13         output reg [6:0] addr_wr;
  14         output reg [31:0] data_wr;
  15         output wire strobe_wr;
  16         input wire [31:0] rssi_0;
  17         input wire [31:0] rssi_1;
  18         input wire [31:0] rssi_2;
  19         input wire [31:0] rssi_3;
  20         output wire [31:0] threshhold;
  21         output wire [31:0] rssi_wait;
  22         input wire [15:0] reg_0;
  23         input wire [15:0] reg_1;
  24         input wire [15:0] reg_2;
  25         input wire [15:0] reg_3;
  26         input wire [3:0]  debug_en;
  27         input wire [7:0]  misc;
  28         input wire [31:0] txmux;
  29
  30         reg strobe;
  31         wire [31:0] out[2:1];
  32         assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
  33         assign threshhold = out[1];
  34         assign rssi_wait = out[2];
  35         assign strobe_wr = strobe;
  36
  37         always @(*)
  38         if (reset | ~enable[1])
  39            begin
  40              strobe <= 0;
  41                      dataout <= 0;
  42                    end
  43                 else
  44                    begin
  45                  if (enable[0])
  46                    begin
  47                      //read
  48                                 if (addr <= 7'd52 && addr > 7'd50)
  49                                         dataout <= out[addr-7'd50];
  50                                 else
  51                                         dataout <= 32'hFFFFFFFF;
  52                     strobe <= 0;
  53               end
  54              else
  55                begin
  56                  //write
  57                      dataout <= dataout;
  58                  strobe <= 1;
  59                                  data_wr <= datain;
  60                                  addr_wr <= addr;
  61                end
  62           end
  63
  64 //register declarations
  65     /*setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
  66     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));*/
  67     setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
  68     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1]));
  69     setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
  70     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2]));
  71     /*setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
  72     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3]));
  73     setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
  74     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4]));
  75     setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
  76     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5]));
  77     setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
  78     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6]));
  79     setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
  80     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));*/
  81
  82 endmodule