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   1 module channel_demux
   2  #(parameter NUM_CHAN = 2) (     //usb Side
   3    input [31:0]usbdata_final,
   4    input WR_final,
   5    // TX Side
   6    input reset,
   7    input txclk,
   8    output reg [NUM_CHAN:0] WR_channel,
   9    output reg [31:0] ram_data,
  10    output reg [NUM_CHAN:0] WR_done_channel );
  11    /* Parse header and forward to ram */
  12
  13     reg [2:0]reader_state;
  14     reg [4:0]channel ;
  15     reg [6:0]read_length ;
  16
  17          // States
  18     parameter IDLE      =    3'd0;
  19     parameter HEADER    =    3'd1;
  20     parameter WAIT      =    3'd2;
  21     parameter FORWARD   =    3'd3;
  22
  23         `define CHANNEL 20:16
  24         `define PKT_SIZE 127
  25         wire [4:0] true_channel;
  26         assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
  27                                                         NUM_CHAN : (usbdata_final[`CHANNEL]);
  28
  29         always @(posedge txclk)
  30           begin
  31             if (reset)
  32               begin
  33                reader_state <= IDLE;
  34                WR_channel <= 0;
  35                WR_done_channel <= 0;
  36               end
  37               else
  38                 case (reader_state)
  39                 IDLE: begin
  40                     if (WR_final)
  41                         reader_state <= HEADER;
  42                     end
  43
  44             // Store channel and forware header
  45                 HEADER: begin
  46                     channel <= true_channel;
  47                     WR_channel[true_channel] <= 1;
  48                     ram_data <= usbdata_final;
  49                                 read_length <= 7'd0 ;
  50
  51                 reader_state <= WAIT;
  52                 end
  53
  54                 WAIT: begin
  55                    WR_channel[channel] <= 0;
  56
  57                            if (read_length == `PKT_SIZE)
  58                        reader_state <= IDLE;
  59                    else if (WR_final)
  60                        reader_state <= FORWARD;
  61                 end
  62
  63                 FORWARD: begin
  64                    WR_channel[channel] <= 1;
  65                    ram_data <= usbdata_final;
  66                    read_length <= read_length + 7'd1;
  67
  68                    reader_state <= WAIT;
  69                 end
  70
  71                         default:
  72                begin
  73                                         //error handling
  74                    reader_state <= IDLE;
  75                end
  76                endcase
  77            end
  78 endmodule