2 * USRP - Universal Software Radio Peripheral
4 * Copyright (C) 2003 Free Software Foundation, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 3 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
22 * common code for USRP
25 #include "usrp_common.h"
27 void init_board (void);
32 CPUCS = bmCLKSPD1; // CPU runs @ 48 MHz
33 CKCON = 0; // MOVX takes 2 cycles
35 // IFCLK is generated internally and runs at 48 MHz; GPIF "master mode"
37 IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmIFCLKPOL | bmIFGPIF;
40 // configure IO ports (B and D are used by GPIF)
42 IOA = bmPORT_A_INITIAL; // Port A initial state
43 OEA = bmPORT_A_OUTPUTS; // Port A direction register
45 IOC = bmPORT_C_INITIAL; // Port C initial state
46 OEC = bmPORT_C_OUTPUTS; // Port C direction register
48 IOE = bmPORT_E_INITIAL; // Port E initial state
49 OEE = bmPORT_E_OUTPUTS; // Port E direction register
52 // REVCTL = bmDYN_OUT | bmENH_PKT; // highly recommended by docs
55 // configure end points
57 EP1OUTCFG = bmVALID | bmBULK; SYNCDELAY;
58 EP1INCFG = bmVALID | bmBULK | bmIN; SYNCDELAY;
60 EP2CFG = bmVALID | bmBULK | bmQUADBUF; SYNCDELAY; // 512 quad bulk OUT
61 EP4CFG = 0; SYNCDELAY; // disabled
62 EP6CFG = bmVALID | bmBULK | bmQUADBUF | bmIN; SYNCDELAY; // 512 quad bulk IN
63 EP8CFG = 0; SYNCDELAY; // disabled
67 FIFORESET = bmNAKALL; SYNCDELAY;
68 FIFORESET = 2; SYNCDELAY;
69 // FIFORESET = 4; SYNCDELAY;
70 FIFORESET = 6; SYNCDELAY;
71 // FIFORESET = 8; SYNCDELAY;
72 FIFORESET = 0; SYNCDELAY;
74 // configure end point FIFOs
76 // let core see 0 to 1 transistion of autoout bit
78 EP2FIFOCFG = bmWORDWIDE; SYNCDELAY;
79 EP2FIFOCFG = bmAUTOOUT | bmWORDWIDE; SYNCDELAY;
80 EP6FIFOCFG = bmAUTOIN | bmWORDWIDE; SYNCDELAY;
86 EP2BCL = 0x80; SYNCDELAY;
87 EP2BCL = 0x80; SYNCDELAY;
88 EP2BCL = 0x80; SYNCDELAY;
89 EP2BCL = 0x80; SYNCDELAY;
92 EP0BCH = 0; SYNCDELAY;
94 // arm EP1OUT so we can receive "out" packets (TRM pg 8-8)
96 EP1OUTBC = 0; SYNCDELAY;
98 EP2GPIFFLGSEL = 0x01; SYNCDELAY; // For EP2OUT, GPIF uses EF flag
99 EP6GPIFFLGSEL = 0x02; SYNCDELAY; // For EP6IN, GPIF uses FF flag
101 // set autoin length for EP6
102 // FIXME should be f(enumeration)
104 EP6AUTOINLENH = (512) >> 8; SYNCDELAY; // this is the length for high speed
105 EP6AUTOINLENL = (512) & 0xff; SYNCDELAY;