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   1 /*
   2  * USRP - Universal Software Radio Peripheral
   3  *
   4  * Copyright (C) 2003,2004 Free Software Foundation, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
  19  */
  20
  21 #ifndef _USRP_COMMANDS_H_
  22 #define _USRP_COMMANDS_H_
  23
  24 #include <usrp_interfaces.h>
  25 #include <usrp_spi_defs.h>
  26
  27 #define MAX_EP0_PKTSIZE                64       // max size of EP0 packet on FX2
  28
  29 // ----------------------------------------------------------------
  30 //                      Vendor bmRequestType's
  31 // ----------------------------------------------------------------
  32
  33 #define VRT_VENDOR_IN                   0xC0
  34 #define VRT_VENDOR_OUT                  0x40
  35
  36 // ----------------------------------------------------------------
  37 //                        USRP Vendor Requests
  38 //
  39 // Note that Cypress reserves [0xA0,0xAF].
  40 // 0xA0 is the firmware load function.
  41 // ----------------------------------------------------------------
  42
  43
  44 // IN commands
  45
  46 #define VRQ_GET_STATUS                  0x80
  47 #define         GS_TX_UNDERRUN                  0       // wIndexL      // returns 1 byte
  48 #define         GS_RX_OVERRUN                   1       // wIndexL      // returns 1 byte
  49
  50 #define VRQ_I2C_READ                    0x81            // wValueL: i2c address; length: how much to read
  51
  52 #define VRQ_SPI_READ                    0x82            // wValue: optional header bytes
  53                                                         // wIndexH:     enables
  54                                                         // wIndexL:     format
  55                                                         // len: how much to read
  56
  57 // OUT commands
  58
  59 #define VRQ_SET_LED                     0x01            // wValueL off/on {0,1}; wIndexL: which {0,1}
  60
  61 #define VRQ_FPGA_LOAD                   0x02
  62 #  define       FL_BEGIN                        0       // wIndexL: begin fpga programming cycle.  stalls if trouble.
  63 #  define       FL_XFER                         1       // wIndexL: xfer up to 64 bytes of data
  64 #  define       FL_END                          2       // wIndexL: end programming cycle, check for success.
  65                                                         //          stalls endpoint if trouble.
  66
  67 #define VRQ_FPGA_WRITE_REG              0x03            // wIndexL: regno; data: 32-bit regval MSB first
  68 #define VRQ_FPGA_SET_RESET              0x04            // wValueL: {0,1}
  69 #define VRQ_FPGA_SET_TX_ENABLE          0x05            // wValueL: {0,1}
  70 #define VRQ_FPGA_SET_RX_ENABLE          0x06            // wValueL: {0,1}
  71 // see below VRQ_FPGA_SET_{TX,RX}_RESET
  72
  73 #define VRQ_SET_SLEEP_BITS              0x07            // wValueH: mask; wValueL: bits.  set bits given by mask to bits
  74
  75 #  define       SLEEP_ADC0                      0x01
  76 #  define       SLEEP_ADC1                      0x02
  77 #  define       SLEEP_DAC0                      0x04
  78 #  define       SLEEP_DAC1                      0x08
  79
  80 #define VRQ_I2C_WRITE                   0x08            // wValueL: i2c address; data: data
  81
  82 #define VRQ_SPI_WRITE                   0x09            // wValue: optional header bytes
  83                                                         // wIndexH:     enables
  84                                                         // wIndexL:     format
  85                                                         // len: how much to write
  86
  87 #define VRQ_FPGA_SET_TX_RESET           0x0a            // wValueL: {0, 1}
  88 #define VRQ_FPGA_SET_RX_RESET           0x0b            // wValueL: {0, 1}
  89
  90
  91 // -------------------------------------------------------------------
  92 // we store the hashes at fixed addresses in the FX2 internal memory
  93
  94 #define   USRP_HASH_SLOT_0_ADDR                 0xe1e0
  95 #define   USRP_HASH_SLOT_1_ADDR                 0xe1f0
  96
  97
  98
  99 #endif /* _USRP_COMMANDS_H_ */