3 * Copyright 2003,2004,2006 Free Software Foundation, Inc.
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22 #ifndef INCLUDED_FPGA_REGS_STANDARD_H
23 #define INCLUDED_FPGA_REGS_STANDARD_H
25 // Register numbers 0 to 31 are reserved for use in fpga_regs_common.h.
26 // Registers 64 to 79 are available for custom FPGA builds.
31 #define FR_INTERP_RATE 32 // [1,1024]
32 #define FR_DECIM_RATE 33 // [1,256]
36 #define FR_RX_FREQ_0 34
37 #define FR_RX_FREQ_1 35
38 #define FR_RX_FREQ_2 36
39 #define FR_RX_FREQ_3 37
41 // See below for DDC Starting Phase
43 // ------------------------------------------------------------------------
44 // configure FPGA Rx mux
47 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
48 // +-----------------------+-------+-------+-------+-------+-+-----+
49 // | must be zero | Q3| I3| Q2| I2| Q1| I1| Q0| I0|Z| NCH |
50 // +-----------------------+-------+-------+-------+-------+-+-----+
52 // There are a maximum of 4 digital downconverters in the the FPGA.
53 // Each DDC has two 16-bit inputs, I and Q, and two 16-bit outputs, I & Q.
55 // DDC I inputs are specified by the two bit fields I3, I2, I1 & I0
57 // 0 = DDC input is from ADC 0
58 // 1 = DDC input is from ADC 1
59 // 2 = DDC input is from ADC 2
60 // 3 = DDC input is from ADC 3
62 // If Z == 1, all DDC Q inputs are set to zero
63 // If Z == 0, DDC Q inputs are specified by the two bit fields Q3, Q2, Q1 & Q0
65 // NCH specifies the number of complex channels that are sent across
66 // the USB. The legal values are 1, 2 or 4, corresponding to 2, 4 or
71 // ------------------------------------------------------------------------
72 // configure FPGA Tx Mux.
75 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
76 // +-----------------------+-------+-------+-------+-------+-+-----+
77 // | | DAC3 | DAC2 | DAC1 | DAC0 |0| NCH |
78 // +-----------------------------------------------+-------+-+-----+
80 // NCH specifies the number of complex channels that are sent across
81 // the USB. The legal values are 1 or 2, corresponding to 2 or 4
84 // There are two interpolators with complex inputs and outputs.
85 // There are four DACs. (We use the DUC in each AD9862.)
87 // Each 4-bit DACx field specifies the source for the DAC and
88 // whether or not that DAC is enabled. Each subfield is coded
96 // Where E is set if the DAC is enabled, and N specifies which
97 // interpolator output is connected to this DAC.
99 // N which interp output
100 // --- -------------------
108 // ------------------------------------------------------------------------
111 // Control whether a reference clock is sent to the daughterboards,
112 // and what frequency. The refclk is sent on d'board i/o pin 0.
115 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
116 // +-----------------------------------------------+-+------------+
117 // | Reserved (Must be zero) |E| DIVISOR |
118 // +-----------------------------------------------+-+------------+
121 // Bit 7 -- 1 turns on refclk, 0 allows IO use
122 // Bits 6:0 Divider value
124 #define FR_TX_A_REFCLK 40
125 #define FR_RX_A_REFCLK 41
126 #define FR_TX_B_REFCLK 42
127 #define FR_RX_B_REFCLK 43
129 # define bmFR_REFCLK_EN 0x80
130 # define bmFR_REFCLK_DIVISOR_MASK 0x7f
132 // ------------------------------------------------------------------------
133 // DDC Starting Phase
135 #define FR_RX_PHASE_0 44
136 #define FR_RX_PHASE_1 45
137 #define FR_RX_PHASE_2 46
138 #define FR_RX_PHASE_3 47
140 // ------------------------------------------------------------------------
141 // Tx data format control register
144 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
145 // +-------------------------------------------------------+-------+
146 // | Reserved (Must be zero) | FMT |
147 // +-------------------------------------------------------+-------+
151 #define FR_TX_FORMAT 48
152 # define bmFR_TX_FORMAT_16_IQ 0 // 16-bit I, 16-bit Q
154 // ------------------------------------------------------------------------
155 // Rx data format control register
158 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
159 // +-----------------------------------------+-+-+---------+-------+
160 // | Reserved (Must be zero) |B|Q| WIDTH | SHIFT |
161 // +-----------------------------------------+-+-+---------+-------+
165 #define FR_RX_FORMAT 49
167 # define bmFR_RX_FORMAT_SHIFT_MASK (0x0f << 0) // arithmetic right shift [0, 15]
168 # define bmFR_RX_FORMAT_SHIFT_SHIFT 0
169 # define bmFR_RX_FORMAT_WIDTH_MASK (0x1f << 4) // data width in bits [1, 16] (not all valid)
170 # define bmFR_RX_FORMAT_WIDTH_SHIFT 4
171 # define bmFR_RX_FORMAT_WANT_Q (0x1 << 9) // deliver both I & Q, else just I
172 # define bmFR_RX_FORMAT_BYPASS_HB (0x1 << 10) // bypass half-band filter
174 // The valid combinations currently are:
181 // Possible future values of WIDTH = {4, 2, 1}
182 // 12 takes a bit more work, since we need to know packet alignment.
184 // ------------------------------------------------------------------------
185 // FIXME register numbers 50 to 63 are available
187 // ------------------------------------------------------------------------
188 // Registers 64 to 79 are reserved for user custom FPGA builds.
189 // The standard USRP software will not touch these.
201 #define FR_USER_10 74
202 #define FR_USER_11 75
203 #define FR_USER_12 76
204 #define FR_USER_13 77
205 #define FR_USER_14 78
206 #define FR_USER_15 79
208 //Registers needed for multi usrp master/slave configuration
210 //Rx Master/slave control register (FR_RX_MASTER_SLAVE = FR_USER_0)
212 #define FR_RX_MASTER_SLAVE 64
213 #define bitnoFR_RX_SYNC 0
214 #define bitnoFR_RX_SYNC_MASTER 1
215 #define bitnoFR_RX_SYNC_SLAVE 2
216 # define bmFR_RX_SYNC (1 <<bitnoFR_RX_SYNC) //1 If this is a master "sync now" and send sync to slave.
217 // If this is a slave "sync now" (testing purpose only)
218 // Sync is allmost the same as reset (clear all counters and buffers)
219 // except that the io outputs and settings don't get reset (otherwise it couldn't send the sync to the slave)
222 # define bmFR_RX_SYNC_MASTER (1 <<bitnoFR_RX_SYNC_MASTER) //1 This is a rx sync master, output sync_rx on rx_a_io[15]
223 //0 This is not a rx sync master
224 # define bmFR_RX_SYNC_SLAVE (1 <<bitnoFR_RX_SYNC_SLAVE) //1 This is a rx sync slave, follow sync_rx on rx_a_io[bitnoFR_RX_SYNC_INPUT_IOPIN]
225 //0 This is not an rx sync slave.
227 //Caution The master settings will output values on the io lines.
228 //They inheritely enable these lines as output. If you have a daughtercard which uses these lines also as output then you will burn your usrp and daughtercard.
229 //If you set the slave bits then your usrp won't do anything if you don't connect a master.
230 // Rx Master/slave control register
232 // The way this is supposed to be used is connecting a (short) 16pin flatcable from an rx daughterboard in RXA master io_rx[8..15] to slave io_rx[8..15] on RXA of slave usrp
233 // This can be done with basic_rx boards or dbsrx boards
234 //dbsrx: connect master-J25 to slave-J25
235 //basic rx: connect J25 to slave-J25
236 //CAUTION: pay attention to the lineup of your connector.
237 //The red line (pin1) should be at the same side of the daughterboards on master and slave.
238 //If you turnaround the cable on one end you will burn your usrp.
240 //You cannot use a 16pin flatcable if you are using FLEX400 or FLEX2400 daughterboards, since these use a lot of the io pins.
241 //You can still link them but you must use only a 2pin or 1pin cable
242 //You can also use a 2-wire link. put a 2pin header on io[15],gnd of the master RXA daughterboard and connect it to io15,gnd of the slave RXA db.
243 //You can use a cable like the ones found with the leds on the mainbord of a PC.
244 //Make sure you don't twist the cable, otherwise you connect the sync output to ground.
245 //To be save you could also just use a single wire from master io[15] to slave io[15], but this is not optimal for signal integrity.
248 // Since rx_io[0] can normally be used as a refclk and is not exported on all daughterboards this line
249 // still has the refclk function if you use the master/slave setup (it is not touched by the master/slave settings).
250 // The master/slave circuitry will only use io pin 15 and does not touch any of the other io pins.
251 #define bitnoFR_RX_SYNC_INPUT_IOPIN 15
252 #define bmFR_RX_SYNC_INPUT_IOPIN (1<<bitnoFR_RX_SYNC_INPUT_IOPIN)
253 //TODO the output pin is still hardcoded in the verilog code, make it listen to the following define
254 #define bitnoFR_RX_SYNC_OUTPUT_IOPIN 15
255 #define bmFR_RX_SYNC_OUTPUT_IOPIN (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN)
256 // =======================================================================
257 // READBACK Registers
258 // =======================================================================
260 #define FR_RB_IO_RX_A_IO_TX_A 1 // read back a-side i/o pins
261 #define FR_RB_IO_RX_B_IO_TX_B 2 // read back b-side i/o pins
263 // ------------------------------------------------------------------------
264 // FPGA Capability register
267 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
268 // +-----------------------------------------------+-+-----+-+-----+
269 // | Reserved (Must be zero) |T|NDUC |R|NDDC |
270 // +-----------------------------------------------+-+-----+-+-----+
272 // Bottom 4-bits are Rx capabilities
273 // Next 4-bits are Tx capabilities
276 # define bmFR_RB_CAPS_NDDC_MASK (0x7 << 0) // # of digital down converters 0,1,2,4
277 # define bmFR_RB_CAPS_NDDC_SHIFT 0
278 # define bmFR_RB_CAPS_RX_HAS_HALFBAND (0x1 << 3)
279 # define bmFR_RB_CAPS_NDUC_MASK (0x7 << 4) // # of digital up converters 0,1,2
280 # define bmFR_RB_CAPS_NDUC_SHIFT 4
281 # define bmFR_RB_CAPS_TX_HAS_HALFBAND (0x1 << 7)
284 #endif /* INCLUDED_FPGA_REGS_STANDARD_H */