Imported Upstream version 3.2.2
[debian/gnuradio] / gr-radar-mono / src / fpga / lib / fifo32_2k.v
1 // megafunction wizard: %FIFO%\r
2 // GENERATION: STANDARD\r
3 // VERSION: WM1.0\r
4 // MODULE: scfifo \r
5 \r
6 // ============================================================\r
7 // File Name: fifo32_2k.v\r
8 // Megafunction Name(s):\r
9 //                      scfifo\r
10 //\r
11 // Simulation Library Files(s):\r
12 //                      altera_mf\r
13 // ============================================================\r
14 // ************************************************************\r
15 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
16 //\r
17 // 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition\r
18 // ************************************************************\r
19 \r
20 \r
21 //Copyright (C) 1991-2007 Altera Corporation\r
22 //Your use of Altera Corporation's design tools, logic functions \r
23 //and other software and tools, and its AMPP partner logic \r
24 //functions, and any output files from any of the foregoing \r
25 //(including device programming or simulation files), and any \r
26 //associated documentation or information are expressly subject \r
27 //to the terms and conditions of the Altera Program License \r
28 //Subscription Agreement, Altera MegaCore Function License \r
29 //Agreement, or other applicable license agreement, including, \r
30 //without limitation, that your use is for the sole purpose of \r
31 //programming logic devices manufactured by Altera and sold by \r
32 //Altera or its authorized distributors.  Please refer to the \r
33 //applicable agreement for further details.\r
34 \r
35 \r
36 // synopsys translate_off\r
37 `timescale 1 ps / 1 ps\r
38 // synopsys translate_on\r
39 module fifo32_2k (\r
40         clock,\r
41         data,\r
42         rdreq,\r
43         sclr,\r
44         wrreq,\r
45         empty,\r
46         q);\r
47 \r
48         input     clock;\r
49         input   [31:0]  data;\r
50         input     rdreq;\r
51         input     sclr;\r
52         input     wrreq;\r
53         output    empty;\r
54         output  [31:0]  q;\r
55 \r
56         wire  sub_wire0;\r
57         wire [31:0] sub_wire1;\r
58         wire  empty = sub_wire0;\r
59         wire [31:0] q = sub_wire1[31:0];\r
60 \r
61         scfifo  scfifo_component (\r
62                                 .rdreq (rdreq),\r
63                                 .sclr (sclr),\r
64                                 .clock (clock),\r
65                                 .wrreq (wrreq),\r
66                                 .data (data),\r
67                                 .empty (sub_wire0),\r
68                                 .q (sub_wire1)\r
69                                 // synopsys translate_off\r
70                                 ,\r
71                                 .aclr (),\r
72                                 .almost_empty (),\r
73                                 .almost_full (),\r
74                                 .full (),\r
75                                 .usedw ()\r
76                                 // synopsys translate_on\r
77                                 );\r
78         defparam\r
79                 scfifo_component.add_ram_output_register = "OFF",\r
80                 scfifo_component.intended_device_family = "Cyclone",\r
81                 scfifo_component.lpm_numwords = 2048,\r
82                 scfifo_component.lpm_showahead = "OFF",\r
83                 scfifo_component.lpm_type = "scfifo",\r
84                 scfifo_component.lpm_width = 32,\r
85                 scfifo_component.lpm_widthu = 11,\r
86                 scfifo_component.overflow_checking = "OFF",\r
87                 scfifo_component.underflow_checking = "OFF",\r
88                 scfifo_component.use_eab = "ON";\r
89 \r
90 \r
91 endmodule\r
92 \r
93 // ============================================================\r
94 // CNX file retrieval info\r
95 // ============================================================\r
96 // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"\r
97 // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"\r
98 // Retrieval info: PRIVATE: AlmostFull NUMERIC "0"\r
99 // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"\r
100 // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"\r
101 // Retrieval info: PRIVATE: Clock NUMERIC "0"\r
102 // Retrieval info: PRIVATE: Depth NUMERIC "2048"\r
103 // Retrieval info: PRIVATE: Empty NUMERIC "1"\r
104 // Retrieval info: PRIVATE: Full NUMERIC "0"\r
105 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
106 // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"\r
107 // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"\r
108 // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"\r
109 // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"\r
110 // Retrieval info: PRIVATE: Optimize NUMERIC "2"\r
111 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
112 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"\r
113 // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"\r
114 // Retrieval info: PRIVATE: UsedW NUMERIC "0"\r
115 // Retrieval info: PRIVATE: Width NUMERIC "32"\r
116 // Retrieval info: PRIVATE: dc_aclr NUMERIC "0"\r
117 // Retrieval info: PRIVATE: diff_widths NUMERIC "0"\r
118 // Retrieval info: PRIVATE: msb_usedw NUMERIC "0"\r
119 // Retrieval info: PRIVATE: output_width NUMERIC "32"\r
120 // Retrieval info: PRIVATE: rsEmpty NUMERIC "1"\r
121 // Retrieval info: PRIVATE: rsFull NUMERIC "0"\r
122 // Retrieval info: PRIVATE: rsUsedW NUMERIC "0"\r
123 // Retrieval info: PRIVATE: sc_aclr NUMERIC "0"\r
124 // Retrieval info: PRIVATE: sc_sclr NUMERIC "1"\r
125 // Retrieval info: PRIVATE: wsEmpty NUMERIC "0"\r
126 // Retrieval info: PRIVATE: wsFull NUMERIC "1"\r
127 // Retrieval info: PRIVATE: wsUsedW NUMERIC "0"\r
128 // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"\r
129 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
130 // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"\r
131 // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"\r
132 // Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"\r
133 // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"\r
134 // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"\r
135 // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"\r
136 // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"\r
137 // Retrieval info: CONSTANT: USE_EAB STRING "ON"\r
138 // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock\r
139 // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]\r
140 // Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty\r
141 // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]\r
142 // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq\r
143 // Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr\r
144 // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq\r
145 // Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0\r
146 // Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0\r
147 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0\r
148 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0\r
149 // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0\r
150 // Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0\r
151 // Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0\r
152 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
153 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.v TRUE\r
154 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.inc FALSE\r
155 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.cmp FALSE\r
156 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.bsf FALSE\r
157 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_inst.v FALSE\r
158 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_bb.v FALSE\r
159 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_waveforms.html FALSE\r
160 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_wave*.jpg FALSE\r
161 // Retrieval info: LIB_FILE: altera_mf\r