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  41 #ifndef _SPU_MUTEX_H_
  42 #define _SPU_MUTEX_H_           1
  43
  44 #include "sync_utils.h"
  45 #include "sync_irq.h"
  46 #include <spu_mfcio.h>
  47
  48 typedef eaddr_t mutex_ea_t;
  49
  50 #define DECL_MUTEX_VARS()                               \
  51     char _tmp[256];                                     \
  52     char *tmp = (char *) ALIGN(_tmp, 128);              \
  53     volatile s32 *buf = (volatile s32 *) &tmp[0];       \
  54     u32 size = 128, tagid = 0;                          \
  55     u32 offset;                                         \
  56     addr64 ea64
  57
  58 /* RAW_TEST_AND_SET
  59  *    Macro implementing the test and set primitive.
  60  *
  61  *    RAW_TEST_AND_SET(==, 1)   used by spin_try_lock()
  62  *    RAW_TEST_AND_SET(>=, 1)   used by read_try_lock()
  63  *    RAW_TEST_AND_SET(==, -1)  used by write_try_lock()
  64  */
  65 #define RAW_TEST_AND_SET(_RELOP_, _val)                         \
  66     ea64.ull = ALIGN128_EA(ea);                                 \
  67     offset = OFFSET128_EA_U32(ea);                              \
  68     do {                                                        \
  69         MFC_DMA(buf, ea64, size, tagid, MFC_GETLLAR_CMD);       \
  70         spu_readch(MFC_RdAtomicStat);                           \
  71         SET_HIT;                                                \
  72         if (likely(buf[offset] _RELOP_ 0)) {                    \
  73             buf[offset] += _val;                                \
  74             MFC_DMA(buf, ea64, size, tagid, MFC_PUTLLC_CMD);    \
  75             status = spu_readch(MFC_RdAtomicStat);              \
  76             ret_val = 1;                                        \
  77         } else {                                                \
  78             MFC_DMA(buf, ea64, size, tagid, MFC_PUTLLC_CMD);    \
  79             spu_readch(MFC_RdAtomicStat);                       \
  80             status = ret_val = 0;                               \
  81             break;                                              \
  82         }                                                       \
  83     } while (status != 0)
  84
  85 /* RAW_SPINLOCK
  86  *    Macro implementing the spinlock primitive.
  87  *
  88  *    RAW_SPINLOCK(==, 1)       used by spin_lock()
  89  *    RAW_SPINLOCK(>=, 1)       used by read_lock()
  90  *    RAW_SPINLOCK(==, -1)      used by write_lock()
  91  */
  92
  93
  94 #define RAW_SPINLOCK(_RELOP_, _val)                             \
  95     ea64.ull = ALIGN128_EA(ea);                                 \
  96     offset = OFFSET128_EA_U32(ea);                              \
  97     do {                                                        \
  98         MFC_DMA(buf, ea64, size, tagid, MFC_GETLLAR_CMD);       \
  99         spu_readch(MFC_RdAtomicStat);                           \
 100         SET_HIT;                                                \
 101         status = 1;                                             \
 102         if (likely(buf[offset] _RELOP_ 0)) {                    \
 103             buf[offset] += _val;                                \
 104             MFC_DMA(buf, ea64, size, tagid, MFC_PUTLLC_CMD);    \
 105             status = spu_readch(MFC_RdAtomicStat);              \
 106         }                                                       \
 107     } while (status != 0);
 108
 109
 110 static inline void _lock_init(eaddr_t ea)
 111 {
 112     DECL_MUTEX_VARS();
 113     u32 oldtmask, tagmask;
 114
 115     tagid = mfc_tag_reserve();
 116
 117     tagmask = 1 << (tagid & 31);
 118
 119     /* __lock_init
 120      *    Internal routine to initialize a spinlock or
 121      *    reader/writer lock.
 122      */
 123     ea64.ull = ALIGN128_EA(ea);
 124     offset = OFFSET128_EA_U32(ea);
 125     MFC_DMA(buf, ea64, size, tagid & 31, MFC_GET_CMD);
 126     oldtmask = spu_readch(MFC_RdTagMask);
 127     spu_writech(MFC_WrTagMask, tagmask);
 128     spu_writech(MFC_WrTagUpdate, MFC_TAG_UPDATE_ANY);
 129     spu_readch(MFC_RdTagStat);
 130
 131     buf[offset] = 0;
 132     MFC_DMA(buf, ea64, size, tagid & 31, MFC_PUT_CMD);
 133     spu_writech(MFC_WrTagMask, tagmask);
 134     spu_writech(MFC_WrTagUpdate, MFC_TAG_UPDATE_ANY);
 135     spu_readch(MFC_RdTagStat);
 136     spu_writech(MFC_WrTagMask, oldtmask);
 137     mfc_tag_release(tagid);
 138 }
 139
 140 static inline void _spin_lock(eaddr_t ea)
 141 {
 142     DECL_MUTEX_VARS();
 143     s32 status;
 144
 145     /* _spin_lock
 146      *    Internal routine to acquire spinlock.
 147      */
 148 /* non trace - no hit/miss indicator */
 149 #define SET_HIT
 150     RAW_SPINLOCK(==, 1);
 151 }
 152
 153 #ifdef LIBSYNC_TRACE
 154 static inline s32 _spin_lock_trace(eaddr_t ea)
 155 {
 156     DECL_MUTEX_VARS();
 157     s32 status = 0;
 158 /* trace - need hit/miss indicator */
 159 #undef SET_HIT
 160 #define SET_HIT if (status == 0) hit = buf[offset]
 161     s32 hit;
 162
 163     hit = 0;
 164     /* _spin_lock_trace for trace
 165      *    Internal routine to acquire spinlock.
 166      */
 167     RAW_SPINLOCK(==, 1);
 168
 169     return hit;
 170
 171 #undef SET_HIT
 172 #define SET_HIT
 173 }
 174
 175 #endif /* LIBSYNC_TRACE */
 176
 177
 178 #endif /* SPU_MUTEX_H */