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   1 /*
   2  * Simulator of microcontrollers (interrupt.cc)
   3  *
   4  * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
   5  *
   6  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
   7  *
   8  */
   9
  10 /* This file is part of microcontroller simulator: ucsim.
  11
  12 UCSIM is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2 of the License, or
  15 (at your option) any later version.
  16
  17 UCSIM is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with UCSIM; see the file COPYING.  If not, write to the Free
  24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  25 02111-1307, USA. */
  26 /*@1@*/
  27
  28 // prj
  29 #include "utils.h"
  30
  31 // sim
  32 #include "itsrccl.h"
  33
  34 // local
  35 #include "interruptcl.h"
  36 #include "regs51.h"
  37 //#include "uc51cl.h"
  38 #include "types51.h"
  39
  40
  41 cl_interrupt::cl_interrupt(class cl_uc *auc):
  42   cl_hw(auc, HW_INTERRUPT, 0, "irq")
  43 {
  44   was_reti= DD_FALSE;
  45 }
  46
  47 int
  48 cl_interrupt::init(void)
  49 {
  50   sfr= uc->address_space(MEM_SFR_ID);
  51   if (sfr)
  52     {
  53       //sfr->register_hw(IE, this, 0);
  54       register_cell(sfr, IE, 0, wtd_restore);
  55       register_cell(sfr, TCON, &cell_tcon, wtd_restore_write);
  56       bit_INT0= sfr->read(P3) & bm_INT0;
  57       bit_INT1= sfr->read(P3) & bm_INT1;
  58     }
  59   return(0);
  60 }
  61
  62 void
  63 cl_interrupt::added_to_uc(void)
  64 {
  65   uc->it_sources->add(new cl_it_src(bmEX0, TCON, bmIE0, 0x0003, true,
  66                                     "external #0", 1));
  67   uc->it_sources->add(new cl_it_src(bmEX1, TCON, bmIE1, 0x0013, true,
  68                                     "external #1", 3));
  69 }
  70
  71 void
  72 cl_interrupt::write(class cl_memory_cell *cell, t_mem *val)
  73 {
  74   if (cell == cell_tcon)
  75     {
  76       bit_IT0= *val & bmIT0;
  77       bit_IT1= *val & bmIT1;
  78     }
  79   else
  80     // IE register
  81     was_reti= DD_TRUE;
  82 }
  83
  84 /*void
  85 cl_interrupt::mem_cell_changed(class cl_m *mem, t_addr addr)
  86 {
  87 }*/
  88
  89 int
  90 cl_interrupt::tick(int cycles)
  91 {
  92   if (!bit_IT0 && !bit_INT0)
  93     cell_tcon->set_bit1(bmIE0);
  94   if (!bit_IT1 && !bit_INT1)
  95     cell_tcon->set_bit1(bmIE1);
  96   return(resGO);
  97 }
  98
  99 void
 100 cl_interrupt::reset(void)
 101 {
 102   was_reti= DD_FALSE;
 103 }
 104
 105 void
 106 cl_interrupt::happen(class cl_hw *where, enum hw_event he, void *params)
 107 {
 108   struct ev_port_changed *ep= (struct ev_port_changed *)params;
 109
 110   if (where->cathegory == HW_PORT &&
 111       he == EV_PORT_CHANGED &&
 112       ep->id == 3)
 113     {
 114       t_mem p3n= ep->new_pins & ep->new_value;
 115       t_mem p3o= ep->pins & ep->prev_value;
 116       if (bit_IT0 &&
 117           !(p3n & bm_INT0) &&
 118           (p3o & bm_INT0))
 119         cell_tcon->set_bit1(bmIE0);
 120       if (bit_IT1 &&
 121           !(p3n & bm_INT1) &&
 122           (p3o & bm_INT1))
 123         cell_tcon->set_bit1(bmIE1);
 124       bit_INT0= p3n & bm_INT0;
 125       bit_INT1= p3n & bm_INT1;
 126     }
 127 }
 128
 129
 130 void
 131 cl_interrupt::print_info(class cl_console_base *con)
 132 {
 133   int ie= sfr->get(IE);
 134   int i;
 135
 136   con->dd_printf("Interrupts are %s. Interrupt sources:\n",
 137                  (ie&bmEA)?"enabled":"disabled");
 138   con->dd_printf("  Handler  En  Pr Req Act Name\n");
 139   for (i= 0; i < uc->it_sources->count; i++)
 140     {
 141       class cl_it_src *is= (class cl_it_src *)(uc->it_sources->at(i));
 142       con->dd_printf("  0x%06x", is->addr);
 143       con->dd_printf(" %-3s", (ie&(is->ie_mask))?"en":"dis");
 144       con->dd_printf(" %2d", uc->it_priority(is->ie_mask));
 145       con->dd_printf(" %-3s",
 146                      (sfr->get(is->src_reg)&(is->src_mask))?
 147                      "YES":"no");
 148       con->dd_printf(" %-3s", (is->active)?"act":"no");
 149       con->dd_printf(" %s", object_name(is));
 150       con->dd_printf("\n");
 151     }
 152   con->dd_printf("Active interrupt service(s):\n");
 153   con->dd_printf("  Pr Handler  PC       Source\n");
 154   for (i= 0; i < uc->it_levels->count; i++)
 155     {
 156       class it_level *il= (class it_level *)(uc->it_levels->at(i));
 157       if (il->level >= 0)
 158         {
 159           con->dd_printf("  %2d", il->level);
 160           con->dd_printf(" 0x%06x", il->addr);
 161           con->dd_printf(" 0x%06x", il->PC);
 162           con->dd_printf(" %s", (il->source)?(object_name(il->source)):
 163                          "nothing");
 164           con->dd_printf("\n");
 165         }
 166     }
 167 }
 168
 169
 170 /* End of s51.src/interrupt.cc */