1 /*-------------------------------------------------------------------------
\r
2 Register Declarations for ST's uPSD33xx "Fast 8032 MCU with Programmable Logic"
\r
3 (Based on preliminary datasheet from Jan/2005 )
\r
5 Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (May 2007)
\r
7 This library is free software; you can redistribute it and/or
\r
8 modify it under the terms of the GNU Lesser General Public
\r
9 License as published by the Free Software Foundation; either
\r
10 version 2.1 of the License, or (at your option); any later version
\r
12 This library is distributed in the hope that it will be useful,
\r
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
\r
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
\r
15 Lesser General Public License for more details
\r
17 You should have received a copy of the GNU Lesser General Public
\r
18 License along with this library; if not, write to the Free Software
\r
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
\r
21 In other words, you are welcome to use, share and improve this program
\r
22 You are forbidden to forbid anyone else to use, share and improve
\r
23 what you give them. Help stamp out software-hoarding!
\r
24 -------------------------------------------------------------------------*/
\r
25 #ifndef REG_UPSD33XX_H
\r
26 #define REG_UPSD33XX_H
\r
28 #include <compiler.h>
\r
30 //Interrupt vector numbers (see table 16 on datasheet)
\r
31 #define EXT0_INTERRUPT ((0x03-3)/8)
\r
32 #define TIMER0_INTERRUPT ((0x0B-3)/8)
\r
33 #define EXT1_INTERRUPT ((0x13-3)/8)
\r
34 #define TIMER1_INTERRUPT ((0x1B-3)/8)
\r
35 #define UART0_INTERRUPT ((0x23-3)/8)
\r
36 #define TIMER2_INTERRUPT ((0x2B-3)/8)
\r
37 #define TX2_INTERRUPT ((0x2B-3)/8)
\r
38 #define SPI_INTERRUPT ((0x53-3)/8)
\r
39 #define I2C_INTERRUPT ((0x43-3)/8)
\r
40 #define ADC_INTERRUPT ((0x3B-3)/8)
\r
41 #define PCA_INTERRUPT ((0x5B-3)/8)
\r
42 #define UART1_INTERRUPT ((0x4B-3)/8)
\r
44 SFR(SP, 0x81); // Stack Pointer.
\r
45 SFR(DPL, 0x82); // Data Pointer Low.
\r
46 SFR(DPH, 0x83); // Data Pointer High.
\r
48 SFR(DPTC, 0x85); // Data Pointer Control Register.
\r
49 SFR(DPS, 0x85); // Data Pointer Control Register alias for SDCC
\r
50 #define AT 0x40 //0:Manually Select Data Pointer / 1:Auto Toggle between DPTR0 and DPTR1
\r
51 #define DPSE0 0x01 // 0:DPTR0 Selected for use as DPTR / 1:DPTR1 Selected for use as DPTR
\r
53 SFR(DPTM, 0x86); // Data Pointer Mode Register.
\r
54 #define DP1_1 0x08 // DPTR1 Mode Bit 1.
\r
55 #define DP1_0 0x04 // DPTR1 Mode Bit 0.
\r
56 #define DP0_1 0x02 // DPTR0 Mode Bit 1.
\r
57 #define DP0_0 0x01 // DPTR0 Mode Bit 0.
\r
59 // 0 0 : DPTRx No Change
\r
61 // 1 0 : DPTRx Auto Increment
\r
62 // 1 1 : DPTRx Auto Decrement
\r
64 SFR(PCON, 0x87); // Power Control.
\r
65 #define SMOD0 0x80 //Baud Rate Double Bit (UART0)
\r
66 #define SMOD1 0x40 //Baud Rate Double Bit (UART1)
\r
67 #define POR 0x10 //Only a power-on reset sets this bit (cold reset).
\r
68 #define RCLK1 0x08 //Receive Clock Flag (UART1)
\r
69 #define TCLK1 0x04 //Transmit Clock Flag (UART1)
\r
70 #define PD 0x02 //Power-Down Mode Enable.
\r
71 #define IDL 0x01 //Idle Mode Enable.
\r
73 SFR(TCON, 0x88); // Timer/Counter Control.
\r
74 SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.
\r
75 SBIT(TR1, 0x88, 6); // Timer 1 run control flag.
\r
76 SBIT(TF0, 0x88, 5); // Timer 0 overflow flag.
\r
77 SBIT(TR0, 0x88, 4); // Timer 0 run control flag.
\r
78 SBIT(IE1, 0x88, 3); // Interrupt 1 flag.
\r
79 SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.
\r
80 SBIT(IE0, 0x88, 1); // Interrupt 0 flag.
\r
81 SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.
\r
83 SFR(TMOD, 0x89); // Timer/Counter Mode Control.
\r
84 #define GATE1 0x80 // External enable for timer 1.
\r
85 #define C_T1 0x40 // Timer or counter select for timer 1.
\r
86 #define M1_1 0x20 // Operation mode bit 1 for timer 1.
\r
87 #define M0_1 0x10 // Operation mode bit 0 for timer 1.
\r
88 #define GATE0 0x08 // External enable for timer 0.
\r
89 #define C_T0 0x04 // Timer or counter select for timer 0.
\r
90 #define M1_0 0x02 // Operation mode bit 1 for timer 0.
\r
91 #define M0_0 0x01 // Operation mode bit 0 for timer 0.
\r
93 SFR(TL0, 0x8A); // Timer 0 LSB.
\r
94 SFR(TL1, 0x8B); // Timer 1 LSB.
\r
95 SFR(TH0, 0x8C); // Timer 0 MSB.
\r
96 SFR(TH1, 0x8D); // Timer 1 MSB.
\r
98 //For P1SFS0 and P1SFS1 SFRs details check datasheet Table 31.
\r
99 SFR(P1SFS0, 0x8E); //Port 1 Special Function Select 0 Register.
\r
100 #define P1SF07 0x80
\r
101 #define P1SF06 0x40
\r
102 #define P1SF05 0x20
\r
103 #define P1SF04 0x10
\r
104 #define P1SF03 0x08
\r
105 #define P1SF02 0x04
\r
106 #define P1SF01 0x02
\r
107 #define P1SF00 0x01
\r
108 SFR(P1SFS1, 0x8F); //Port 1 Special Function Select 1 Register.
\r
109 #define P1SF17 0x80
\r
110 #define P1SF16 0x40
\r
111 #define P1SF15 0x20
\r
112 #define P1SF14 0x10
\r
113 #define P1SF13 0x08
\r
114 #define P1SF12 0x04
\r
115 #define P1SF11 0x02
\r
116 #define P1SF10 0x01
\r
118 SFR(P1, 0x90); // Port 1
\r
119 SBIT(P1_0, 0x90, 0); // Port 1 bit 0.
\r
120 SBIT(P1_1, 0x90, 1); // Port 1 bit 1.
\r
121 SBIT(P1_2, 0x90, 2); // Port 1 bit 2.
\r
122 SBIT(P1_3, 0x90, 3); // Port 1 bit 3.
\r
123 SBIT(P1_4, 0x90, 4); // Port 1 bit 4.
\r
124 SBIT(P1_5, 0x90, 5); // Port 1 bit 5.
\r
125 SBIT(P1_6, 0x90, 6); // Port 1 bit 6.
\r
126 SBIT(P1_7, 0x90, 7); // Port 1 bit 7.
\r
127 //Alternate names (from figure 3)
\r
128 SBIT(T2, 0x90, 0); //Input to Timer/Counter 2.
\r
129 SBIT(T2X, 0x90, 1); //Capture/reload trigger for Counter 2.
\r
130 SBIT(RXD1, 0x90, 2);
\r
131 SBIT(TXD1, 0x90, 3);
\r
132 SBIT(SPICLK, 0x90, 4);
\r
133 SBIT(SPIRXD, 0x90, 5);
\r
134 SBIT(SPITXD, 0x90, 6);
\r
135 SBIT(SPISEL, 0x90, 7);
\r
137 SFR(P3SFS, 0x91); // Port 3 Special Function Select Register
\r
147 //For P4SFS0 and P4SFS1 SFRs details check datasheet Table 34.
\r
148 SFR(P4SFS0, 0x92); //Port 4 Special Function Select 0 Register.
\r
149 #define P4SF07 0x80
\r
150 #define P4SF06 0x40
\r
151 #define P4SF05 0x20
\r
152 #define P4SF04 0x10
\r
153 #define P4SF03 0x08
\r
154 #define P4SF02 0x04
\r
155 #define P4SF01 0x02
\r
156 #define P4SF00 0x01
\r
157 SFR(P4SFS1, 0x93); //Port 4 Special Function Select 1 Register.
\r
158 #define P4SF17 0x80
\r
159 #define P4SF16 0x40
\r
160 #define P4SF15 0x20
\r
161 #define P4SF14 0x10
\r
162 #define P4SF13 0x08
\r
163 #define P4SF12 0x04
\r
164 #define P4SF11 0x02
\r
165 #define P4SF10 0x01
\r
167 SFR(ADCPS, 0x94); // ADC pre-scaller?
\r
168 #define ADCCE 0x08 // ADC Conversion Reference Clock Enable.
\r
169 //ADC Reference Clock PreScaler. Only three Prescaler values are allowed:
\r
170 #define ADCPS2 0x02 // Resulting ADC clock is fOSC.
\r
171 #define ADCPS1 0x01 // Resulting ADC clock is fOSC/2.
\r
172 #define ADCPS0 0x00 // Resulting ADC clock is fOSC/4.
\r
174 SFR(ADAT0, 0x95); // A/D result register (bits 0 to 7).
\r
175 SFR(ADAT1, 0x96); // A/D result register (bits 8 and 9).
\r
176 SFR(ACON, 0x97); // A/D control register.
\r
177 #define AINTF 0x80 // ADC Interrupt flag. This bit must be cleared with software.
\r
178 #define AINTEN 0x40 // ADC Interrupt Enable.
\r
179 #define ADEN 0x20 // ADC Enable Bit.
\r
180 #define ADS2 0x10 // Analog channel Select bit 3.
\r
181 #define ADS1 0x08 // Analog channel Select bit 2.
\r
182 #define ADS0 0x04 // Analog channel Select bit 1.
\r
183 #define ADST 0x02 // ADC Start Bit.
\r
184 #define ADSF 0x01 // ADC Status Bit.
\r
186 SFR(SCON, 0x98); // For compatibity with legacy code
\r
187 SFR(SCON0, 0x98); // Serial Port UART0 Control Register
\r
188 SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
\r
189 SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
\r
190 SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
\r
191 SBIT(REN, 0x98, 4); // Enables serial reception.
\r
192 SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
\r
193 SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
\r
194 SBIT(TI, 0x98, 1); // Transmit interrupt flag.
\r
195 SBIT(RI, 0x98, 0); // Receive interrupt flag.
\r
197 SFR(SBUF, 0x99); // For compatibity with legacy code.
\r
198 SFR(SBUF0, 0x99); // Serial Port UART0 Data Buffer.
\r
200 SFR(BUSCON, 0x9D); // Bus Control Register.
\r
201 #define EPFQ 0x80 // Enable Pre-Fetch Queue.
\r
202 #define EBC 0x40 // Enable Branch Cache.
\r
203 #define WRW1 0x20 // WR Wait bit 2.
\r
204 #define WRW0 0x10 // WR Wait bit 1.
\r
205 #define RDW1 0x08 // RD Wait bit 2.
\r
206 #define RDW0 0x04 // RD Wait bit 1.
\r
207 #define CW1 0x02 // PSEN Wait bit 2.
\r
208 #define CW0 0x01 // PSEN Wait bit 1.
\r
210 SFR(PCACL0, 0xA2); // The low 8 bits of PCA 0 16-bit counter.
\r
211 SFR(PCACH0, 0xA3); // The high 8 bits of PCA 0 16-bit counter.
\r
212 SFR(PCACON0, 0xA4); // PCA 0 Control Register.
\r
213 SFR(PCASTA, 0xA5); // PCA 0 and PCA 1 Status Register.
\r
214 SFR(PCACL1, 0xBA); // The low 8 bits of PCA 1 16-bit counter.
\r
215 SFR(PCACH1, 0xBB); // The high 8 bits of PCA 1 16-bit counter.
\r
216 SFR(PCACON1, 0xBC); // PCA 1 Control Register.
\r
218 SFR(IEA, 0xA7); // Interrupt Enable Addition Register.
\r
219 #define EADC 0x80 // Enable ADC Interrupt.
\r
220 #define ESPI 0x40 // Enable SPI Interrupt.
\r
221 #define EPCA 0x20 // Enable Programmable Counter Array Interrupt.
\r
222 #define ES1 0x10 // Enable UART1 Interrupt.
\r
223 #define EI2C 0x02 // Enable I2C Interrupt.
\r
225 SFR(IE, 0xA8); // Interrupt Enable Register.
\r
226 SBIT(EA, 0xA8, 7); // Global disable bit.
\r
227 SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt.
\r
228 SBIT(ES0, 0xA8, 4); // Enable UART0 Interrupt.
\r
229 SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt.
\r
230 SBIT(EX1, 0xA8, 2); // Enable External Interrupt INT1.
\r
231 SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt.
\r
232 SBIT(EX0, 0xA8, 0); // Enable External Interrupt INT0.
\r
234 SFR(TCMMODE0, 0xA9); // TCM 0 Mode.
\r
235 SFR(TCMMODE1, 0xAA); // TCM 1 Mode.
\r
236 SFR(TCMMODE2, 0xAB); // TCM 2 Mode.
\r
237 SFR(TCMMODE3, 0xBD); // TCM 3 Mode.
\r
238 SFR(TCMMODE4, 0xBE); // TCM 4 Mode.
\r
239 SFR(TCMMODE5, 0xBF); // TCM 5 Mode.
\r
240 //These are the bits for the six SFRs above:
\r
241 #define EINTF 0x80 // Enable the interrupt flags (INTF) in the Status Register to generate an interrupt.
\r
242 #define E_COMP 0x40 // Enable the comparator when set.
\r
243 #define CAP_PE 0x20 // Enable Capture Mode, a positive edge on the CEXn pin.
\r
244 #define CAP_NE 0x20 // Enable Capture Mode, a negative edge on the CEXn pin.
\r
245 #define MATCH 0x08 // A match from the comparator sets the INTF bits in the Status Register.
\r
246 #define TOGGLE 0x04 // A match on the comparator results in a toggling output on CEXn pin.
\r
247 #define PWM1 0x02 // PWM mode bit 2.
\r
248 #define PWM0 0x01 // PWM mode bit 1.
\r
250 SFR(CAPCOML0, 0xAC); // Capture/Compare register low of TCM 0.
\r
251 SFR(CAPCOMH0, 0xAD); // Capture/Compare register High of TCM 0.
\r
252 SFR(CAPCOML1, 0xAF); // Capture/Compare register low of TCM 1.
\r
253 SFR(CAPCOMH1, 0xB1); // Capture/Compare register High of TCM 1.
\r
254 SFR(CAPCOML2, 0xB2); // Capture/Compare register low of TCM 2.
\r
255 SFR(CAPCOMH2, 0xB3); // Capture/Compare register High of TCM 2.
\r
256 SFR(CAPCOML3, 0xC1); // Capture/Compare register low of TCM 3.
\r
257 SFR(CAPCOMH3, 0xC2); // Capture/Compare register High of TCM 3.
\r
258 SFR(CAPCOML4, 0xC3); // Capture/Compare register low of TCM 4.
\r
259 SFR(CAPCOMH4, 0xC4); // Capture/Compare register High of TCM 4.
\r
260 SFR(CAPCOML5, 0xC5); // Capture/Compare register low of TCM 5.
\r
261 SFR(CAPCOMH5, 0xC6); // Capture/Compare register High of TCM 5.
\r
263 SFR(IPA, 0xB7); // Interrupt Priority Addition register.
\r
264 #define PADC 0x80 // ADC Interrupt priority level.
\r
265 #define PSPI 0x40 // SPI Interrupt priority level.
\r
266 #define PPCA 0x20 // PCA Interrupt level.
\r
267 #define PS1 0x10 // UART1 Interrupt priority.
\r
268 #define PI2C 0x02 // I2C Interrupt priority level.
\r
270 SFR(IP, 0xB8); // Interrupt Priority Register.
\r
271 SBIT(PT2, 0xB8, 5); // Timer 2 Interrupt priority level.
\r
272 SBIT(PS0, 0xB8, 4); // UART0 Interrupt priority level.
\r
273 SBIT(PT1, 0xB8, 3); // Timer 1 Interrupt priority level.
\r
274 SBIT(PX1, 0xB8, 2); // External Interrupt INT1 priority level.
\r
275 SBIT(PT0, 0xB8, 1); // Timer 0 Interrupt priority level.
\r
276 SBIT(PX0, 0xB8, 0); // External Interrupt INT0 priority level.
\r
278 SFR(WDTRST, 0xA6); // Watchdog Timer Reset Counter Register.
\r
279 SFR(WDTKEY, 0xAE); //Watchdog Timer Key Register.
\r
281 SFR(P3, 0xB0); // I/O Port 3 Register
\r
282 SBIT(P3_0, 0xB0, 0); // Port 3 bit 0.
\r
283 SBIT(P3_1, 0xB0, 1); // Port 3 bit 1.
\r
284 SBIT(P3_2, 0xB0, 2); // Port 3 bit 2.
\r
285 SBIT(P3_3, 0xB0, 3); // Port 3 bit 3.
\r
286 SBIT(P3_4, 0xB0, 4); // Port 3 bit 4.
\r
287 SBIT(P3_5, 0xB0, 5); // Port 3 bit 5.
\r
288 SBIT(P3_6, 0xB0, 6); // Port 3 bit 6.
\r
289 SBIT(P3_7, 0xB0, 7); // Port 3 bit 7.
\r
291 SFR(P4, 0xC0); // I/O Port 4 Register
\r
292 SBIT(P4_0, 0xC0, 0); // Port 4 bit 0.
\r
293 SBIT(P4_1, 0xC0, 1); // Port 4 bit 1.
\r
294 SBIT(P4_2, 0xC0, 2); // Port 4 bit 2.
\r
295 SBIT(P4_3, 0xC0, 3); // Port 4 bit 3.
\r
296 SBIT(P4_4, 0xC0, 4); // Port 4 bit 4.
\r
297 SBIT(P4_5, 0xC0, 5); // Port 4 bit 5.
\r
298 SBIT(P4_6, 0xC0, 6); // Port 4 bit 6.
\r
299 SBIT(P4_7, 0xC0, 7); // Port 4 bit 7.
\r
301 SFR(PWMF0, 0xB4); // PWM frequency register 0.
\r
302 SFR(PWMF1, 0xC7); // PWM frequency register 1.
\r
304 SFR(T2CON, 0xC8); // Timer / Counter 2 Control.
\r
305 SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag.
\r
306 SBIT(EXF2, 0xC8, 6); // Timer 2 external flag.
\r
307 SBIT(RCLK, 0xC8, 5); // Receive clock flag.
\r
308 SBIT(TCLK, 0xC8, 4); // Transmit clock flag.
\r
309 SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag.
\r
310 SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2.
\r
311 SBIT(CNT2, 0xC8, 1); // Timer or coutner select.
\r
312 SBIT(CAP2, 0xC8, 0); // Capture/reload flag.
\r
314 SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB.
\r
315 SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB.
\r
316 SFR(TL2, 0xCC); // Timer 2 LSB.
\r
317 SFR(TH2, 0xCD); // Timer 2 MSB.
\r
319 SFR(IRDACON, 0xCE); //IrDA control register
\r
320 #define IRDAEN 0x40 // IrDA Enable bit
\r
321 #define PULSE 0x20 // IrDA Pulse Modulation Select. 0: 1.627us, 1: 3/16 bit time pulses.
\r
322 #define CDIV4 0x10 //Specify Clock Divider bit 5.
\r
323 #define CDIV3 0x08 //Specify Clock Divider bit 4.
\r
324 #define CDIV2 0x04 //Specify Clock Divider bit 3.
\r
325 #define CDIV1 0x02 //Specify Clock Divider bit 2.
\r
326 #define CDIV0 0x01 //Specify Clock Divider bit 1.
\r
328 SFR(CCON0, 0xF9); // Clock Control Register.
\r
329 #define DBGCE 0x10 // Debug Unit Breakpoint Comparator Enable.
\r
330 #define CPUAR 0x08 // Automatic MCU Clock Recovery.
\r
331 #define CPUPS2 0x04 // MCUCLK Pre-Scaler bit 3.
\r
332 #define CPUPS1 0x02 // MCUCLK Pre-Scaler bit 2.
\r
333 #define CPUPS0 0x01 // MCUCLK Pre-Scaler bit 1.
\r
335 SFR(CCON2, 0xFB); // Pre-scaler value for PCA0.
\r
336 #define PCA0CE 0x10 // PCA0 Clock Enable.
\r
337 #define PCA0PS3 0x08 // PCA0 Pre-Scaler bit 4.
\r
338 #define PCA0PS2 0x04 // PCA0 Pre-Scaler bit 3.
\r
339 #define PCA0PS1 0x02 // PCA0 Pre-Scaler bit 2.
\r
340 #define PCA0PS0 0x01 // PCA0 Pre-Scaler bit 1.
\r
342 SFR(CCON3, 0xFC); // Pre-scaler value for PCA1.
\r
343 #define PCA1CE 0x10 // PCA1 Clock Enable.
\r
344 #define PCA1PS3 0x08 // PCA1 Pre-Scaler bit 4.
\r
345 #define PCA1PS2 0x04 // PCA1 Pre-Scaler bit 3.
\r
346 #define PCA1PS1 0x02 // PCA1 Pre-Scaler bit 2.
\r
347 #define PCA1PS0 0x01 // PCA1 Pre-Scaler bit 1.
\r
349 SFR(SPICLKD, 0xD2); // SPI Prescaler (Clock Divider) Register.
\r
350 #define DIV128 0x80
\r
357 SFR(SPISTAT, 0xD3); // SPI Interface Status Register.
\r
358 #define BUSY 0x10 // SPI Busy.
\r
359 #define TEISF 0x08 // Transmission End Interrupt Source flag.
\r
360 #define RORISF 0x04 // Receive Overrun Interrupt Source flag.
\r
361 #define TISF 0x02 // Transfer Interrupt Source flag.
\r
362 #define RISF 0x01 // Receive Interrupt Source flag.
\r
364 SFR(SPITDR, 0xD4); // SPI transmit data register.
\r
365 SFR(SPIRDR, 0xD5); // SPI receive data register.
\r
367 SFR(SPICON0, 0xD6); // SPI Control Register 0.
\r
368 #define TE 0x40 // Transmitter Enable.
\r
369 #define RE 0x20 // Receiver Enable.
\r
370 #define SPIEN 0x10 // SPI Enable.
\r
371 #define SSEL 0x08 // Slave Selection.
\r
372 #define FLSB 0x04 // First LSB.
\r
373 #define SPO 0x02 // Sampling Polarity.
\r
375 SFR(SPICON1, 0xD7); // SPI Interface Control Register 1.
\r
376 #define TEIE 0x08 // Transmission End Interrupt Enable.
\r
377 #define RORIE 0x04 // Receive Overrun Interrupt Enable.
\r
378 #define TIE 0x02 // Transmission Interrupt Enable.
\r
379 #define RIE 0x01 // Reception Interrupt Enable.
\r
381 SFR(SCON1, 0x98); // Serial Port Control.
\r
382 SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
\r
383 SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
\r
384 SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
\r
385 SBIT(REN, 0x98, 4); // Enables serial reception.
\r
386 SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
\r
387 SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
\r
388 SBIT(TI, 0x98, 1); // Transmit interrupt flag.
\r
389 SBIT(RI, 0x98, 0); // Receive interrupt flag.
\r
391 SFR(SBUF1, 0xD9); // Data buffer for UART1.
\r
392 SFR(S1SETUP, 0xDB); // I2C START Condition Sample Setup register.
\r
393 #define EN_SS 0x80 // Enable Sample Setup.
\r
394 #define SMPL_SET6 0x40 // Sample Setting bit 7.
\r
395 #define SMPL_SET5 0x20 // Sample Setting bit 6.
\r
396 #define SMPL_SET4 0x10 // Sample Setting bit 5.
\r
397 #define SMPL_SET3 0x08 // Sample Setting bit 4.
\r
398 #define SMPL_SET2 0x04 // Sample Setting bit 3.
\r
399 #define SMPL_SET1 0x02 // Sample Setting bit 2.
\r
400 #define SMPL_SET0 0x01 // Sample Setting bit 1.
\r
402 SFR(S1CON, 0xDC); // I2C Interface Control Register.
\r
403 #define CR2 0x80 // SCL clock frequency select bit 3.
\r
404 #define ENI1 0x40 // I2C Interface Enable.
\r
405 #define STA 0x20 // START flag.
\r
406 #define STO 0x10 // STOP flag.
\r
407 #define ADDR 0x08 // Slave mode address.
\r
408 #define AA 0x04 // Assert Acknowledge enable.
\r
409 #define CR1 0x02 // SCL clock frequency select bit 2.
\r
410 #define CR0 0x01 // SCL clock frequency select bit 1.
\r
412 SFR(S1STA, 0xDD); // I2C Interface Status Register.
\r
413 #define GC 0x80 // General Call flag.
\r
414 #define STOP 0x40 // STOP flag.
\r
415 #define INTR 0x20 // Interrupt flag.
\r
416 #define TX_MODE 0x10 // Transmission Mode flag.
\r
417 #define BBUSY 0x08 // Bus Busy flag.
\r
418 #define BLOST 0x04 // Bus Lost flag.
\r
419 #define ACK_RESP 0x02 // Not Acknowledge Response flag.
\r
420 #define SLV 0x01 // Slave Mode flag.
\r
422 SFR(S1DAT, 0xDE); // I2C Data Shift Register.
\r
423 SFR(S1ADR, 0xDF); // I2C Address Register (bit 0 not used).
\r
425 SFR(PSW, 0xD0); // Program Status Word.
\r
426 SBIT(CY, 0xD0, 7); // Carry Flag.
\r
427 SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag.
\r
428 SBIT(F0, 0xD0, 5); // User-Defined Flag.
\r
429 SBIT(RS1, 0xD0, 4); // Register Bank Select 1.
\r
430 SBIT(RS0, 0xD0, 3); // Register Bank Select 0.
\r
431 SBIT(OV, 0xD0, 2); // Overflow Flag.
\r
432 SBIT(P, 0xD0, 0); // Parity Flag.
\r
435 SFR(ACC, 0xE0); // Accumulator
\r
436 SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0.
\r
437 SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1.
\r
438 SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2.
\r
439 SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3.
\r
440 SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4.
\r
441 SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5.
\r
442 SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6.
\r
443 SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7.
\r
445 SFR(B, 0xF0); // B Register
\r
446 SBIT(B_0, 0xF0, 0); // Register B bit 0.
\r
447 SBIT(B_1, 0xF0, 1); // Register B bit 1.
\r
448 SBIT(B_2, 0xF0, 2); // Register B bit 2.
\r
449 SBIT(B_3, 0xF0, 3); // Register B bit 3.
\r
450 SBIT(B_4, 0xF0, 4); // Register B bit 4.
\r
451 SBIT(B_5, 0xF0, 5); // Register B bit 5.
\r
452 SBIT(B_6, 0xF0, 6); // Register B bit 6.
\r
453 SBIT(B_7, 0xF0, 7); // Register B bit 7.
\r
455 // PSD registers definition - by Jan Waclawek - wek at efton dot sk - May 2007
\r
456 // all defines here are with PSD_ prefix to identify them as PSD-related
\r
458 // Based on uPSD33xx datasheet (preliminary) - Jan 2005, Table 79 at pages 145/146
\r
459 // and subsequent text
\r
461 // requires to have PSD_CSIOP defined to the base address of the PSD IO area,
\r
462 // as defined in PSDSoftExpress or CUPS
\r
464 #error PSD_CSIOP has to be #define-d (before #include-ing this file) to the base address of the PSD registers area, according to csiop setting in CUPS/PSDSoftExpress
\r
466 // -- Port A not available on 52-pin uPSD33xx devices
\r
467 SFRX(PSD_DATAIN_A, PSD_CSIOP+0x00); // MCU I/O Mode Port A Data In Register
\r
468 // reads 0 if pin is log.0, 1 if pin is log. 1
\r
470 SFRX(PSD_DATAOUT_A, PSD_CSIOP+0x04); // MCU I/O Mode Port A Data Out Register
\r
471 // write 0 to set pin to log. 0, 1 to set pin to log. 1
\r
472 // read back written value
\r
473 // reset default = 00
\r
474 SFRX(PSD_DIRECTION_A, PSD_CSIOP+0x06); // MCU I/O Mode Port A Direction Register
\r
475 // write 1 to set pin as output, 0 to set pin as input
\r
476 // read back written value
\r
477 // reset default = 00
\r
478 SFRX(PSD_DRIVE_A, PSD_CSIOP+0x08); // Select Open Drain or High Slew Rate for port A
\r
479 // PA0-PA3: write 0 to select standard push-pull CMOS output, 1 to select High Slew Rate push-pull CMOS output
\r
480 // PA4-PA7: write 0 to select standard push-pull CMOS output, 1 to select Open Drain output
\r
481 // reset default = 00
\r
482 SFRX(PSD_CONTROL_A, PSD_CSIOP+0x02); // Selects MCU I/O or Latched Address Out mode for port A
\r
483 // write 0 to select standard I/O pin, 1 to drive demultiplexed address signal on pin
\r
484 // read back written value
\r
485 // reset default = 00
\r
486 SFRX(PSD_OUTENABLE_A, PSD_CSIOP+0x0C); // Read state of Output Enable Logic on each I/O port driver of Port A
\r
487 // 1 - driver output is enabled, 0 - driver is off (high impedance)
\r
490 // -- for comment on individual registers, see above Port A
\r
491 SFRX(PSD_DATAIN_B, PSD_CSIOP+0x01); // MCU I/O Mode Port B Data In Register
\r
492 SFRX(PSD_DATAOUT_B, PSD_CSIOP+0x05); // MCU I/O Mode Port B Data Out Register
\r
493 SFRX(PSD_DIRECTION_B, PSD_CSIOP+0x07); // MCU I/O Mode Port B Direction Register
\r
494 SFRX(PSD_DRIVE_B, PSD_CSIOP+0x09); // Select Open Drain or High Slew Rate for port B
\r
495 // PB0-PB3: standard/High Slew Rate, PB4-PB7: standard/Open Drain
\r
496 SFRX(PSD_CONTROL_B, PSD_CSIOP+0x03); // Selects MCU I/O or Latched Address Out mode for port B
\r
497 SFRX(PSD_OUTENABLE_B, PSD_CSIOP+0x0D); // Read state of Output Enable Logic on each I/O port driver of Port B
\r
499 // -- for comment on individual registers, see above Port A
\r
500 // only pins PC2, PC3, PC4, PC7 available; other bits in registers are undefined
\r
501 SFRX(PSD_DATAIN_C, PSD_CSIOP+0x10); // MCU I/O Mode Port C Data In Register
\r
502 SFRX(PSD_DATAOUT_C, PSD_CSIOP+0x12); // MCU I/O Mode Port C Data Out Register
\r
503 SFRX(PSD_DIRECTION_C, PSD_CSIOP+0x14); // MCU I/O Mode Port C Direction Register
\r
504 SFRX(PSD_DRIVE_C, PSD_CSIOP+0x16); // Select Open Drain for port C
\r
505 SFRX(PSD_OUTENABLE_C, PSD_CSIOP+0x1A); // Read state of Output Enable Logic on each I/O port driver of Port C
\r
507 // -- for comment on individual registers, see above Port A
\r
508 // only pins PD1, PD2 available (PD2 not available on 52-pin package); other bits in registers are undefined
\r
509 SFRX(PSD_DATAIN_D, PSD_CSIOP+0x11); // MCU I/O Mode Port D Data In Register
\r
510 SFRX(PSD_DATAOUT_D, PSD_CSIOP+0x13); // MCU I/O Mode Port D Data Out Register
\r
511 SFRX(PSD_DIRECTION_D, PSD_CSIOP+0x15); // MCU I/O Mode Port D Direction Register
\r
512 SFRX(PSD_DRIVE_D, PSD_CSIOP+0x17); // Select High Slew Rate for port D
\r
513 SFRX(PSD_OUTENABLE_D, PSD_CSIOP+0x1B); // Read state of Output Enable Logic on each I/O port driver of Port D
\r
515 SFRX(PSD_IMC_A, PSD_CSIOP+0x0A); // Read to obtain logic state of Input Macrocells connected to Port A
\r
517 SFRX(PSD_IMC_B, PSD_CSIOP+0x0B); // Read to obtain logic state of Input Macrocells connected to Port B
\r
518 SFRX(PSD_IMC_C, PSD_CSIOP+0x18); // Read to obtain logic state of Input Macrocells connected to Port C
\r
519 // only pins PC2, PC3, PC4, PC7 available; other bits in register are undefined
\r
520 SFRX(PSD_OMC_AB, PSD_CSIOP+0x20); // Read logic state of macrocells AB. Write to load macrocell AB flip-flops.
\r
521 SFRX(PSD_OMC_BC, PSD_CSIOP+0x21); // Read logic state of macrocells BC. Write to load macrocell BC flip-flops.
\r
522 SFRX(PSD_OMCMASK_AB, PSD_CSIOP+0x22); // Write to set mask for macrocell AB.
\r
523 // 1 blocks READs/WRITEs of OMF, 0 will pass OMF value
\r
524 // Read back written value.
\r
525 SFRX(PSD_OMCMASK_BC, PSD_CSIOP+0x23); // Write to set mask for macrocell BC.
\r
527 // -- all three Power Management Register are set to 00 after PowerUp, but unchanged during reset (/RST)
\r
528 SFRX(PSD_PMMR0, PSD_CSIOP+0xB0); // -- Power Management Register 0 - write/read
\r
529 // bit 0 unused and should be set to 0
\r
530 #define PSD_APD_ENA 0x02 // 0 - Automatic Power Down (APD) counter is disabled, 1 - APD enabled
\r
531 // bit 2 unused and should be set to 0
\r
532 #define PSD_TURBO_DISA 0x08 // 0 - PSD Turbo mode enabled, 1 - Turbo mode off, saving power
\r
533 #define PSD_BLOCK_CLKIN_PLD 0x10 // 0 - CLKIN to PLD not blocked, 1 - no CLKIN to PLD Input Bus, saving power
\r
534 #define PSD_BLOCK_CLKIN_OMC 0x20 // 0 - CLKIN to Output Macrocells not blocked, 1 - blocked, saving power
\r
535 // bits 6 and 7 unused and should be set to 0
\r
537 SFRX(PSD_PMMR2, PSD_CSIOP+0xB4); // -- Power Management Register 2 - write/read
\r
538 // bits 0 and 1 unused and should be set to 0
\r
539 #define PSD_BLOCK_WR_PLD 0x04 // 0 - /WR from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
\r
540 #define PSD_BLOCK_RD_PLD 0x08 // 0 - /RD from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
\r
541 #define PSD_BLOCK_PSEN_PLD 0x10 // 0 - /PSEN from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
\r
542 #define PSD_BLOCK_ALE_PLD 0x20 // 0 - ALE from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
\r
543 #define PSD_BLOCK_PC7_PDL 0x40 // 0 - input from Port C pin 7 to PLD Input Bus not blocked, 1 - blocked, saving power
\r
544 // bit 7 unused and should be set to 0
\r
546 SFRX(PSD_PMMR3, PSD_CSIOP+0xC7); // -- Power Management Register 3 - write/read
\r
547 // bit 0 unused and should be set to 0
\r
548 #define PSD_FORCE_PD 0x02 // 0 - APD counter, if enabled, will cause powerdown, 1 - powerdown will be entered immediately
\r
549 // - once set, cleared only by reset condition
\r
550 // bit 2 not defined by datasheet
\r
551 // bits 3 to 7 unused and should be set to 0
\r
553 SFRX(PSD_MAINPROTECT, PSD_CSIOP+0xC0); // -- Main Flash Memory Protection Definition
\r
554 // bit 0 to bit 7 - sector 0 to sector 7 protection status
\r
555 // - 1 - flash sector write protected, 0 - not write protected
\r
557 SFRX(PSD_ALTPROTECT, PSD_CSIOP+0xC2); // -- Secondary Flash Memory Protection Definition
\r
558 // bit 0 to bit 3 - sector 0 to sector 3 protection status
\r
559 // - 1 - flash sector write protected, 0 - not write protected
\r
560 // bit 7 - Security Bit
\r
561 // - 1 - device is secured against external reading and writing, 0 - not secured
\r
564 SFRX(PSD_PAGE, PSD_CSIOP+0xE0); // -- Memory Page Register
\r
566 SFRX(PSD_VM, PSD_CSIOP+0xE2); // -- Memory Mapping Register
\r
567 // Places PSD Module memories into 8032 Program Address Space
\r
568 // and/or 8032 XDATA Address Space
\r
569 // Default value of bits 0 to 4 is loaded from Non-Volatile
\r
570 // setting as specified from PSDsoft Express upon any reset
\r
571 // or power-up condition. The default value of these bits
\r
572 // can be overridden by 8032 at run-time.
\r
573 #define PSD_VM_SRAM_CODE 0x01 // 0 - SRAM not accessible as CODE (/PSEN) memory, 1 - SRAM accessible as CODE memory
\r
574 #define PSD_VM_ALT_CODE 0x02 // 0 - secondary FLASH not accessible as CODE (/PSEN) memory, 1 - secondary FLASH accessible as CODE memory
\r
575 #define PSD_VM_MAIN_CODE 0x04 // 0 - primary FLASH not accessible as CODE (/PSEN) memory, 1 - primary FLASH accessible as CODE memory
\r
576 #define PSD_VM_ALT_XDATA 0x08 // 0 - secondary FLASH not accessible as XDATA (/RD/WR) memory, 1 - secondary FLASH accessible as XDATA memory
\r
577 #define PSD_VM_MAIN_XDATA 0x10 // 0 - primary FLASH not accessible as XDATA (/RD/WR) memory, 1 - primary FLASH accessible as XDATA memory
\r
578 // bits 5 and 6 unused
\r
579 #define PSD_VM_PIO_EN 0x80 // 0 - disable, 1- enable peripheral I/O mode on Port A
\r
581 // another terminology for FLASH - MAIN/ALTERNATIVE -> PRIMARY/SECONDARY
\r
582 #define PSD_VM_PRI_CODE PSD_VM_MAIN_CODE
\r
583 #define PSD_VM_SEC_CODE PSD_VM_ALT_CODE
\r
584 #define PSD_VM_PRI_XDATA PSD_VM_MAIN_XDATA
\r
585 #define PSD_VM_SEC_XDATA PSD_VM_ALT_XDATA
\r
589 #endif //REG_UPSD33XX_H
\r
projects / debian / cc1111 / blob