1 /*--------------------------------------------------------------------------
2 * Register Declarations for Texas Intruments MSC12xx MCU family
4 * Written By - Philippe Latu / philippe.latu(at)linux-france.org
5 * $Id: msc1210.h 4776 2007-04-29 13:15:51Z borutr $
7 * Copyright (C) 2006 Philippe Latu
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 *---------------------------------------------------------------------------*/
28 /* BYTE Registers with bit definitions */
30 __sfr __at (0x80) P0; /* Port 0 */
31 __sfr __at (0x81) SP; /* Stack Pointer */
32 __sfr __at (0x82) DPL; /* Data Pointer 0: low byte */
33 __sfr __at (0x82) DPL0; /* Data Pointer 0: low byte */
34 __sfr __at (0x83) DPH; /* Data Pointer 0: high byte */
35 __sfr __at (0x83) DPH0; /* Data Pointer 0: high byte */
36 __sfr __at (0x84) DPL1; /* Data Pointer 1: low byte */
37 __sfr __at (0x85) DPH1; /* Data Pointer 1: high byte */
38 __sfr __at (0x86) DPS; /* Data Pointer Select */
39 __sfr __at (0x87) PCON; /* Power Control */
40 __sfr __at (0x88) TCON; /* Timer Control */
41 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
42 /* |TF1|TR1|TF0|TR0|IE1|IT1|IE0|IT0| */
43 __sbit __at (0x88) IT0; /* External Interrupt 0 Type */
44 __sbit __at (0x89) IE0; /* External Interrupt 0 Edge Flag */
45 __sbit __at (0x8a) IT1; /* External Interrupt 1 Type */
46 __sbit __at (0x8b) IE1; /* External Interrupt 1 Edge Flag */
47 __sbit __at (0x8c) TR0; /* Timer 0 On/Off Control */
48 __sbit __at (0x8d) TF0; /* Timer 0 Overflow Flag */
49 __sbit __at (0x8e) TR1; /* Timer 1 On/Off Control */
50 __sbit __at (0x8f) TF1; /* Timer 1 Overflow Flag */
51 __sfr __at (0x89) TMOD; /* Timer Mode */
52 __sfr __at (0x8a) TL0; /* Timer 0: low byte */
53 __sfr __at (0x8b) TL1; /* Timer 1: low byte */
54 __sfr __at (0x8c) TH0; /* Timer 0: high byte */
55 __sfr __at (0x8d) TH1; /* Timer 1: high byte */
56 __sfr __at (0x8e) CKCON; /* Clock Control */
57 __sfr __at (0x8f) MWS; /* Memory Write Select */
58 __sfr __at (0x90) P1; /* Port 1 */
59 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
60 /* | | | | | | |T2EX|T2 | */
61 __sbit __at (0x90) T2; /* Timer 2 External Input */
62 __sbit __at (0x91) T2EX; /* Timer 2 Capture/Reload */
63 __sfr __at (0x91) EXIF; /* External Interrupt Flag */
64 __sfr __at (0x92) MPAGE; /* Memory Page */
65 __sfr __at (0x92) _XPAGE; /* XDATA/PDATA PAGE */
66 __sfr __at (0x93) CADDR; /* Configuration Address Register */
67 __sfr __at (0x94) CDATA; /* Configuration Data Register */
68 __sfr __at (0x95) MCON; /* Memory Configuration */
69 __sfr __at (0x98) SCON; /* Serial Control 0 */
70 __sfr __at (0x98) SCON0; /* Serial Control 0 */
71 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
72 /* |SM0|SM1|SM2|REN|TB8|RB8|TI |RI | */
73 __sbit __at (0x98) RI; /* Receive Interrupt Flag */
74 __sbit __at (0x98) RI0; /* Receive Interrupt Flag */
75 __sbit __at (0x98) RI_0; /* Receive Interrupt Flag */
76 __sbit __at (0x99) TI; /* Transmit Interrupt Flag */
77 __sbit __at (0x99) TI0; /* Transmit Interrupt Flag */
78 __sbit __at (0x99) TI_0; /* Transmit Interrupt Flag */
79 __sbit __at (0x9a) RB8; /* Receive Bit 8 */
80 __sbit __at (0x9a) RB8_0; /* Receive Bit 8 */
81 __sbit __at (0x9b) TB8; /* Transmit Bit 8 */
82 __sbit __at (0x9b) TB8_0; /* Transmit Bit 8 */
83 __sbit __at (0x9c) REN; /* Receive Enable */
84 __sbit __at (0x9c) REN_0; /* Receive Enable */
85 __sbit __at (0x9d) SM2; /* Multiprocessor Communication Enable*/
86 __sbit __at (0x9d) SM2_0; /* Multiprocessor Communication Enable*/
87 __sbit __at (0x9e) SM1; /* Serial Port Select Mode 1 */
88 __sbit __at (0x9e) SM1_0; /* Serial Port Select Mode 1 */
89 __sbit __at (0x9f) SM0; /* Serial Port Select Mode 0 */
90 __sbit __at (0x9f) SM0_0; /* Serial Port Select Mode 0 */
91 __sfr __at (0x99) SBUF; /* Serial Buffer 0 */
92 __sfr __at (0x99) SBUF0; /* Serial Buffer 0 */
93 __sfr __at (0x9a) SPICON; /* SPI Control */
94 __sfr __at (0x9a) I2CCON; /* I2C Control */
95 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
96 /* |SCLK2|SCLK1|SCLK0|FIFO|ORDER|MSTR|CPHA|CPOL| */
97 __sbit __at (0x9a) CPOL; /* Serial Clock Polarity */
98 __sbit __at (0x9b) CPHA; /* Serial Clock Phase Control */
99 __sbit __at (0x9c) MSTR; /* Set Master Mode */
100 __sbit __at (0x9d) ORDER; /* Set Bit Order Transmit/Receive */
101 __sbit __at (0x9e) FIFO; /* Enable Fifo Buffer */
102 __sbit __at (0x9f) SCLK0; /* Clock Divider Select 0 */
103 __sbit __at (0xa0) SCLK1; /* Clock Divider Select 1 */
104 __sbit __at (0xa1) SCLK2; /* Clock Divider Select 2 */
105 __sfr __at (0x9b) SPIDATA; /* SPI Data */
106 __sfr __at (0x9b) I2CDATA; /* I2C Data */
107 __sfr __at (0x9c) SPIRCON; /* SPI Receive Control */
108 __sfr __at (0x9c) I2CGM; /* I2C GM Register */
109 __sfr __at (0x9d) SPITCON; /* SPI Transmit Control */
110 __sfr __at (0x9d) I2CSTAT; /* I2C Status */
111 __sfr __at (0x9e) SPISTART; /* SPI Buffer Start Address */
112 __sfr __at (0x9e) I2CSTART; /* I2C Start */
113 __sfr __at (0x9f) SPIEND; /* SPI Buffer End Address */
114 __sfr __at (0xa0) P2; /* Port 2 */
115 __sfr __at (0xa1) PWMCON; /* PWM Control */
116 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
117 /* | | |PPOL|PWMSEL|SPDSEL|TPCNTL2|TPCNTL1|TPCNTL0| */
118 __sbit __at (0xa1) TPCNTL0; /* Generator Control */
119 __sbit __at (0xa2) TPCNTL1; /* Generator Control */
120 __sbit __at (0xa3) TPCNTL2; /* Generator Control */
121 __sbit __at (0xa4) SPDSEL; /* Speed Selection */
122 __sbit __at (0xa5) PWMSEL; /* PWM Register Select */
123 __sbit __at (0xa6) PPOL; /* Period Polarity */
124 __sfr __at (0xa2) PWMLOW; /* PWM low byte */
125 __sfr __at (0xa2) TONELOW; /* Tone low byte */
126 __sfr __at (0xa3) PWMHI; /* PWM high byte */
127 __sfr __at (0xa3) TONEHI; /* Tone high byte */
128 __sfr __at (0xa4) AIPOL; /* Auxiliary Interrupt Poll */
129 __sfr __at (0xa5) PAI; /* Pending Auxiliary Interrupt */
130 __sfr __at (0xa6) AIE; /* Auxiliary Interrupt Enable */
131 __sfr __at (0xa7) AISTAT; /* Auxiliary Interrupt Status */
132 __sfr __at (0xa8) IE; /* Interrupt Enable */
133 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
134 /* |EA |ES1|ET2|ES0|ET1|EX1|ET0|EX0| */
135 __sbit __at (0xa8) EX0; /* Enable External Interrupt 0 */
136 __sbit __at (0xa9) ET0; /* Enable Timer 0 Interrupt */
137 __sbit __at (0xaa) EX1; /* Enable External Interrupt 1 */
138 __sbit __at (0xab) ET1; /* Enable Timer 1 Interrupt */
139 __sbit __at (0xac) ES0; /* Enable Serial Port 0 Interrupt */
140 __sbit __at (0xad) ET2; /* Enable Timer 2 Interrupt */
141 __sbit __at (0xae) ES1; /* Enable Serial Port 1 Interrupt */
142 __sbit __at (0xaf) EA; /* Global Interrupt Enable */
143 __sfr __at (0xa9) BPCON; /* Breakpoint Control */
144 __sfr __at (0xaa) BPL; /* Breakpoint Address Low */
145 __sfr __at (0xab) BPH; /* Breakpoint Address High */
146 __sfr __at (0xac) P0DDRL; /* Port 0 Data Direction Low */
147 __sfr __at (0xad) P0DDRH; /* Port 0 Data Direction High */
148 __sfr __at (0xae) P1DDRL; /* Port 1 Data Direction Low */
149 __sfr __at (0xaf) P1DDRH; /* Port 1 Data Direction High */
150 __sfr __at (0xb0) P3; /* Port 3 */
151 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
152 /* |RD |WR |T1 |T0 |INT1|INT0|TXD|RXD| */
153 __sbit __at (0xb0) RXD; /* Serial Port 0 Receive */
154 __sbit __at (0xb0) RXD0; /* Serial Port 0 Receive */
155 __sbit __at (0xb1) TXD; /* Serial Port 0 Transmit */
156 __sbit __at (0xb1) TXD0; /* Serial Port 0 Transmit */
157 __sbit __at (0xb2) INT0; /* External Interrupt 0 */
158 __sbit __at (0xb3) INT1; /* External Interrupt 1 */
159 __sbit __at (0xb4) T0; /* Timer 0 External Input */
160 __sbit __at (0xb5) T1; /* Timer 1 External Input */
161 __sbit __at (0xb6) WR; /* External Memory Write Strobe */
162 __sbit __at (0xb7) RD; /* External Memory Read Strobe */
163 __sfr __at (0xb1) P2DDRL; /* Port 2 Data Direction Low */
164 __sfr __at (0xb2) P2DDRH; /* Port 2 Data Direction High */
165 __sfr __at (0xb3) P3DDRL; /* Port 3 Data Direction Low */
166 __sfr __at (0xb4) P3DDRH; /* Port 3 Data Direction High */
167 __sfr __at (0xb5) DACL; /* Digital-to-Analog Converter Low */
168 __sfr __at (0xb6) DACH; /* Digital-to-Analog Converter High */
169 __sfr __at (0xb7) DACSEL; /* Digital-to-Analog Converter Select */
170 __sfr __at (0xb8) IP; /* Interrupt Priority */
171 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
172 /* | | |PT2|PS |PT1|PX1|PT0|PX0| */
173 __sbit __at (0xb8) PX0; /* External Interrupt 0 */
174 __sbit __at (0xb9) PT0; /* Timer 0 */
175 __sbit __at (0xba) PX1; /* External Interrupt 1 */
176 __sbit __at (0xbb) PT1; /* Timer 1 */
177 __sbit __at (0xbc) PS; /* Serial Port */
178 __sbit __at (0xbd) PT2; /* Timer 2 */
179 __sfr __at (0xc0) SCON1; /* Serial Control 1 */
180 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
181 /* |SM0|SM1|SM2|REN|TB8|RB8|TI |RI | */
182 __sbit __at (0xc0) RI1; /* Receive Interrupt Flag */
183 __sbit __at (0xc0) RI_1; /* Receive Interrupt Flag */
184 __sbit __at (0xc1) TI1; /* Transmit Interrupt Flag */
185 __sbit __at (0xc1) TI_1; /* Transmit Interrupt Flag */
186 __sbit __at (0xc2) RB8_1; /* Receive Bit 8 */
187 __sbit __at (0xc3) TB8_1; /* Transmit Bit 8 */
188 __sbit __at (0xc4) REN_1; /* Receive Enable */
189 __sbit __at (0xc5) SM2_1; /* Multiprocessor Communication Enable*/
190 __sbit __at (0xc6) SM1_1; /* Serial Port Select Mode 1 */
191 __sbit __at (0xc7) SM0_1; /* Serial Port Select Mode 0 */
192 __sfr __at (0xc1) SBUF1; /* Serial Buffer 1 */
193 __sfr __at (0xc6) EWU; /* Enable Wake Up */
194 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
195 /* | | | | | |EWUEX1|EWUEX0|EWUWDT| */
196 __sbit __at (0xc6) EWUWDT; /* Enable Watchdog Interrupt */
197 __sbit __at (0xc7) EWUEX0; /* Enable External Interrupt 0 */
198 __sbit __at (0xc8) EWUEX1; /* Enable External Interrupt 1 */
199 __sfr __at (0xc7) SYSCLK; /* System Clock Divider */
200 __sfr __at (0xc8) T2CON; /* Timer 2 Control */
201 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
202 /* |TF2|EXF2|RCLK|TCLK|EXEN2|TR2|C_T2|CP_RL2 | */
203 __sbit __at (0xc8) CP_RL2; /* Capture/Reload Flag */
204 __sbit __at (0xc9) C_T2; /* Overflow Flag */
205 __sbit __at (0xca) TR2; /* Timer Run */
206 __sbit __at (0xcb) EXEN2; /* Timer External Enable */
207 __sbit __at (0xcc) TCLK; /* Transmit Clock Flag */
208 __sbit __at (0xcd) RCLK; /* Receive Clock Flag */
209 __sbit __at (0xce) EXF2; /* External Flag */
210 __sbit __at (0xcf) TF2; /* Overflow Flag */
211 __sfr __at (0xca) RCAP2L; /* Timer 2 Capture Low */
212 __sfr __at (0xcb) RCAP2H; /* Timer 2 Capture High */
213 __sfr __at (0xcc) TL2; /* Timer 2 Low byte */
214 __sfr __at (0xcd) TH2; /* Timer 2 High byte */
215 __sfr __at (0xd0) PSW; /* Program Status Word */
216 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
217 /* |CY |AC |F0 |RS1|RS0|OV |F1 |P | */
218 __sbit __at (0xd0) P; /* Parity Flag */
219 __sbit __at (0xd1) F1; /* General Purpose User Flag 1 */
220 __sbit __at (0xd2) OV; /* Overflow Flag */
221 __sbit __at (0xd3) RS0; /* Register Bank Select 0 Flag */
222 __sbit __at (0xd4) RS1; /* Register Bank Select 1 Flag */
223 __sbit __at (0xd5) F0; /* General Purpose User Flag 0 */
224 __sbit __at (0xd6) AC; /* Auxiliary Carry Flag */
225 __sbit __at (0xd7) CY; /* Carry Flag */
226 __sfr __at (0xd1) OCL; /* (ADC) Offset Calibration Low byte */
227 __sfr __at (0xd2) OCM; /* (ADC) Offset Calibration Middle byte */
228 __sfr __at (0xd3) OCH; /* (ADC) Offset Calibration High byte */
229 __sfr __at (0xd4) GCL; /* (ADC) Gain Low byte */
230 __sfr __at (0xd5) GCM; /* (ADC) Gain Middle byte */
231 __sfr __at (0xd6) GCH; /* (ADC) Gain High byte */
232 __sfr __at (0xd7) ADMUX; /* ADC Multiplexer Register */
233 __sfr __at (0xd8) EICON; /* Enable Interrupt Control */
234 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
235 /* |SMOD1| |EAI|AI |WDTI| | | | */
236 __sbit __at (0xdb) WDTI; /* Watchdog Timer Interrupt Flag */
237 __sbit __at (0xdc) AI; /* Auxiliary Interrupt Flag */
238 __sbit __at (0xdd) EAI; /* Enable Auxiliary Interrupt */
239 __sbit __at (0xdf) SMOD1; /* Serial Port 1 Mode */
240 __sfr __at (0xd9) ADRESL; /* ADC Conversion Result Low byte */
241 __sfr __at (0xda) ADRESM; /* ADC Conversion Result Middle byte */
242 __sfr __at (0xdb) ADRESH; /* ADC Conversion Result High byte */
243 __sfr __at (0xdc) ADCON0; /* ADC Control 0 */
244 __sfr __at (0xdd) ADCON1; /* ADC Control 1 */
245 __sfr __at (0xde) ADCON2; /* ADC Control 2 */
246 __sfr __at (0xdf) ADCON3; /* ADC Control 3 */
247 __sfr __at (0xe0) ACC; /* Accumulator */
248 __sfr __at (0xe1) SSCON; /* Summation and Shift Control */
249 __sfr __at (0xe2) SUMR0; /* Summation Register 0 (LSB) */
250 __sfr __at (0xe3) SUMR1; /* Summation Register 1 */
251 __sfr __at (0xe4) SUMR2; /* Summation Register 2 */
252 __sfr __at (0xe5) SUMR3; /* Summation Register 3 (MSB) */
253 __sfr __at (0xe6) ODAC; /* (ADC) Offset DAC Register */
254 __sfr __at (0xe7) LVDCON; /* Low Voltage Detection Control */
255 __sfr __at (0xe8) EIE; /* Extended Interrupt Enable */
256 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
257 /* | | | |EWDI|EX5|EX4|EX3|EX2| */
258 __sbit __at (0xe8) EX2; /* Enable External Interrupt 2 */
259 __sbit __at (0xe9) EX3; /* Enable External Interrupt 3 */
260 __sbit __at (0xea) EX4; /* Enable External Interrupt 4 */
261 __sbit __at (0xeb) EX5; /* Enable External Interrupt 5 */
262 __sbit __at (0xec) EWDI; /* Enable Watchdog Interrupt */
263 __sfr __at (0xe9) HWPC0; /* Hardware Product Code 0 */
264 __sfr __at (0xea) HWPC1; /* Hardware Product Code 1 */
265 __sfr __at (0xeb) HWVER; /* Hardware Version number */
266 __sfr __at (0xee) FMCON; /* Flash Memory Control */
267 __sfr __at (0xef) FTCON; /* Flash Memory Timing Control */
268 __sfr __at (0xf0) B; /* B Register */
269 __sfr __at (0xf1) PDCON; /* Power Down Control */
270 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
271 /* | | | |PDPWM|PDAD|PDWDT|PDST|PDSPI| */
272 __sbit __at (0xf1) PDSPI; /* SPI System Control */
273 __sbit __at (0xf2) PDST; /* System Timer Control */
274 __sbit __at (0xf3) PDWDT; /* Watchdog Timer Control */
275 __sbit __at (0xf4) PDAD; /* A/D Control */
276 __sbit __at (0xf5) PDPWM; /* PWM Control */
277 __sfr __at (0xf2) PASEL; /* /PSEN|ALE Select */
278 __sfr __at (0xf6) ACLK; /* Analog Clock */
279 __sfr __at (0xf7) SRST; /* System Reset Register */
280 __sfr __at (0xf8) EIP; /* Extended Interrupt Priority */
281 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
282 /* | | | |PWDI|PX5|PX4|PX3|PX2| */
283 __sbit __at (0xf8) PX2; /* External Interrupt 2 Priority */
284 __sbit __at (0xf9) PX3; /* External Interrupt 3 Priority */
285 __sbit __at (0xfa) PX4; /* External Interrupt 4 Priority */
286 __sbit __at (0xfb) PX5; /* External Interrupt 5 Priority */
287 __sbit __at (0xfc) PWDI; /* Watchdog Interrupt Priority */
288 __sfr __at (0xf9) SECINT; /* Seconds Timer Interrupt */
289 __sfr __at (0xfa) MSINT; /* Milliseconds Interrupt */
290 __sfr __at (0xfb) USEC; /* Microsecond Register */
291 __sfr __at (0xfc) MSECL; /* Millisecond Low byte */
292 __sfr __at (0xfd) MSECH; /* Millisecond High byte */
293 __sfr __at (0xfe) HMSEC; /* Hundred Millisecond Clock */
294 __sfr __at (0xff) WDTCON; /* Watchdog Control */
297 __sfr16 __at (0x8c8a) TMR0;
298 __sfr16 __at (0x8d8b) TMR1;
299 __sfr16 __at (0xa3a2) PWM;
300 __sfr16 __at (0xa3a2) TONE;
301 __sfr16 __at (0xabaa) BP;
302 __sfr16 __at (0xabaa) BREAKPT;
303 __sfr16 __at (0xadac) P0DDR;
304 __sfr16 __at (0xafae) P1DDR;
305 __sfr16 __at (0xb2b1) P2DDR;
306 __sfr16 __at (0xb4b3) P3DDR;
307 __sfr16 __at (0xcbca) RCAP2;
308 __sfr16 __at (0xcdcc) TMR2;
309 __sfr16 __at (0xdfde) DECIMATION;
310 __sfr16 __at (0xfdfc) ONEMS;
311 __sfr16 __at (0xfdfc) MSEC;
313 /* Double Word Registers */
314 __sfr32 __at (0xe5e4e3e2) SUMR;
projects / debian / cc1111 / blob