1 /*-------------------------------------------------------------------------
2 Register Declarations for Chipcon CC2430
4 Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (December 2006)
5 (Based on CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A)
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2.1 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 In other words, you are welcome to use, share and improve this program.
22 You are forbidden to forbid anyone else to use, share and improve
23 what you give them. Help stamp out software-hoarding!
24 -------------------------------------------------------------------------*/
33 #define RFERR_VECTOR 0 // RF TX FIFO underflow and RX FIFO overflow.
34 #define ADC_VECTOR 1 // ADC end of conversion
35 #define URX0_VECTOR 2 // USART0 RX complete
36 #define URX1_VECTOR 3 // USART1 RX complete
37 #define ENC_VECTOR 4 // AES encryption/decryption complete
38 #define ST_VECTOR 5 // Sleep Timer compare
39 #define P2INT_VECTOR 6 // Port 2 inputs
40 #define UTX0_VECTOR 7 // USART0 TX complete
41 #define DMA_VECTOR 8 // DMA transfer complete
42 #define T1_VECTOR 9 // Timer 1 (16-bit) capture/compare/overflow
43 #define T2_VECTOR 10 // Timer 2 (MAC Timer)
44 #define T3_VECTOR 11 // Timer 3 (8-bit) capture/compare/overflow
45 #define T4_VECTOR 12 // Timer 4 (8-bit) capture/compare/overflow
46 #define P0INT_VECTOR 13 // Port 0 inputs
47 #define UTX1_VECTOR 14 // USART1 TX complete
48 #define P1INT_VECTOR 15 // Port 1 inputs
49 #define RF_VECTOR 16 // RF general interrupts
50 #define WDT_VECTOR 17 // Watchdog overflow in timer mode
52 // SFR Registers and BITs
54 SFR(P0, 0x80); // Port 0
55 SBIT(P0_0, 0x80, 0); // Port 0 bit 0
56 SBIT(P0_1, 0x80, 1); // Port 0 bit 1
57 SBIT(P0_2, 0x80, 2); // Port 0 bit 2
58 SBIT(P0_3, 0x80, 3); // Port 0 bit 3
59 SBIT(P0_4, 0x80, 4); // Port 0 bit 4
60 SBIT(P0_5, 0x80, 5); // Port 0 bit 5
61 SBIT(P0_6, 0x80, 6); // Port 0 bit 6
62 SBIT(P0_7, 0x80, 7); // Port 0 bit 7
63 SFR(SP, 0x81); // Stack Pointer
64 SFR(DPL0, 0x82); // Data Pointer 0 Low Byte
65 SFR(DPH0, 0x83); // Data Pointer 0 High Byte
66 SFR(DPL1, 0x84); // Data Pointer 1 Low Byte
67 SFR(DPH1, 0x85); // Data Pointer 1 High Byte
68 SFR(U0CSR, 0x86); // USART 0 Control and Status
69 SFR(PCON, 0x87); // Power Mode Control
70 SFR(TCON, 0x88); // Interrupt Flags
71 SBIT(IT0, 0x88, 0); // reserved (must always be set to 1)
72 SBIT(RFERRIF, 0x88, 1); // RFERR
\96 RF TX/RX FIFO interrupt flag
73 SBIT(IT1, 0x88, 2); // reserved (must always be set to 1)
74 SBIT(URX0IF, 0x88, 3); // USART0 RX Interrupt Flag
75 SBIT(ADCIF, 0x88, 5); // ADC Interrupt Flag
76 SBIT(URX1IF, 0x88, 7); // USART1 RX Interrupt Flag
77 SFR(P0IFG, 0x89); // Port 0 Interrupt Status Flag
78 SFR(P1IFG, 0x8A); // Port 1 Interrupt Status Flag
79 SFR(P2IFG, 0x8B); // Port 2 Interrupt Status Flag
80 SFR(PICTL, 0x8C); // Port Interrupt Control
81 SFR(P1IEN, 0x8D); // Port 1 Interrupt Mask
82 SFR(P0INP, 0x8F); // Port 0 Input Mode
83 SFR(P1, 0x90); // Port 1
84 SBIT(P1_0, 0x90, 0); // Port 1 bit 0
85 SBIT(P1_1, 0x90, 1); // Port 1 bit 1
86 SBIT(P1_2, 0x90, 2); // Port 1 bit 2
87 SBIT(P1_3, 0x90, 3); // Port 1 bit 3
88 SBIT(P1_4, 0x90, 4); // Port 1 bit 4
89 SBIT(P1_5, 0x90, 5); // Port 1 bit 5
90 SBIT(P1_6, 0x90, 6); // Port 1 bit 6
91 SBIT(P1_7, 0x90, 7); // Port 1 bit 7
92 SFR(RFIM, 0x91); // RF Interrupt Mask
93 SFR(DPS, 0x92); // Data Pointer Select
94 SFR(MPAGE, 0x93); // Memory Page Select
95 SFR(_XPAGE, 0x93); // Memory Page Select under the name SDCC needs it
96 SFR(T2CMP, 0x94); // Timer 2 Compare Value
97 SFR(ST0, 0x95); // Sleep Timer 0
98 SFR(ST1, 0x96); // Sleep Timer 1
99 SFR(ST2, 0x97); // Sleep Timer 2
100 SFR(S0CON, 0x98); // Interrupt Flags 2
101 SBIT(ENCIF_0, 0x98, 0); // AES Interrupt Flag 0
102 SBIT(ENCIF_1, 0x98, 1); // AES Interrupt Flag 1
103 SFR(IEN2, 0x9A); // Interrupt Enable 2
104 SFR(S1CON, 0x9B); // Interrupt Flags 3
105 SFR(T2PEROF0, 0x9C); // Timer 2 Overflow Capture/Compare 0
106 SFR(T2PEROF1, 0x9D); // Timer 2 Overflow Capture/Compare 1
107 SFR(T2PEROF2, 0x9E); // Timer 2 Overflow Capture/Compare 2
108 SFR(P2, 0xA0); // Port 2
109 SBIT(P2_0, 0xA0, 0); // Port 2 bit 0
110 SBIT(P2_1, 0xA0, 1); // Port 2 bit 1
111 SBIT(P2_2, 0xA0, 2); // Port 2 bit 2
112 SBIT(P2_3, 0xA0, 3); // Port 2 bit 3
113 SBIT(P2_4, 0xA0, 4); // Port 2 bit 4
114 SBIT(P2_5, 0xA0, 5); // Port 2 bit 5
115 SBIT(P2_6, 0xA0, 6); // Port 2 bit 6
116 SBIT(P2_7, 0xA0, 7); // Port 2 bit 7
117 SFR(T2OF0, 0xA1); // Timer 2 Overflow Count 0
118 SFR(T2OF1, 0xA2); // Timer 2 Overflow Count 1
119 SFR(T2OF2, 0xA3); // Timer 2 Overflow Count 2
120 SFR(T2CAPLPL, 0xA4); // Timer 2 Period Low Byte
121 SFR(T2CAPHPH, 0xA5); // Timer 2 Period High Byte
122 SFR(T2TLD, 0xA6); // Timer 2 Timer Value Low Byte
123 SFR(T2THD, 0xA7); // Timer 2 Timer Value High Byte
124 SFR(IEN0, 0xA8); // Interrupt Enable 0
125 SBIT(RFERRIE, 0xA8, 0); // RF TX/RX FIFO interrupt enable
126 SBIT(ADCIE, 0xA8, 1); // ADC Interrupt Enable
127 SBIT(URX0IE, 0xA8, 2); // USART0 RX Interrupt Enable
128 SBIT(URX1IE, 0xA8, 3); // USART1 RX Interrupt Enable
129 SBIT(ENCIE, 0xA8, 4); // AES Encryption/Decryption Interrupt Enable
130 SBIT(STIE, 0xA8, 5); // Sleep Timer Interrupt Enable
131 SBIT(EA, 0xA8, 7); // Global Interrupt Enable
132 SFR(IP0, 0xA9); // Interrupt Priority 0
133 SFR(FWT, 0xAB); // Flash Write Timing
134 SFR(FADDRL, 0xAC); // Flash Address Low Byte
135 SFR(FADDRH, 0xAD); // Flash Address High Byte
136 SFR(FCTL, 0xAE); // Flash Control
137 SFR(FWDATA, 0xAF); // Flash Write Data
138 SFR(ENCDI, 0xB1); // Encryption Input Data
139 SFR(ENCDO, 0xB2); // Encryption Output Data
140 SFR(ENCCS, 0xB3); // Encryption Control and Status
141 SFR(ADCCON1, 0xB4); // ADC Control 1
142 SFR(ADCCON2, 0xB5); // ADC Control 2
143 SFR(ADCCON3, 0xB6); // ADC Control 3
144 SFR(IEN1, 0xB8); // Interrupt Enable 1
145 SBIT(DMAIE, 0xB8, 0); // DMA Transfer Interrupt Enable
146 SBIT(T1IE, 0xB8, 1); // Timer 1 Interrupt Enable
147 SBIT(T2IE, 0xB8, 2); // Timer 2 Interrupt Enable
148 SBIT(T3IE, 0xB8, 3); // Timer 3 Interrupt Enable
149 SBIT(T4IE, 0xB8, 4); // Timer 4 Interrupt Enable
150 SBIT(P0IE, 0xB8, 5); // Port 0 Interrupt Enable
151 SFR(IP1, 0xB9); // Interrupt Priority 1
152 SFR(ADCL, 0xBA); // ADC Data Low
153 SFR(ADCH, 0xBB); // ADC Data High
154 SFR(RNDL, 0xBC); // Random Number Generator Data Low Byte
155 SFR(RNDH, 0xBD); // Random Number Generator Data High Byte
156 SFR(SLEEP, 0xBE); // Sleep Mode Control
157 SFR(IRCON, 0xC0); // Interrupt Flags 4
158 SBIT(DMAIF, 0xC0, 0); // DMA Complete Interrupt Flag
159 SBIT(T1IF, 0xC0, 1); // Timer 1 Interrupt Flag
160 SBIT(T2IF, 0xC0, 2); // Timer 2 Interrupt Flag
161 SBIT(T3IF, 0xC0, 3); // Timer 3 Interrupt Flag
162 SBIT(T4IF, 0xC0, 4); // Timer 4 Interrupt Flag
163 SBIT(P0IF, 0xC0, 5); // Port 0 Interrupt Flag
164 SBIT(STIF, 0xC0, 7); // Sleep Timer Interrupt Flag
165 SFR(U0DBUF, 0xC1); // USART 0 Receive/Transmit Data Buffer
166 SFR(U0BAUD, 0xC2); // USART 0 Baud Rate Control
167 SFR(T2CNF, 0xC3); // Timer 2 Configuration
168 SFR(U0UCR, 0xC4); // USART 0 UART Control
169 SFR(U0GCR, 0xC5); // USART 0 Generic Control
170 SFR(CLKCON, 0xC6); // Clock Control
171 SFR(MEMCTR, 0xC7); // Memory Arbiter Control
172 SFR(WDCTL, 0xC9); // Watchdog Timer Control
173 SFR(T3CNT, 0xCA); // Timer 3 Counter
174 SFR(T3CTL, 0xCB); // Timer 3 Control
175 SFR(T3CCTL0, 0xCC); // Timer 3 Channel 0 Capture/Compare Control
176 SFR(T3CC0, 0xCD); // Timer 3 Channel 0 Capture/Compare Value
177 SFR(T3CCTL1, 0xCE); // Timer 3 Channel 1 Capture/Compare Control
178 SFR(T3CC1, 0xCF); // Timer 3 Channel 1 Capture/Compare Value
179 SFR(PSW, 0xD0); // Program Status Word
180 SBIT(P, 0xD0, 0); // Parity Flag
181 SBIT(F1, 0xD0, 1); // User-Defined Flag
182 SBIT(OV, 0xD0, 2); // Overflow Flag
183 SBIT(RS0, 0xD0, 3); // Register Bank Select 0
184 SBIT(RS1, 0xD0, 4); // Register Bank Select 1
185 SBIT(F0, 0xD0, 5); // User-Defined Flag
186 SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
187 SBIT(CY, 0xD0, 7); // Carry Flag
188 SFR(DMAIRQ, 0xD1); // DMA Interrupt Flag
189 SFR(DMA1CFGL, 0xD2); // DMA Channel 1-4 Configuration Address Low Byte
190 SFR(DMA1CFGH, 0xD3); // DMA Channel 1-4 Configuration Address High Byte
191 SFR(DMA0CFGL, 0xD4); // DMA Channel 0 Configuration Address Low Byte
192 SFR(DMA0CFGH, 0xD5); // DMA Channel 0 Configuration Address High Byte
193 SFR(DMAARM, 0xD6); // DMA Channel Arm
194 SFR(DMAREQ, 0xD7); // DMA Channel Start Request and Status
195 SFR(TIMIF, 0xD8); // Timers 1/3/4 Interrupt Mask/Flag
196 SBIT(T3OVFIF, 0xD8, 0); // Timer 3 overflow interrupt flag 0:no pending 1:pending
197 SBIT(T3CH0IF, 0xD8, 1); // Timer 3 channel 0 interrupt flag 0:no pending 1:pending
198 SBIT(T3CH1IF, 0xD8, 2); // Timer 3 channel 1 interrupt flag 0:no pending 1:pending
199 SBIT(T4OVFIF, 0xD8, 3); // Timer 4 overflow interrupt flag 0:no pending 1:pending
200 SBIT(T4CH0IF, 0xD8, 4); // Timer 4 channel 0 interrupt flag 0:no pending 1:pending
201 SBIT(T4CH1IF, 0xD8, 5); // Timer 4 channel 1 interrupt flag 0:no pending 1:pending
202 SBIT(OVFIM, 0xD8, 6); // Timer 1 overflow interrupt mask
203 SFR(RFD, 0xD9); // RF Data
204 SFR(T1CC0L, 0xDA); // Timer 1 Channel 0 Capture/Compare Value Low
205 SFR(T1CC0H, 0xDB); // Timer 1 Channel 0 Capture/Compare Value High
206 SFR(T1CC1L, 0xDC); // Timer 1 Channel 1 Capture/Compare Value Low
207 SFR(T1CC1H, 0xDD); // Timer 1 Channel 1 Capture/Compare Value High
208 SFR(T1CC2L, 0xDE); // Timer 1 Channel 2 Capture/Compare Value Low
209 SFR(T1CC2H, 0xDF); // Timer 1 Channel 2 Capture/Compare Value High
210 SFR(ACC, 0xE0); // Accumulator
211 SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0
212 SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1
213 SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2
214 SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3
215 SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4
216 SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5
217 SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6
218 SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7
219 SFR(RFST, 0xE1); // RF CSMA-CA / Strobe Processor
220 SFR(T1CNTL, 0xE2); // Timer 1 Counter Low
221 SFR(T1CNTH, 0xE3); // Timer 1 Counter High
222 SFR(T1CTL, 0xE4); // Timer 1 Control and Status
223 SFR(T1CCTL0, 0xE5); // Timer 1 Channel 0 Capture/Compare Control
224 SFR(T1CCTL1, 0xE6); // Timer 1 Channel 1 Capture/Compare Control
225 SFR(T1CCTL2, 0xE7); // Timer 1 Channel 2 Capture/Compare Control
226 SFR(IRCON2, 0xE8); // Interrupt Flags 5
227 SBIT(P2IF, 0xE8, 0); // Port 2 Interrupt Flag
228 SBIT(UTX0IF, 0xE8, 1); // USART0 TX Interrupt Flag
229 SBIT(UTX1IF, 0xE8, 2); // USART1 TX Interrupt Flag
230 SBIT(P1IF, 0xE8, 3); // Port 1 Interrupt Flag
231 SBIT(WDTIF, 0xE8, 4); // Watchdog Timer Interrupt Flag
232 SFR(RFIF, 0xE9); // RF Interrupt Flags
233 SFR(T4CNT, 0xEA); // Timer 4 Counter
234 SFR(T4CTL, 0xEB); // Timer 4 Control
235 SFR(T4CCTL0, 0xEC); // Timer 4 Channel 0 Capture/Compare Control
236 SFR(T4CC0, 0xED); // Timer 4 Channel 0 Capture/Compare Value
237 SFR(T4CCTL1, 0xEE); // Timer 4 Channel 1 Capture/Compare Control
238 SFR(T4CC1, 0xEF); // Timer 4 Channel 1 Capture/Compare Value
239 SFR(B, 0xF0); // B Register
240 SBIT(B_0, 0xF0, 0); // Register B bit 0
241 SBIT(B_1, 0xF0, 1); // Register B bit 1
242 SBIT(B_2, 0xF0, 2); // Register B bit 2
243 SBIT(B_3, 0xF0, 3); // Register B bit 3
244 SBIT(B_4, 0xF0, 4); // Register B bit 4
245 SBIT(B_5, 0xF0, 5); // Register B bit 5
246 SBIT(B_6, 0xF0, 6); // Register B bit 6
247 SBIT(B_7, 0xF0, 7); // Register B bit 7
248 SFR(PERCFG, 0xF1); // Peripheral Control
249 SFR(ADCCFG, 0xF2); // ADC Input Configuration
250 SFR(P0SEL, 0xF3); // Port 0 Function Select
251 SFR(P1SEL, 0xF4); // Port 1 Function Select
252 SFR(P2SEL, 0xF5); // Port 2 Function Select
253 SFR(P1INP, 0xF6); // Port 1 Input Mode
254 SFR(P2INP, 0xF7); // Port 2 Input Mode
255 SFR(U1CSR, 0xF8); // USART 1 Control and Status
256 SBIT(ACTIVE, 0xF8, 0); // USART transmit/receive active status 0:idle 1:busy
257 SBIT(TX_BYTE, 0xF8, 1); // Transmit byte status 0:Byte not transmitted 1:Last byte transmitted
258 SBIT(RX_BYTE, 0xF8, 2); // Receive byte status 0:No byte received 1:Received byte ready
259 SBIT(ERR, 0xF8, 3); // UART parity error status 0:No error 1:parity error
260 SBIT(FE, 0xF8, 4); // UART framing error status 0:No error 1:incorrect stop bit level
261 SBIT(SLAVE, 0xF8, 5); // SPI master or slave mode select 0:master 1:slave
262 SBIT(RE, 0xF8, 6); // UART receiver enable 0:disabled 1:enabled
263 SBIT(MODE, 0xF8, 7); // USART mode select 0:SPI 1:UART
264 SFR(U1DBUF, 0xF9); // USART 1 Receive/Transmit Data Buffer
265 SFR(U1BAUD, 0xFA); // USART 1 Baud Rate Control
266 SFR(U1UCR, 0xFB); // USART 1 UART Control
267 SFR(U1GCR, 0xFC); // USART 1 Generic Control
268 SFR(P0DIR, 0xFD); // Port 0 Direction
269 SFR(P1DIR, 0xFE); // Port 1 Direction
270 SFR(P2DIR, 0xFF); // Port 2 Direction
272 // From Table 45 : Overview of RF registers
274 SFRX(MDMCTRL0H, 0xDF02); // Modem Control 0, high
275 SFRX(MDMCTRL0L, 0xDF03); // Modem Control 0, low
276 SFRX(MDMCTRL1H, 0xDF04); // Modem Control 1, high
277 SFRX(MDMCTRL1L, 0xDF05); // Modem Control 1, low
278 SFRX(RSSIH, 0xDF06); // RSSI and CCA Status and Control, high
279 SFRX(RSSIL, 0xDF07); // RSSI and CCA Status and Control, low
280 SFRX(SYNCWORDH, 0xDF08); // Synchronisation Word Control, high
281 SFRX(SYNCWORDL, 0xDF09); // Synchronisation Word Control, low
282 SFRX(TXCTRLH, 0xDF0A); // Transmit Control, high
283 SFRX(TXCTRLL, 0xDF0B); // Transmit Control, low
284 SFRX(RXCTRL0H, 0xDF0C); // Receive Control 0, high
285 SFRX(RXCTRL0L, 0xDF0D); // Receive Control 0, low
286 SFRX(RXCTRL1H, 0xDF0E); // Receive Control 1, high
287 SFRX(RXCTRL1L, 0xDF0F); // Receive Control 1, low
288 SFRX(FSCTRLH, 0xDF10); // Frequency Synthesizer Control and Status, high
289 SFRX(FSCTRLL, 0xDF11); // Frequency Synthesizer Control and Status, low
290 SFRX(CSPX, 0xDF12); // CSP X Data
291 SFRX(CSPY, 0xDF13); // CSP Y Data
292 SFRX(CSPZ, 0xDF14); // CSP Z Data
293 SFRX(CSPCTRL, 0xDF15); // CSP Control
294 SFRX(CSPT, 0xDF16); // CSP T Data
295 SFRX(RFPWR, 0xDF17); // RF Power Control
296 SFRX(FSMTCH, 0xDF20); // Finite State Machine Time Constants, high
297 SFRX(FSMTCL, 0xDF21); // Finite State Machine Time Constants, low
298 SFRX(MANANDH, 0xDF22); // Manual AND Override, high
299 SFRX(MANANDL, 0xDF23); // Manual AND Override, low
300 SFRX(MANORH, 0xDF24); // Manual OR Override, high
301 SFRX(MANORL, 0xDF25); // Manual OR Override, low
302 SFRX(AGCCTRLH, 0xDF26); // AGC Control, high
303 SFRX(AGCCTRLL, 0xDF27); // AGC Control, low
304 SFRX(FSMSTATE, 0xDF39); // Finite State Machine State Status
305 SFRX(ADCTSTH, 0xDF3A); // ADC Test, high
306 SFRX(ADCTSTL, 0xDF3B); // ADC Test, low
307 SFRX(DACTSTH, 0xDF3C); // DAC Test, high
308 SFRX(DACTSTL, 0xDF3D); // DAC Test, low
309 SFRX(IEEE_ADDR0, 0xDF43); // IEEE Address 0
310 SFRX(IEEE_ADDR1, 0xDF44); // IEEE Address 1
311 SFRX(IEEE_ADDR2, 0xDF45); // IEEE Address 2
312 SFRX(IEEE_ADDR3, 0xDF46); // IEEE Address 3
313 SFRX(IEEE_ADDR4, 0xDF47); // IEEE Address 4
314 SFRX(IEEE_ADDR5, 0xDF48); // IEEE Address 5
315 SFRX(IEEE_ADDR6, 0xDF49); // IEEE Address 6
316 SFRX(IEEE_ADDR7, 0xDF4A); // IEEE Address 7
317 SFRX(PANIDH, 0xDF4B); // PAN Identifier, high
318 SFRX(PANIDL, 0xDF4C); // PAN Identifier, low
319 SFRX(SHORTADDRH, 0xDF4D); // Short Address, high
320 SFRX(SHORTADDRL, 0xDF4E); // Short Address, low
321 SFRX(IOCFG0, 0xDF4F); // I/O Configuration 0
322 SFRX(IOCFG1, 0xDF50); // I/O Configuration 1
323 SFRX(IOCFG2, 0xDF51); // I/O Configuration 2
324 SFRX(IOCFG3, 0xDF52); // I/O Configuration 3
325 SFRX(RXFIFOCNT, 0xDF53); // RX FIFO Count
326 SFRX(FSMTC1, 0xDF54); // Finite State Machine Control
327 SFRX(CHVER, 0xDF60); // Chip Version
328 SFRX(CHIPID, 0xDF61); // Chip Identification
329 SFRX(RFSTATUS, 0xDF62); // RF Status
331 // SFRs also accesible through XDATA space
333 SFRX(X_U0CSR, 0xDF86); // USART 0 Control and Status
334 SFRX(X_P0IFG, 0xDF89); // Port 0 Interrupt Status Flag
335 SFRX(X_P1IFG, 0xDF8A); // Port 1 Interrupt Status Flag
336 SFRX(X_P2IFG, 0xDF8B); // Port 2 Interrupt Status Flag
337 SFRX(X_PICTL, 0xDF8C); // Port Interrupt Control
338 SFRX(X_P1IEN, 0xDF8D); // Port 1 Interrupt Mask
339 SFRX(X_P0INP, 0xDF8F); // Port 0 Input Mode
340 SFRX(X_RFIM, 0xDF91); // RF Interrupt Mask
341 SFRX(X_MPAGE, 0xDF93); // Memory Page Select
342 SFRX(X_T2CMP, 0xDF94); // Timer 2 Compare Value
343 SFRX(X_ST0, 0xDF95); // Sleep Timer 0
344 SFRX(X_ST1, 0xDF96); // Sleep Timer 1
345 SFRX(X_ST2, 0xDF97); // Sleep Timer 2
346 SFRX(X_T2PEROF0, 0xDF9C); // Timer 2 Overflow Capture/Compare 0
347 SFRX(X_T2PEROF1, 0xDF9D); // Timer 2 Overflow Capture/Compare 1
348 SFRX(X_T2PEROF2, 0xDF9E); // Timer 2 Overflow Capture/Compare 2
349 SFRX(X_T2OF0, 0xDFA1); // Timer 2 Overflow Count 0
350 SFRX(X_T2OF1, 0xDFA2); // Timer 2 Overflow Count 1
351 SFRX(X_T2OF2, 0xDFA3); // Timer 2 Overflow Count 2
352 SFRX(X_T2CAPLPL, 0xDFA4); // Timer 2 Period Low Byte
353 SFRX(X_T2CAPHPH, 0xDFA5); // Timer 2 Period High Byte
354 SFRX(X_T2TLD, 0xDFA6); // Timer 2 Timer Value Low Byte
355 SFRX(X_T2THD, 0xDFA7); // Timer 2 Timer Value High Byte
356 SFRX(X_FWT, 0xDFAB); // Flash Write Timing
357 SFRX(X_FADDRL, 0xDFAC); // Flash Address Low Byte
358 SFRX(X_FADDRH, 0xDFAD); // Flash Address High Byte
359 SFRX(X_FCTL, 0xDFAE); // Flash Control
360 SFRX(X_FWDATA, 0xDFAF); // Flash Write Data
361 SFRX(X_ENCDI, 0xDFB1); // Encryption Input Data
362 SFRX(X_ENCDO, 0xDFB2); // Encryption Output Data
363 SFRX(X_ENCCS, 0xDFB3); // Encryption Control and Status
364 SFRX(X_ADCCON1, 0xDFB4); // ADC Control 1
365 SFRX(X_ADCCON2, 0xDFB5); // ADC Control 2
366 SFRX(X_ADCCON3, 0xDFB6); // ADC Control 3
367 SFRX(X_ADCL, 0xDFBA); // ADC Data Low
368 SFRX(X_ADCH, 0xDFBB); // ADC Data High
369 SFRX(X_RNDL, 0xDFBC); // Random Number Generator Data Low Byte
370 SFRX(X_RNDH, 0xDFBD); // Random Number Generator Data High Byte
371 SFRX(X_SLEEP, 0xDFBE); // Sleep Mode Control
372 SFRX(X_U0DBUF, 0xDFC1); // USART 0 Receive/Transmit Data Buffer
373 SFRX(X_U0BAUD, 0xDFC2); // USART 0 Baud Rate Control
374 SFRX(X_T2CNF, 0xDFC3); // Timer 2 Configuration
375 SFRX(X_U0UCR, 0xDFC4); // USART 0 UART Control
376 SFRX(X_U0GCR, 0xDFC5); // USART 0 Generic Control
377 SFRX(X_CLKCON, 0xDFC6); // Clock Control
378 SFRX(X_MEMCTR, 0xDFC7); // Memory Arbiter Control
379 SFRX(X_WDCTL, 0xDFC9); // Watchdog Timer Control
380 SFRX(X_T3CNT, 0xDFCA); // Timer 3 Counter
381 SFRX(X_T3CTL, 0xDFCB); // Timer 3 Control
382 SFRX(X_T3CCTL0, 0xDFCC); // Timer 3 Channel 0 Capture/Compare Control
383 SFRX(X_T3CC0, 0xDFCD); // Timer 3 Channel 0 Capture/Compare Value
384 SFRX(X_T3CCTL1, 0xDFCE); // Timer 3 Channel 1 Capture/Compare Control
385 SFRX(X_T3CC1, 0xDFCF); // Timer 3 Channel 1 Capture/Compare Value
386 SFRX(X_DMAIRQ, 0xDFD1); // DMA Interrupt Flag
387 SFRX(X_DMA1CFGL, 0xDFD2); // DMA Channel 1-4 Configuration Address Low Byte
388 SFRX(X_DMA1CFGH, 0xDFD3); // DMA Channel 1-4 Configuration Address High Byte
389 SFRX(X_DMA0CFGL, 0xDFD4); // DMA Channel 0 Configuration Address Low Byte
390 SFRX(X_DMA0CFGH, 0xDFD5); // DMA Channel 0 Configuration Address High Byte
391 SFRX(X_DMAARM, 0xDFD6); // DMA Channel Arm
392 SFRX(X_DMAREQ, 0xDFD7); // DMA Channel Start Request and Status
393 SFRX(X_TIMIF, 0xDFD8); // Timers 1/3/4 Interrupt Mask/Flag
394 SFRX(X_RFD, 0xDFD9); // RF Data
395 SFRX(X_T1CC0L, 0xDFDA); // Timer 1 Channel 0 Capture/Compare Value Low
396 SFRX(X_T1CC0H, 0xDFDB); // Timer 1 Channel 0 Capture/Compare Value High
397 SFRX(X_T1CC1L, 0xDFDC); // Timer 1 Channel 1 Capture/Compare Value Low
398 SFRX(X_T1CC1H, 0xDFDD); // Timer 1 Channel 1 Capture/Compare Value High
399 SFRX(X_T1CC2L, 0xDFDE); // Timer 1 Channel 2 Capture/Compare Value Low
400 SFRX(X_T1CC2H, 0xDFDF); // Timer 1 Channel 2 Capture/Compare Value High
401 SFRX(X_RFST, 0xDFE1); // RF CSMA-CA / Strobe Processor
402 SFRX(X_T1CNTL, 0xDFE2); // Timer 1 Counter Low
403 SFRX(X_T1CNTH, 0xDFE3); // Timer 1 Counter High
404 SFRX(X_T1CTL, 0xDFE4); // Timer 1 Control and Status
405 SFRX(X_T1CCTL0, 0xDFE5); // Timer 1 Channel 0 Capture/Compare Control
406 SFRX(X_T1CCTL1, 0xDFE6); // Timer 1 Channel 1 Capture/Compare Control
407 SFRX(X_T1CCTL2, 0xDFE7); // Timer 1 Channel 2 Capture/Compare Control
408 SFRX(X_RFIF, 0xDFE9); // RF Interrupt Flags
409 SFRX(X_T4CNT, 0xDFEA); // Timer 4 Counter
410 SFRX(X_T4CTL, 0xDFEB); // Timer 4 Control
411 SFRX(X_T4CCTL0, 0xDFEC); // Timer 4 Channel 0 Capture/Compare Control
412 SFRX(X_T4CC0, 0xDFED); // Timer 4 Channel 0 Capture/Compare Value
413 SFRX(X_T4CCTL1, 0xDFEE); // Timer 4 Channel 1 Capture/Compare Control
414 SFRX(X_T4CC1, 0xDFEF); // Timer 4 Channel 1 Capture/Compare Value
415 SFRX(X_PERCFG, 0xDFF1); // Peripheral Control
416 SFRX(X_ADCCFG, 0xDFF2); // ADC Input Configuration
417 SFRX(X_P0SEL, 0xDFF3); // Port 0 Function Select
418 SFRX(X_P1SEL, 0xDFF4); // Port 1 Function Select
419 SFRX(X_P2SEL, 0xDFF5); // Port 2 Function Select
420 SFRX(X_P1INP, 0xDFF6); // Port 1 Input Mode
421 SFRX(X_P2INP, 0xDFF7); // Port 2 Input Mode
422 SFRX(X_U1CSR, 0xDFF8); // USART 1 Control and Status
423 SFRX(X_U1DBUF, 0xDFF9); // USART 1 Receive/Transmit Data Buffer
424 SFRX(X_U1BAUD, 0xDFFA); // USART 1 Baud Rate Control
425 SFRX(X_U1UCR, 0xDFFB); // USART 1 UART Control
426 SFRX(X_U1GCR, 0xDFFC); // USART 1 Generic Control
427 SFRX(X_P0DIR, 0xDFFD); // Port 0 Direction
428 SFRX(X_P1DIR, 0xDFFE); // Port 1 Direction
429 SFRX(X_P2DIR, 0xDFFF); // Port 2 Direction
431 #endif //REG_CC2430_H
projects / debian / cc1111 / blob