1 /*-------------------------------------------------------------------------
2 Register Declarations for SST SST89E516RD2, ST89E516RD, SST89V516RD2, and
3 SST89V516RD Processors (Based on datasheed S71273-03-000 1/07)
5 Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (February 2007)
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2.1 of the License, or (at your option); any later version
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 In other words, you are welcome to use, share and improve this program
22 You are forbidden to forbid anyone else to use, share and improve
23 what you give them. Help stamp out software-hoarding!
24 -------------------------------------------------------------------------*/
26 #ifndef REG_SST89x5xRDx_H
27 #define REG_SST89x5xRDx_H
31 // From TABLE 3-5: CPU related SFRs
33 SFR(ACC, 0xE0); // Accumulator
34 SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0
35 SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1
36 SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2
37 SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3
38 SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4
39 SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5
40 SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6
41 SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7
42 SFR(B, 0xF0); // B Register
43 SBIT(B_0, 0xF0, 0); // Register B bit 0
44 SBIT(B_1, 0xF0, 1); // Register B bit 1
45 SBIT(B_2, 0xF0, 2); // Register B bit 2
46 SBIT(B_3, 0xF0, 3); // Register B bit 3
47 SBIT(B_4, 0xF0, 4); // Register B bit 4
48 SBIT(B_5, 0xF0, 5); // Register B bit 5
49 SBIT(B_6, 0xF0, 6); // Register B bit 6
50 SBIT(B_7, 0xF0, 7); // Register B bit 7
51 SFR(PSW, 0xD0); // Program Status Word
52 SBIT(P, 0xD0, 0); // Parity Flag
53 SBIT(F1, 0xD0, 1); // User-Defined Flag
54 SBIT(OV, 0xD0, 2); // Overflow Flag
55 SBIT(RS0, 0xD0, 3); // Register Bank Select 0
56 SBIT(RS1, 0xD0, 4); // Register Bank Select 1
57 SBIT(F0, 0xD0, 5); // User-Defined Flag
58 SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
59 SBIT(CY, 0xD0, 7); // Carry Flag
60 SFR(SP, 0x81); // Stack Pointer
61 SFR(DPL, 0x82); // Data Pointer Low
62 SFR(DPH, 0x83); // Data Pointer High
63 SFR(IE, 0xA8); // Interrupt Enable
64 SBIT(EA, 0xA8, 7); // Global Interrupt Enable
65 SBIT(EC, 0xA8, 6); // PCA Interrupt Enable
66 SBIT(ET2, 0xA8, 5); // Timer 2 Interrupt Enable
67 SBIT(ES, 0xA8, 4); // Serial Interrupt Enable
68 SBIT(ET1, 0xA8, 3); // Timer 1 Interrupt Enable
69 SBIT(EX1, 0xA8, 2); // External 1 Interrupt Enable
70 SBIT(ET0, 0xA8, 1); // Timer 0 Interrupt Enable
71 SBIT(EX0, 0xA8, 0); // External 0 Interrupt Enable
72 SFR(IEA, 0xE8); // Interrupt Enable A
73 SBIT(EBO, 0xE8, 3); // Brown-out Interrupt Enable. (Vector is 0x00b4)
74 SFR(IP, 0xB8); // Interrupt Priority Reg
75 SBIT(PPC, 0xB8, 6); // PCA interrupt priority bit
76 SBIT(PT2, 0xB8, 5); // Timer 2 interrupt priority bit
77 SBIT(PS, 0xB8, 4); // Serial Port interrupt priority bit
78 SBIT(PT1, 0xB8, 3); // Timer 1 interrupt priority bit
79 SBIT(PX1, 0xB8, 2); // External interrupt 1 priority bit
80 SBIT(PT0, 0xB8, 1); // Timer 0 interrupt priority bit
81 SBIT(PX0, 0xB8, 0); // External interrupt 0 priority bit
82 SFR(IPH, 0xB7); // Interrupt Priority Reg High
83 #define PPCH 0x40 // PCA Interrupt Priority High Bit
84 #define PT2H 0x20 // Timer 2 Interrupt Interrupt Priority High Bit
85 #define PSH 0x10 // Serial Port Interrupt Priority High Bit
86 #define PT1H 0x08 // Timer 1 Interrupt Priority High Bit
87 #define PX1H 0x04 // External Interrupt 1 Priority High Bit
88 #define PT0H 0x02 // Timer 0 Interrupt Priority High Bit
89 #define PX0H 0x01 // External Interrupt 0 Priority High Bit
90 SFR(IP1, 0xF8); // Interrupt Priority Reg A
91 SBIT(PBO, 0xF8, 4); // Brown-out interrupt priority bit
92 SBIT(PX2, 0xF8, 1); // External Interrupt 2 priority bit
93 SBIT(PX3, 0xF8, 2); // External Interrupt 3 priority bit
94 SFR(IP1H, 0xF7); // Interrupt Priority Reg A High
95 #define PBOH 0x08 // Brown-out Interrupt priority bit high
96 #define PX2H 0x02 // External Interrupt 2 priority bit high
97 #define PX3H 0x04 // External Interrupt 3 priority bit high
98 SFR(PCON, 0x87); // Power Control
99 #define SMOD1 0x80 // Double Baud rate bit
100 #define SMOD0 0x40 // FE/SM0 Selection bit
101 #define BOF 0x20 // Brown-out detection status bit
102 #define POF 0x10 // Power-on reset status bit
103 #define GF1 0x08 // General-purpose flag bit
104 #define GF0 0x04 // General-purpose flag bit
105 #define PD 0x02 // Power-down bit
106 #define IDL 0x01 // Idle mode bit
107 SFR(AUXR, 0x8E); // Auxiliary Reg
108 #define EXTRAM 0x02 // Internal/External RAM access
109 #define AO 0x01 // Disable/Enable ALE
110 SFR(AUXR1, 0xA2); // Auxiliary Reg 1
111 #define GF2 0x08 // General purpose user-defined flag
112 #define DPS 0x01 // DPTR registers select bit
113 SFR(XICON, 0xAE); // External Interrupt Control
121 // TABLE 3-6: Flash Memory Programming SFRs
123 SFR(SFCF, 0xB1); // SuperFlash Configuration
124 #define IAPEN 0x40 // Enable IAP operation
125 #define SWR 0x02 // Software Reset
126 #define BSEL 0x01 // Program memory block switching bit
127 SFR(SFCM, 0xB2); // SuperFlash Command
128 #define FIE 0x80 // Flash Interrupt Enable
129 #define CHIP_ERASE 0x01
130 #define SECTOR_ERASE 0x0B
131 #define BLOCK_ERASE 0x0D
132 #define BYTE_VERIFY 0x0C
133 #define BYTE_PROGRAM 0x0E
134 #define PROG_SB1 0x0F
135 #define PROG_SB2 0x03
136 #define PROG_SB3 0x05
137 #define PROG_SC0 0x09
138 #define ENABLE_CLOCK_DOUBLE 0x08
139 SFR(SFAL, 0xB3); // SuperFlash Address Low Register - A7 to A0
140 SFR(SFAH, 0xB4); // SuperFlash Address High Register - A15 to A8
141 SFR(SFDT, 0xB5); // SuperFlash Data Register
142 SFR(SFST, 0xB6); // SuperFlash Status
143 #define SB1_i 0x80 // Security Bit 1 status (inverse of SB1 bit)
144 #define SB2_i 0x40 // Security Bit 2 status (inverse of SB2 bit)
145 #define SB3_i 0x20 // Security Bit 3 status (inverse of SB3 bit)
146 #define EDC_i 0x08 // Double Clock Status
147 #define FLASH_BUSY 0x04 // Flash operation completion polling bit
149 // TABLE 3-7: Watchdog Timer SFRs
151 SFR(WDTC, 0xC0); // Watchdog Timer Control
152 SBIT(WDOUT, 0xC0, 4); // Watchdog output enable
153 SBIT(WDRE, 0xC0, 3); // Watchdog timer reset enable
154 SBIT(WDTS, 0xC0, 2); // Watchdog timer reset flag
155 SBIT(WDT, 0xC0, 1); // Watchdog timer refresh
156 SBIT(SWDT, 0xC0, 0); // Start watchdog timer
157 SFR(WDTD, 0x85); // Watchdog Timer Data/Reload
159 // TABLE 3-8: Timer/Counters SFRs
161 SFR(TMOD, 0x89); // Timer/Counter Mode Control GATE C/T# M1 M0 GATE C/T# M1 M0
162 #define GATE1 0x80 // External enable for timer 1
163 #define C_T1 0x40 // Timer or counter select for timer 1
164 #define M1_1 0x20 // Operation mode bit 1 for timer 1
165 #define M0_1 0x10 // Operation mode bit 0 for timer 1
166 #define GATE0 0x08 // External enable for timer 0
167 #define C_T0 0x04 // Timer or counter select for timer 0
168 #define M1_0 0x02 // Operation mode bit 1 for timer 0
169 #define M0_0 0x01 // Operation mode bit 0 for timer 0
170 SFR(TCON, 0x88); // Timer/Counter Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
171 SBIT(TF1, 0x88, 7); // Timer 1 overflow flag
172 SBIT(TR1, 0x88, 6); // Timer 1 run control flag
173 SBIT(TF0, 0x88, 5); // Timer 0 overflow flag
174 SBIT(TR0, 0x88, 4); // Timer 0 run control flag
175 SBIT(IE1, 0x88, 3); // Interrupt 1 flag
176 SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit
177 SBIT(IE0, 0x88, 1); // Interrupt 0 flag
178 SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit
179 SFR(TH0, 0x8C); // Timer 0 MSB
180 SFR(TL0, 0x8A); // Timer 0 LSB
181 SFR(TH1, 0x8D); // Timer 1 MSB
182 SFR(TL1, 0x8B); // Timer 1 LSB
183 SFR(T2CON, 0xC8); // Timer / Counter 2 Control
184 SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag
185 SBIT(EXF2, 0xC8, 6); // Timer 2 external flag
186 SBIT(RCLK, 0xC8, 5); // Receive clock flag
187 SBIT(TCLK, 0xC8, 4); // Transmit clock flag
188 SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag
189 SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2
190 SBIT(C_T2, 0xC8, 1); // Timer or coutner select
191 SBIT(CP_RL2,0xC8, 0); // Capture/reload flag
192 SFR(T2MOD, 0xC9); // Timer 2 Mode Control
193 #define DCEN 0x02 // Down count enable bit
194 #define T2OE 0x01 // Timer 2 output enable bit
195 SFR(TH2, 0xCD); // Timer 2 MSB
196 SFR(TL2, 0xCC); // Timer 2 LSB
197 SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB
198 SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB
200 // TABLE 3-9: Interface SFRs
202 SFR(SBUF, 0x99); // Serial Data Buffer
203 SFR(SCON, 0x98); // Serial Port Control
204 SBIT(FE, 0x98, 7); // Framing Error when reading, SM0 when writing
205 SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0
206 SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1
207 SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2
208 SBIT(REN, 0x98, 4); // Enables serial reception
209 SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3
210 SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received
211 SBIT(TI, 0x98, 1); // Transmit interrupt flag
212 SBIT(RI, 0x98, 0); // Receive interrupt flag
213 SFR(SADDR, 0xA9); // Slave Address
214 SFR(SADEN, 0xB9); // Slave Address Mask
215 SFR(SPCR, 0xD5); // SPI Control Register
216 #define SPIE 0x80 // If both SPIE and ES are set to one, SPI interrupts are enabled
217 #define SPE 0x40 // SPI enable bit. When set enables SPI
218 #define DORD 0x20 // Data trans. order. 0=MSB first; 1=LSB first
219 #define MSTR 0x10 // 1=master mode. 0=slave mode
220 #define CPOL 0x08 // 1=SCK is high when idle (active low), 0=SCK is low when idle (active high)
221 #define CPHA 0x04 // 1=shift triggered on the trailing edge of SCK. 0=shift trig. on leading edge
222 #define SPR1 0x02 // SPI Clork Rate select bit 1
223 #define SPR0 0x01 // SPI Clork Rate select bit 0
228 SFR(SPSR, 0xAA); // SPI Status Register
229 #define SPIF 0x80 // SPI interrupt flag
230 #define WCOL 0x40 // Write collision Flag
231 SFR(SPDR, 0x86); // SPI Data Register
232 SFR(P0, 0x80); // Port 0
233 SBIT(P0_0, 0x80, 0); // Port 0 bit 0
234 SBIT(P0_1, 0x80, 1); // Port 0 bit 1
235 SBIT(P0_2, 0x80, 2); // Port 0 bit 2
236 SBIT(P0_3, 0x80, 3); // Port 0 bit 3
237 SBIT(P0_4, 0x80, 4); // Port 0 bit 4
238 SBIT(P0_5, 0x80, 5); // Port 0 bit 5
239 SBIT(P0_6, 0x80, 6); // Port 0 bit 6
240 SBIT(P0_7, 0x80, 7); // Port 0 bit 7
241 SFR(P1, 0x90); // Port 1
242 SBIT(P1_0, 0x90, 0); // Port 1 bit 0
243 SBIT(P1_1, 0x90, 1); // Port 1 bit 1
244 SBIT(P1_2, 0x90, 2); // Port 1 bit 2
245 SBIT(P1_3, 0x90, 3); // Port 1 bit 3
246 SBIT(P1_4, 0x90, 4); // Port 1 bit 4
247 SBIT(P1_5, 0x90, 5); // Port 1 bit 5
248 SBIT(P1_6, 0x90, 6); // Port 1 bit 6
249 SBIT(P1_7, 0x90, 7); // Port 1 bit 7
251 SBIT(T2, 0x90, 0); // Port 1 bit 0
252 SBIT(T2EX, 0x90, 1); // Port 1 bit 1
253 SBIT(ECI, 0x90, 2); // Port 1 bit 2
254 SBIT(CEX0, 0x90, 3); // Port 1 bit 3
255 SBIT(CEX1, 0x90, 4); // Port 1 bit 4
256 SBIT(CEX2, 0x90, 5); // Port 1 bit 5
257 SBIT(CEX3, 0x90, 6); // Port 1 bit 6
258 SBIT(CEX4, 0x90, 7); // Port 1 bit 7
259 // More alternate names
260 SBIT(SS, 0x90, 4); // Port 1 bit 4
261 SBIT(MOSI, 0x90, 5); // Port 1 bit 5
262 SBIT(MISO, 0x90, 6); // Port 1 bit 6
263 SBIT(SCK, 0x90, 7); // Port 1 bit 7
264 SFR(P2, 0xA0); // Port 2
265 SBIT(P2_0, 0xA0, 0); // Port 2 bit 0
266 SBIT(P2_1, 0xA0, 1); // Port 2 bit 1
267 SBIT(P2_2, 0xA0, 2); // Port 2 bit 2
268 SBIT(P2_3, 0xA0, 3); // Port 2 bit 3
269 SBIT(P2_4, 0xA0, 4); // Port 2 bit 4
270 SBIT(P2_5, 0xA0, 5); // Port 2 bit 5
271 SBIT(P2_6, 0xA0, 6); // Port 2 bit 6
272 SBIT(P2_7, 0xA0, 7); // Port 2 bit 7
273 SFR(P3, 0xB0); // Port 3
274 SBIT(P3_0, 0xB0, 0); // Port 2 bit 0
275 SBIT(P3_1, 0xB0, 1); // Port 2 bit 1
276 SBIT(P3_2, 0xB0, 2); // Port 2 bit 2
277 SBIT(P3_3, 0xB0, 3); // Port 2 bit 3
278 SBIT(P3_4, 0xB0, 4); // Port 2 bit 4
279 SBIT(P3_5, 0xB0, 5); // Port 2 bit 5
280 SBIT(P3_6, 0xB0, 6); // Port 2 bit 6
281 SBIT(P3_7, 0xB0, 7); // Port 2 bit 7
283 SBIT(RXD, 0xB0, 0); // Port 2 bit 0
284 SBIT(TXD, 0xB0, 1); // Port 2 bit 1
285 SBIT(INT0, 0xB0, 2); // Port 2 bit 2
286 SBIT(INT1, 0xB0, 3); // Port 2 bit 3
287 SBIT(T0, 0xB0, 4); // Port 2 bit 4
288 SBIT(T1, 0xB0, 5); // Port 2 bit 5
289 SBIT(WR, 0xB0, 6); // Port 2 bit 6
290 SBIT(RD, 0xB0, 7); // Port 2 bit 7
291 SFR(P4, 0xA5); // Port 4 - not bit addressable
297 // TABLE 3-10: PCA SFRs
299 SFR(CH, 0xF9); // PCA Timer/Counter High
300 SFR(CL, 0xE9); // PCA Timer/Counter Low
301 SFR(CCON, 0xD8); // PCA Timer/Counter Control Register CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 00x00000b
302 SBIT(CF, 0xD8, 7); // PCA Counter overflow flag
303 SBIT(CR, 0xD8, 6); // PCA Counter Run Control Bit
304 SBIT(CCF4, 0xD8, 4); // PCA Module 4 Interrupt Flag
305 SBIT(CCF3, 0xD8, 3); // PCA Module 3 Interrupt Flag
306 SBIT(CCF2, 0xD8, 2); // PCA Module 2 Interrupt Flag
307 SBIT(CCF1, 0xD8, 1); // PCA Module 1 Interrupt Flag
308 SBIT(CCF0, 0xD8, 0); // PCA Module 0 Interrupt Flag
309 SFR(CMOD, 0xD9); // PCA Timer/Counter Mode Register
310 #define CIDL 0x80 // CIDL=0 program the PCA counter to work during idle mode
311 #define WDTE 0x40 // Watchdog Timer Enable
312 #define CPS1 0x04 // PCA Count Pulse Select bit 1
313 #define CPS0 0x02 // PCA Count Pulse Select bit 0
314 // 00=Internal clock, Fosc/6
315 // 01=Internal clock, Fosc/6
316 // 10=Timer 0 overflow
317 // 11=External clock at ECI/P1.2 pin (max rate=Fosc/4)
318 #define ECF 0x01 // PCA Enable Counter Overflow Interrupt
319 SFR(CCAP0H, 0xFA); // PCA Module 0 Compare/Capture Register High
320 SFR(CCAP0L, 0xEA); // PCA Module 0 Compare/Capture Register Low
321 SFR(CCAP1H, 0xFB); // PCA Module 1 Compare/Capture Register High
322 SFR(CCAP1L, 0xEB); // PCA Module 1 Compare/Capture Register Low
323 SFR(CCAP2H, 0xFC); // PCA Module 2 Compare/Capture Register High
324 SFR(CCAP2L, 0xEC); // PCA Module 2 Compare/Capture Register Low
325 SFR(CCAP3H, 0xFD); // PCA Module 3 Compare/Capture Register High
326 SFR(CCAP3L, 0xED); // PCA Module 3 Compare/Capture Register Low
327 SFR(CCAP4H, 0xFE); // PCA Module 4 Compare/Capture Register High
328 SFR(CCAP4L, 0xEE); // PCA Module 4 Compare/Capture Register Low
329 SFR(CCAPM0, 0xDA); // PCA Compare/Capture Module 0 Mode Register
330 SFR(CCAPM1, 0xDB); // PCA Compare/Capture Module 1 Mode Register
331 SFR(CCAPM2, 0xDC); // PCA Compare/Capture Module 2 Mode Register
332 SFR(CCAPM3, 0xDD); // PCA Compare/Capture Module 3 Mode Register
333 SFR(CCAPM4, 0xDE); // PCA Compare/Capture Module 4 Mode Register
334 // The preceding five registers have the following bits:
335 #define ECOM 0x40 // Enable Comparator
336 #define CAPP 0x20 // 1=enables positive edge capture
337 #define CAPN 0x10 // 1=enables negative edge capture
338 #define MAT 0x08 // When counter matches sets CCFn bit causing and interrupt
339 #define TOG 0x04 // Toggle output on match
340 #define PWM 0x02 // Pulse width modulation mode
341 #define ECCF 0x01 // Enable CCF interrupt
343 #endif /*REG_SST89x5xRDx_H*/
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