1 /*-------------------------------------------------------------------------
2 Register Declarations for the SiLabs C8051F52x-F53x Processor Range
4 Copyright (C) 2006 - Maarten Brock, sourceforge.brock@dse.nl
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------*/
26 SFR(P0, 0x80); // Port 0
27 SBIT(P0_0, 0x80, 0); // Port 0 bit 0
28 SBIT(P0_1, 0x80, 1); // Port 0 bit 1
29 SBIT(P0_2, 0x80, 2); // Port 0 bit 2
30 SBIT(P0_3, 0x80, 3); // Port 0 bit 3
31 SBIT(P0_4, 0x80, 4); // Port 0 bit 4
32 SBIT(P0_5, 0x80, 5); // Port 0 bit 5
33 SBIT(P0_6, 0x80, 6); // Port 0 bit 6
34 SBIT(P0_7, 0x80, 7); // Port 0 bit 7
35 SFR(SP, 0x81); // Stack Pointer
36 SFR(DPL, 0x82); // Data Pointer Low Byte
37 SFR(DPH, 0x83); // Data Pointer High Byte
38 SFR(PCON, 0x87); // Power Mode Control
39 SFR(TCON, 0x88); // Timer Control
40 SBIT(IT0, 0x88, 0); // Ext. Interrupt 0 Type Select
41 SBIT(IE0, 0x88, 1); // Ext. Interrupt 0 Flag
42 SBIT(IT1, 0x88, 2); // Ext. Interrupt 1 Type Select
43 SBIT(IE1, 0x88, 3); // Ext. Interrupt 1 Flag
44 SBIT(TR0, 0x88, 4); // Timer 0 Run Control
45 SBIT(TF0, 0x88, 5); // Timer 0 Overflow Flag
46 SBIT(TR1, 0x88, 6); // Timer 1 Run Control
47 SBIT(TF1, 0x88, 7); // Timer 1 Overflow Flag
48 SFR(TMOD, 0x89); // Timer Mode
49 SFR16E(TMR0, 0x8C8A); // Timer/Counter 0 Word
50 SFR(TL0, 0x8A); // Timer/Counter 0 Low Byte
51 SFR(TH0, 0x8C); // Timer/Counter 0 High Byte
52 SFR16E(TMR1, 0x8D8B); // Timer/Counter 1 Word
53 SFR(TL1, 0x8B); // Timer/Counter 1 Low Byte
54 SFR(TH1, 0x8D); // Timer/Counter 1 High Byte
55 SFR(CKCON, 0x8E); // Clock Control
56 SFR(PSCTL, 0x8F); // Program Store R/W Control
57 SFR(P1, 0x90); // Port 1
58 SBIT(P1_0, 0x90, 0); // Port 1 bit 0
59 SBIT(P1_1, 0x90, 1); // Port 1 bit 1
60 SBIT(P1_2, 0x90, 2); // Port 1 bit 2
61 SBIT(P1_3, 0x90, 3); // Port 1 bit 3
62 SBIT(P1_4, 0x90, 4); // Port 1 bit 4
63 SBIT(P1_5, 0x90, 5); // Port 1 bit 5
64 SBIT(P1_6, 0x90, 6); // Port 1 bit 6
65 SBIT(P1_7, 0x90, 7); // Port 1 bit 7
66 SFR(LINADDR, 0x92); // LIN Indirect Address Pointer
67 SFR(LINDATA, 0x93); // LIN Indirect Data Buffer
68 SFR(LINCF, 0x95); // LIN Control Mode
69 SFR(SCON0, 0x98); // Serial Port 0 Control
70 SBIT(RI0, 0x98, 0); // Receive Interrupt Flag
71 SBIT(TI0, 0x98, 1); // Transmit Interrupt Flag
72 SBIT(RB80, 0x98, 2); // Ninth Receive Bit
73 SBIT(TB80, 0x98, 3); // Ninth Transmission Bit
74 SBIT(REN0, 0x98, 4); // Receive Enable
75 SBIT(MCE0, 0x98, 5); // Multiprocessor Communication Enable
76 SBIT(S0MODE, 0x98, 7); // Serial Port 0 Operation Mode
77 SFR(SBUF0, 0x99); // Serial Port 0 Data Buffer
78 SFR(CPT0CN, 0x9B); // Comparator 0 Control
79 SFR(CPT0MD, 0x9D); // Comparator 0 Mode Selection
80 SFR(CPT0MX, 0x9F); // Comparator 0 MUX Selection
81 SFR(SPI0CFG, 0xA1); // SPI Configuration
82 SFR(SPI0CKR, 0xA2); // SPI Clock Rate Control
83 SFR(SPI0DAT, 0xA3); // SPI Data
84 SFR(P0MDOUT, 0xA4); // Port 0 Output Mode Configuration
85 SFR(P1MDOUT, 0xA5); // Port 1 Output Mode Configuration
86 SFR(IE, 0xA8); // Interrupt Enable
87 SBIT(EX0, 0xA8, 0); // Enable External Interrupt 0
88 SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt
89 SBIT(EX1, 0xA8, 2); // Enable External Interrupt 1
90 SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt
91 SBIT(ES0, 0xA8, 4); // Enable Serial Port Interrupt
92 SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt
93 SBIT(ESPI0, 0xA8, 6); // Enable SPI0 Interrupt
94 SBIT(EA, 0xA8, 7); // Global Interrupt Enable
95 SFR(CLKSEL, 0xA9); // Clock Select
96 SFR(OSCIFIN, 0xB0); // Internal Oscillator Fine Calibration
97 SFR(OSCXCN, 0xB1); // External Oscillator Control
98 SFR(OSCICN, 0xB2); // Internal Oscillator Control
99 SFR(OSCICL, 0xB3); // Internal Oscillator Calibration
100 SFR(FLKEY, 0xB7); // Flash Lock and Key
101 SFR(IP, 0xB8); // Interrupt Priority
102 SBIT(PX0, 0xB8, 0); // External Interrupt 0 Priority
103 SBIT(PT0, 0xB8, 1); // Timer 0 Interrupt Priority
104 SBIT(PX1, 0xB8, 2); // External Interrupt 1 Priority
105 SBIT(PT1, 0xB8, 3); // Timer 1 Interrupt Priority
106 SBIT(PS0, 0xB8, 4); // Serial Port Interrupt Priority
107 SBIT(PT2, 0xB8, 5); // Timer 2 Interrupt Priority
108 SBIT(PSPI0, 0xB8, 6); // SPI0 Interrupt Priority
109 SFR(ADC0TK, 0xBA); // ADC0 Tracking Mode Select
110 SFR(ADC0MX, 0xBB); // ADC0 Channel Select
111 SFR(ADC0CF, 0xBC); // ADC0 Configuration
112 SFR16(ADC0, 0xBD); // ADC0 Word
113 SFR(ADC0L, 0xBD); // ADC0 Low Byte
114 SFR(ADC0H, 0xBE); // ADC0 High Byte
115 SFR(P1MASK, 0xBF); // Port 1 Mask
116 SFR16(ADC0GT, 0xC3); // ADC0 Greater-Than Data Word
117 SFR(ADC0GTL, 0xC3); // ADC0 Greater-Than Data Low Byte
118 SFR(ADC0GTH, 0xC4); // ADC0 Greater-Than Data High Byte
119 SFR16(ADC0LT, 0xC5); // ADC0 Less-Than Data Word
120 SFR(ADC0LTL, 0xC5); // ADC0 Less-Than Data Low Byte
121 SFR(ADC0LTH, 0xC6); // ADC0 Less-Than Data High Byte
122 SFR(P0MASK, 0xC7); // Port 0 Mask
123 SFR(TMR2CN, 0xC8); // Timer/Counter 2 Control
124 SFR(REG0CN, 0xC9); // Voltage Regulator Control
125 SFR16(TMR2RL, 0xCA); // Timer/Counter 2 Reload Word
126 SFR(TMR2RLL, 0xCA); // Timer/Counter 2 Reload Low Byte
127 SFR(TMR2RLH, 0xCB); // Timer/Counter 2 Reload High Byte
128 SFR16(TMR2, 0xCC); // Timer/Counter 2 Word
129 SFR(TMR2L, 0xCC); // Timer/Counter 2 Low Byte
130 SFR(TMR2H, 0xCD); // Timer/Counter 2 High Byte
131 SFR(P1MAT, 0xCF); // Port 1 Match
132 SFR(PSW, 0xD0); // Program Status Word
133 SBIT(P, 0xD0, 0); // Parity Flag
134 SBIT(F1, 0xD0, 1); // User-Defined Flag
135 SBIT(OV, 0xD0, 2); // Overflow Flag
136 SBIT(RS0, 0xD0, 3); // Register Bank Select 0
137 SBIT(RS1, 0xD0, 4); // Register Bank Select 1
138 SBIT(F0, 0xD0, 5); // User-Defined Flag
139 SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
140 SBIT(CY, 0xD0, 7); // Carry Flag
141 SFR(REF0CN, 0xD1); // Voltage Reference Control
142 SFR(P0SKIP, 0xD4); // Port 0 Skip
143 SFR(P1SKIP, 0xD5); // Port 1 Skip
144 SFR(P0MAT, 0xD7); // Port 0 Match
145 SFR(PCA0CN, 0xD8); // PCA Control
146 SBIT(CCF0, 0xD8, 0); // PCA Module 0 Capture/Compare Flag
147 SBIT(CCF1, 0xD8, 1); // PCA Module 1 Capture/Compare Flag
148 SBIT(CCF2, 0xD8, 2); // PCA Module 2 Capture/Compare Flag
149 SBIT(CR, 0xD8, 6); // PCA Counter/Timer Run Control
150 SBIT(CF, 0xD8, 7); // PCA Counter/Timer Overflow Flag
151 SFR(PCA0MD, 0xD9); // PCA Mode
152 SFR(PCA0CPM0, 0xDA); // PCA Module 0 Mode
153 SFR(PCA0CPM1, 0xDB); // PCA Module 1 Mode
154 SFR(PCA0CPM2, 0xDC); // PCA Module 2 Mode
155 SFR(ACC, 0xE0); // Accumulator
156 SFR(XBR0, 0xE1); // Port I/O Crossbar Control 0
157 SFR(XBR1, 0xE2); // Port I/O Crossbar Control 1
158 SFR(IT01CF, 0xE4); // INT0/INT1 Configuration
159 SFR(EIE1, 0xE6); // Extended Interrupt Enable 1
160 SFR(ADC0CN, 0xE8); // ADC0 Control
161 SBIT(AD0CM0, 0xE8, 0); // ADC0 Conversion Start Mode Select Bit 0
162 SBIT(AD0CM1, 0xE8, 1); // ADC0 Conversion Start Mode Select Bit 1
163 SBIT(AD0LJST, 0xE8, 2); // ADC0 Left Justify Select
164 SBIT(AD0WINT, 0xE8, 3); // ADC0 Window Compare Interrupt Flag
165 SBIT(AD0BUSY, 0xE8, 4); // ADC0 Busy Bit
166 SBIT(AD0INT, 0xE8, 5); // ADC0 Conversion Complete Interrupt Flag
167 SBIT(BURSTEN, 0xE8, 6); // ADC0 Burst Mode Enable Bit
168 SBIT(AD0EN, 0xE8, 7); // ADC0 Enable Bit
169 SFR16(PCA0CP1, 0xE9); // PCA Capture 1 Word
170 SFR(PCA0CPL1, 0xE9); // PCA Capture 1 Low Byte
171 SFR(PCA0CPH1, 0xEA); // PCA Capture 1 High Byte
172 SFR16(PCA0CP2, 0xEB); // PCA Capture 2 Word
173 SFR(PCA0CPL2, 0xEB); // PCA Capture 2 Low Byte
174 SFR(PCA0CPH2, 0xEC); // PCA Capture 2 High Byte
175 SFR(RSTSRC, 0xEF); // Reset Source Configuration/Status
176 SFR(B, 0xF0); // B Register
177 SFR(P0MDIN, 0xF1); // Port 0 Input Mode Configuration
178 SFR(P1MDIN, 0xF2); // Port 1 Input Mode Configuration
179 SFR(EIP1, 0xF6); // Extended Interrupt Priority 1
180 SFR(SPI0CN, 0xF8); // SPI0 Control
181 SBIT(SPIEN, 0xF8, 0); // SPI0 Enable
182 SBIT(TXBMT, 0xF8, 1); // SPI0 Transmit Buffer Empty
183 SBIT(NSSMD0, 0xF8, 2); // SPI0 Slave Select Mode Bit 0
184 SBIT(NSSMD1, 0xF8, 3); // SPI0 Slave Select Mode Bit 1
185 SBIT(RXOVRN, 0xF8, 4); // SPI0 Receive Overrun Flag
186 SBIT(MODF, 0xF8, 5); // SPI0 Mode Fault Flag
187 SBIT(WCOL, 0xF8, 6); // SPI0 Write Collision Flag
188 SBIT(SPIF, 0xF8, 7); // SPI0 Interrupt Flag
189 SFR16(PCA0, 0xF9); // PCA Counter Word
190 SFR(PCA0L, 0xF9); // PCA Counter Low Byte
191 SFR(PCA0H, 0xFA); // PCA Counter High Byte
192 SFR16(PCA0CP0, 0xFB); // PCA Capture 0 Word
193 SFR(PCA0CPL0, 0xFB); // PCA Capture 0 Low Byte
194 SFR(PCA0CPH0, 0xFC); // PCA Capture 0 High Byte
195 SFR(VDDMON, 0xFF); // VDD Control
197 /* Predefined SFR Bit Masks */
199 #define PCON_IDLE 0x01 /* PCON */
200 #define PCON_STOP 0x02 /* PCON */
201 #define T1M 0x08 /* CKCON */
202 #define PSWE 0x01 /* PSCTL */
203 #define PSEE 0x02 /* PSCTL */
204 #define PORSF 0x02 /* RSTSRC */
205 #define SWRSF 0x10 /* RSTSRC */
206 #define ECCF 0x01 /* PCA0CPMn */
207 #define PWM 0x02 /* PCA0CPMn */
208 #define TOG 0x04 /* PCA0CPMn */
209 #define MAT 0x08 /* PCA0CPMn */
210 #define CAPN 0x10 /* PCA0CPMn */
211 #define CAPP 0x20 /* PCA0CPMn */
212 #define ECOM 0x40 /* PCA0CPMn */
213 #define PWM16 0x80 /* PCA0CPMn */
214 #define CP0E 0x10 /* XBR0 */
215 #define CP0AE 0x20 /* XBR0 */
219 #define INT_EXT0 0 // External Interrupt 0
220 #define INT_TIMER0 1 // Timer0 Overflow
221 #define INT_EXT1 2 // External Interrupt 1
222 #define INT_TIMER1 3 // Timer1 Overflow
223 #define INT_UART0 4 // Serial Port 0
224 #define INT_TIMER2 5 // Timer2 Overflow
225 #define INT_SPI0 6 // Serial Peripheral Interface 0
226 #define INT_ADC0_WINDOW 7 // ADC0 Window Comparison
227 #define INT_ADC0_EOC 8 // ADC0 End Of Conversion
228 #define INT_PCA0 9 // PCA0 Peripheral
229 #define INT_COMP_FALLING 10 // Comparator0 Falling
230 #define INT_COMP_RISING 11 // Comparator0 Rising
231 #define INT_LIN 12 // LIN
232 #define INT_VREG_DROPOUT 13 // VREG dropout
233 #define INT_PORT_MATCH 14 // Port Match
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