1 /*-------------------------------------------------------------------------
2 Register Declarations for the SiLabs C8051F36x Processor Range
4 Copyright (C) 2007 - Maarten Brock, sourceforge.brock@dse.nl
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------*/
28 SFR(P0, 0x80); // Port 0
29 SBIT(P0_0, 0x80, 0); // Port 0 bit 0
30 SBIT(P0_1, 0x80, 1); // Port 0 bit 1
31 SBIT(P0_2, 0x80, 2); // Port 0 bit 2
32 SBIT(P0_3, 0x80, 3); // Port 0 bit 3
33 SBIT(P0_4, 0x80, 4); // Port 0 bit 4
34 SBIT(P0_5, 0x80, 5); // Port 0 bit 5
35 SBIT(P0_6, 0x80, 6); // Port 0 bit 6
36 SBIT(P0_7, 0x80, 7); // Port 0 bit 7
37 SFR(SP, 0x81); // Stack Pointer
38 SFR(DPL, 0x82); // Data Pointer Low Byte
39 SFR(DPH, 0x83); // Data Pointer High Byte
40 SFR(SFRNEXT, 0x85); // SFR Stack Next Page
41 SFR(SFRLAST, 0x86); // SFR Stack Last Page
42 SFR(PCON, 0x87); // Power Mode Control
43 SFR(TCON, 0x88); // Timer Control
44 SBIT(IT0, 0x88, 0); // Ext. Interrupt 0 Type Select
45 SBIT(IE0, 0x88, 1); // Ext. Interrupt 0 Flag
46 SBIT(IT1, 0x88, 2); // Ext. Interrupt 1 Type Select
47 SBIT(IE1, 0x88, 3); // Ext. Interrupt 1 Flag
48 SBIT(TR0, 0x88, 4); // Timer 0 Run Control
49 SBIT(TF0, 0x88, 5); // Timer 0 Overflow Flag
50 SBIT(TR1, 0x88, 6); // Timer 1 Run Control
51 SBIT(TF1, 0x88, 7); // Timer 1 Overflow Flag
52 SFR(TMOD, 0x89); // Timer Mode
53 SFR16E(TMR0, 0x8C8A); // Timer/Counter 0 Word
54 SFR(TL0, 0x8A); // Timer/Counter 0 Low Byte
55 SFR(TH0, 0x8C); // Timer/Counter 0 High Byte
56 SFR16E(TMR1, 0x8D8B); // Timer/Counter 1 Word
57 SFR(TL1, 0x8B); // Timer/Counter 1 Low Byte
58 SFR(TH1, 0x8D); // Timer/Counter 1 High Byte
59 SFR(CKCON, 0x8E); // Clock Control
60 SFR(P1, 0x90); // Port 1
61 SBIT(P1_0, 0x90, 0); // Port 1 bit 0
62 SBIT(P1_1, 0x90, 1); // Port 1 bit 1
63 SBIT(P1_2, 0x90, 2); // Port 1 bit 2
64 SBIT(P1_3, 0x90, 3); // Port 1 bit 3
65 SBIT(P1_4, 0x90, 4); // Port 1 bit 4
66 SBIT(P1_5, 0x90, 5); // Port 1 bit 5
67 SBIT(P1_6, 0x90, 6); // Port 1 bit 6
68 SBIT(P1_7, 0x90, 7); // Port 1 bit 7
69 SFR(TMR3CN, 0x91); // Timer 3 Control
70 SFR16(TMR3RL, 0x92); // Timer 3 Reload Register Word
71 SFR(TMR3RLL, 0x92); // Timer 3 Reload Register Low Byte
72 SFR(TMR3RLH, 0x93); // Timer 3 Reload Register High Byte
73 SFR16(TMR3, 0x94); // Timer 3 Word
74 SFR(TMR3L, 0x94); // Timer 3 Low Byte
75 SFR(TMR3H, 0x95); // Timer 3 High Byte
76 SFR16(IDA0, 0x96); // IDAC 0 Word
77 SFR(IDA0L, 0x96); // IDAC 0 Low Byte
78 SFR(IDA0H, 0x97); // IDAC 0 High Byte
79 SFR(SCON0, 0x98); // Serial Port 0 Control
80 SBIT(RI0, 0x98, 0); // Receive Interrupt Flag
81 SBIT(TI0, 0x98, 1); // Transmit Interrupt Flag
82 SBIT(RB80, 0x98, 2); // Ninth Receive Bit
83 SBIT(TB80, 0x98, 3); // Ninth Transmission Bit
84 SBIT(REN0, 0x98, 4); // Receive Enable
85 SBIT(MCE0, 0x98, 5); // Multiprocessor Communication Enable
86 SBIT(S0MODE, 0x98, 7); // Serial Port 0 Operation Mode
87 SFR(SBUF0, 0x99); // Serial Port 0 Data Buffer
88 SFR(CPT1CN, 0x9A); // Comparator 1 Control
89 SFR(CPT0CN, 0x9B); // Comparator 0 Control
90 SFR(CPT1MD, 0x9C); // Comparator 1 Mode Selection
91 SFR(CPT0MD, 0x9D); // Comparator 0 Mode Selection
92 SFR(CPT1MX, 0x9E); // Comparator 1 MUX Selection
93 SFR(CPT0MX, 0x9F); // Comparator 0 MUX Selection
94 SFR(P2, 0xA0); // Port 2
95 SBIT(P2_0, 0xA0, 0); // Port 2 bit 0
96 SBIT(P2_1, 0xA0, 1); // Port 2 bit 1
97 SBIT(P2_2, 0xA0, 2); // Port 2 bit 2
98 SBIT(P2_3, 0xA0, 3); // Port 2 bit 3
99 SBIT(P2_4, 0xA0, 4); // Port 2 bit 4
100 SBIT(P2_5, 0xA0, 5); // Port 2 bit 5
101 SBIT(P2_6, 0xA0, 6); // Port 2 bit 6
102 SBIT(P2_7, 0xA0, 7); // Port 2 bit 7
103 SFR(SPI0CFG, 0xA1); // SPI Configuration
104 SFR(SPI0CKR, 0xA2); // SPI Clock Rate Control
105 SFR(SPI0DAT, 0xA3); // SPI Data
106 SFR(SFRPAGE, 0xA7); // SFR Page Select
107 SFR(IE, 0xA8); // Interrupt Enable
108 SBIT(EX0, 0xA8, 0); // Enable External Interrupt 0
109 SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt
110 SBIT(EX1, 0xA8, 2); // Enable External Interrupt 1
111 SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt
112 SBIT(ES0, 0xA8, 4); // Enable Serial Port Interrupt
113 SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt
114 SBIT(ESPI0, 0xA8, 6); // Enable SPI0 Interrupt
115 SBIT(EA, 0xA8, 7); // Global Interrupt Enable
116 SFR(EMI0CN, 0xAA); // EMIF Control
117 SFR(_XPAGE, 0xAA); // SDCC: XDATA/PDATA Page
118 SFR(P3, 0xB0); // Port 3
119 SBIT(P3_0, 0xB0, 0); // Port 3 bit 0
120 SBIT(P3_1, 0xB0, 1); // Port 3 bit 1
121 SBIT(P3_2, 0xB0, 2); // Port 3 bit 2
122 SBIT(P3_3, 0xB0, 3); // Port 3 bit 3
123 SBIT(P3_4, 0xB0, 4); // Port 3 bit 4
124 SBIT(P3_5, 0xB0, 5); // Port 3 bit 5
125 SBIT(P3_6, 0xB0, 6); // Port 3 bit 6
126 SBIT(P3_7, 0xB0, 7); // Port 3 bit 7
127 SFR(P4, 0xB5); // Port 4
128 SFR(IP, 0xB8); // Interrupt Priority
129 SBIT(PX0, 0xB8, 0); // External Interrupt 0 Priority
130 SBIT(PT0, 0xB8, 1); // Timer 0 Interrupt Priority
131 SBIT(PX1, 0xB8, 2); // External Interrupt 1 Priority
132 SBIT(PT1, 0xB8, 3); // Timer 1 Interrupt Priority
133 SBIT(PS0, 0xB8, 4); // Serial Port Interrupt Priority
134 SBIT(PT2, 0xB8, 5); // Timer 2 Interrupt Priority
135 SBIT(PSPI0, 0xB8, 6); // SPI0 Interrupt Priority
136 SFR(IDA0CN, 0xB9); // IDAC 0 Control
137 SFR(AMX0N, 0xBA); // AMUX 0 Negative Channel Select
138 SFR(AMX0P, 0xBB); // AMUX 0 Positive Channel Select
139 SFR(ADC0CF, 0xBC); // ADC0 Configuration
140 SFR16(ADC0, 0xBD); // ADC0 Word
141 SFR(ADC0L, 0xBD); // ADC0 Low Byte
142 SFR(ADC0H, 0xBE); // ADC0 High Byte
143 SFR(SMB0CN, 0xC0); // SMBus Control
144 SBIT(SI, 0xC0, 0); // SMBus Interrupt Flag
145 SBIT(ACK, 0xC0, 1); // SMBus Acknowledge Flag
146 SBIT(ARBLOST, 0xC0, 2); // SMBus Arbitration Lost Indicator
147 SBIT(ACKRQ, 0xC0, 3); // SMBus Acknowledge Request
148 SBIT(STO, 0xC0, 4); // SMBus Stop Flag
149 SBIT(STA, 0xC0, 5); // SMBus Start Flag
150 SBIT(TXMODE, 0xC0, 6); // SMBus Transmit Mode Indicator
151 SBIT(MASTER, 0xC0, 7); // SMBus Master/Slave Indicator
152 SFR(SMB0CF, 0xC1); // SMBus Configuration
153 SFR(SMB0DAT, 0xC2); // SMBus Data
154 SFR16(ADC0GT, 0xC3); // ADC0 Greater-Than Data Word
155 SFR(ADC0GTL, 0xC3); // ADC0 Greater-Than Data Low Byte
156 SFR(ADC0GTH, 0xC4); // ADC0 Greater-Than Data High Byte
157 SFR16(ADC0LT, 0xC5); // ADC0 Less-Than Data Word
158 SFR(ADC0LTL, 0xC5); // ADC0 Less-Than Data Low Byte
159 SFR(ADC0LTH, 0xC6); // ADC0 Less-Than Data High Byte
160 SFR(TMR2CN, 0xC8); // Timer/Counter 2 Control
161 SBIT(T2XCLK, 0xC8, 0); // Timer 2 External Clock Select
162 SBIT(TR2, 0xC8, 2); // Timer 2 Run Control
163 SBIT(T2SPLIT, 0xC8, 3); // Timer 2 Split Mode Enable
164 SBIT(TF2CEN, 0xC8, 4); // Timer 2 Low-Frequency Oscillator Capture Enable
165 SBIT(TF2LEN, 0xC8, 5); // Timer 2 Low Byte Interrupt Enable
166 SBIT(TF2L, 0xC8, 6); // Timer 2 Low Byte Overflow Flag
167 SBIT(TF2H, 0xC8, 7); // Timer 2 High Byte Overflow Flag
168 SFR16(TMR2RL, 0xCA); // Timer/Counter 2 Reload Word
169 SFR(TMR2RLL, 0xCA); // Timer/Counter 2 Reload Low Byte
170 SFR(TMR2RLH, 0xCB); // Timer/Counter 2 Reload High Byte
171 SFR16(TMR2, 0xCC); // Timer/Counter 2 Word
172 SFR(TMR2L, 0xCC); // Timer/Counter 2 Low Byte
173 SFR(TMR2H, 0xCD); // Timer/Counter 2 High Byte
174 SFR(PSW, 0xD0); // Program Status Word
175 SBIT(P, 0xD0, 0); // Parity Flag
176 SBIT(F1, 0xD0, 1); // User-Defined Flag
177 SBIT(OV, 0xD0, 2); // Overflow Flag
178 SBIT(RS0, 0xD0, 3); // Register Bank Select 0
179 SBIT(RS1, 0xD0, 4); // Register Bank Select 1
180 SBIT(F0, 0xD0, 5); // User-Defined Flag
181 SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
182 SBIT(CY, 0xD0, 7); // Carry Flag
183 SFR(REF0CN, 0xD1); // Voltage Reference Control
184 SFR(PCA0CN, 0xD8); // PCA Control
185 SBIT(CCF0, 0xD8, 0); // PCA Module 0 Capture/Compare Flag
186 SBIT(CCF1, 0xD8, 1); // PCA Module 1 Capture/Compare Flag
187 SBIT(CCF2, 0xD8, 2); // PCA Module 2 Capture/Compare Flag
188 SBIT(CCF3, 0xD8, 3); // PCA Module 3 Capture/Compare Flag
189 SBIT(CCF4, 0xD8, 4); // PCA Module 4 Capture/Compare Flag
190 SBIT(CCF5, 0xD8, 5); // PCA Module 5 Capture/Compare Flag
191 SBIT(CR, 0xD8, 6); // PCA Counter/Timer Run Control
192 SBIT(CF, 0xD8, 7); // PCA Counter/Timer Overflow Flag
193 SFR(PCA0MD, 0xD9); // PCA Mode
194 SFR(PCA0CPM0, 0xDA); // PCA Module 0 Mode
195 SFR(PCA0CPM1, 0xDB); // PCA Module 1 Mode
196 SFR(PCA0CPM2, 0xDC); // PCA Module 2 Mode
197 SFR(PCA0CPM3, 0xDD); // PCA Module 3 Mode
198 SFR(PCA0CPM4, 0xDE); // PCA Module 4 Mode
199 SFR(PCA0CPM5, 0xDF); // PCA Module 5 Mode
200 SFR(ACC, 0xE0); // Accumulator
201 SFR(IT01CF, 0xE4); // INT0/INT1 Configuration
202 SFR(EIE1, 0xE6); // Extended Interrupt Enable 1
203 SFR(EIE2, 0xE7); // Extended Interrupt Enable 2
204 SFR(ADC0CN, 0xE8); // ADC0 Control
205 SBIT(AD0CM0, 0xE8, 0); // ADC0 Conversion Start Mode Select Bit 0
206 SBIT(AD0CM1, 0xE8, 1); // ADC0 Conversion Start Mode Select Bit 1
207 SBIT(AD0CM2, 0xE8, 2); // ADC0 Conversion Start Mode Select Bit 2
208 SBIT(AD0WINT, 0xE8, 3); // ADC0 Window Compare Interrupt Flag
209 SBIT(AD0BUSY, 0xE8, 4); // ADC0 Busy Bit
210 SBIT(AD0INT, 0xE8, 5); // ADC0 Conversion Complete Interrupt Flag
211 SBIT(AD0TM, 0xE8, 6); // ADC0 Track Mode Bit
212 SBIT(AD0EN, 0xE8, 7); // ADC0 Enable Bit
213 SFR16(PCA0CP1, 0xE9); // PCA Capture 1 Word
214 SFR(PCA0CPL1, 0xE9); // PCA Capture 1 Low Byte
215 SFR(PCA0CPH1, 0xEA); // PCA Capture 1 High Byte
216 SFR16(PCA0CP2, 0xEB); // PCA Capture 2 Word
217 SFR(PCA0CPL2, 0xEB); // PCA Capture 2 Low Byte
218 SFR(PCA0CPH2, 0xEC); // PCA Capture 2 High Byte
219 SFR16(PCA0CP3, 0xED); // PCA Capture 3 Word
220 SFR(PCA0CPL3, 0xED); // PCA Capture 3 Low Byte
221 SFR(PCA0CPH3, 0xEE); // PCA Capture 3 High Byte
222 SFR(RSTSRC, 0xEF); // Reset Source Configuration/Status
223 SFR(B, 0xF0); // B Register
224 SFR16(PCA0CP5, 0xF5); // PCA Capture 5 Word
225 SFR(PCA0CPL5, 0xF5); // PCA Capture 5 Low Byte
226 SFR(PCA0CPH5, 0xF6); // PCA Capture 5 High Byte
227 SFR(SPI0CN, 0xF8); // SPI0 Control
228 SBIT(SPIEN, 0xF8, 0); // SPI0 Enable
229 SBIT(TXBMT, 0xF8, 1); // SPI0 Transmit Buffer Empty
230 SBIT(NSSMD0, 0xF8, 2); // SPI0 Slave Select Mode Bit 0
231 SBIT(NSSMD1, 0xF8, 3); // SPI0 Slave Select Mode Bit 1
232 SBIT(RXOVRN, 0xF8, 4); // SPI0 Receive Overrun Flag
233 SBIT(MODF, 0xF8, 5); // SPI0 Mode Fault Flag
234 SBIT(WCOL, 0xF8, 6); // SPI0 Write Collision Flag
235 SBIT(SPIF, 0xF8, 7); // SPI0 Interrupt Flag
236 SFR16(PCA0, 0xF9); // PCA Counter Word
237 SFR(PCA0L, 0xF9); // PCA Counter Low Byte
238 SFR(PCA0H, 0xFA); // PCA Counter High Byte
239 SFR16(PCA0CP0, 0xFB); // PCA Capture 0 Word
240 SFR(PCA0CPL0, 0xFB); // PCA Capture 0 Low Byte
241 SFR(PCA0CPH0, 0xFC); // PCA Capture 0 High Byte
242 SFR16(PCA0CP4, 0xFD); // PCA Capture 4 Word
243 SFR(PCA0CPL4, 0xFD); // PCA Capture 4 Low Byte
244 SFR(PCA0CPH4, 0xFE); // PCA Capture 4 High Byte
245 SFR(VDM0CN, 0xFF); // VDD Monitor Control
249 SFR(PSCTL, 0x8F); // Program Store R/W Control
250 SFR16(MAC0A, 0xA4); // MAC0 A Register Word
251 SFR(MAC0AL, 0xA4); // MAC0 A Register Low Byte
252 SFR(MAC0AH, 0xA5); // MAC0 A Register High Byte
253 SFR16(MAC0RND, 0xAE); // MAC0 Rounding Register Word
254 SFR(MAC0RNDL, 0xAE); // MAC0 Rounding Register Low Byte
255 SFR(MAC0RNDH, 0xAF); // MAC0 Rounding Register High Byte
256 SFR(P2MAT, 0xB1); // Port 2 Match
257 SFR(P2MASK, 0xB2); // Port 2 Mask
258 SFR(FLSCL, 0xB6); // Flash Scale
259 SFR(FLKEY, 0xB7); // Flash Lock and Key
260 SFR(MAC0STA, 0xCF); // MAC0 Status Register
261 SFR32(MAC0ACC, 0xD2); // MAC0 Accumulator Long Word
262 SFR(MAC0ACC0, 0xD2); // MAC0 Accumulator Byte 0 (LSB)
263 SFR(MAC0ACC1, 0xD3); // MAC0 Accumulator Byte 1
264 SFR(MAC0ACC2, 0xD4); // MAC0 Accumulator Byte 2
265 SFR(MAC0ACC3, 0xD5); // MAC0 Accumulator Byte 3 (MSB)
266 SFR(MAC0OVR, 0xD6); // MAC0 Accumulator Overflow
267 SFR(MAC0CF, 0xD7); // MAC0 Configuration
268 SFR(P1MAT, 0xE1); // Port 1 Match
269 SFR(P1MASK, 0xE2); // Port 1 Mask
270 // No sfr16 definition for MAC0B because MAC0BL must be written last
271 SFR(MAC0BL, 0xF1); // MAC0 B Register Low Byte
272 SFR(MAC0BH, 0xF2); // MAC0 B Register High Byte
273 SFR(P0MAT, 0xF3); // Port 0 Match
274 SFR(P0MASK, 0xF4); // Port 0 Mask
278 SFR(CCH0CN, 0x84); // Cache Control
279 SFR(CLKSEL, 0x8F); // Clock Select
280 SFR(P0MDOUT, 0xA4); // Port 0 Output Mode Configuration
281 SFR(P1MDOUT, 0xA5); // Port 1 Output Mode Configuration
282 SFR(P2MDOUT, 0xA6); // Port 2 Output Mode Configuration
283 SFR(PLL0DIV, 0xA9); // PLL Divider
284 SFR(FLSTAT, 0xAC); // Flash Status
285 SFR(OSCLCN, 0xAD); // Internal Low-Frequency Oscillator Control
286 SFR(P4MDOUT, 0xAE); // Port 4 Output Mode Configuration
287 SFR(P3MDOUT, 0xAF); // Port 3 Output Mode Configuration
288 SFR(PLL0MUL, 0xB1); // PLL Multiplier
289 SFR(PLL0FLT, 0xB2); // PLL Filter
290 SFR(PLL0CN, 0xB3); // PLL Control
291 SFR(OSCXCN, 0xB6); // External Oscillator Control
292 SFR(OSCICN, 0xB7); // Internal Oscillator Control
293 SFR(OSCICL, 0xBF); // Internal Oscillator Calibration
294 SFR(EMI0CF, 0xC7); // EMIF Configuration
295 SFR(CCH0TN, 0xC9); // Cache Tuning
296 SFR(EIP1, 0xCE); // Extended Interrupt Priority 1
297 SFR(EIP2, 0xCF); // Extended Interrupt Priority 2
298 SFR(CCH0LC, 0xD2); // Cache Lock
299 SFR(CCH0MA, 0xD3); // Cache Miss Accumulator
300 SFR(P0SKIP, 0xD4); // Port 0 Skip
301 SFR(P1SKIP, 0xD5); // Port 1 Skip
302 SFR(P2SKIP, 0xD6); // Port 2 Skip
303 SFR(P3SKIP, 0xD7); // Port 3 Skip
304 SFR(XBR0, 0xE1); // Port I/O Crossbar Control 0
305 SFR(XBR1, 0xE2); // Port I/O Crossbar Control 1
306 SFR(SFR0CN, 0xE5); // SFR Page Control
307 SFR(P0MDIN, 0xF1); // Port 0 Input Mode Configuration
308 SFR(P1MDIN, 0xF2); // Port 1 Input Mode Configuration
309 SFR(P2MDIN, 0xF3); // Port 2 Input Mode Configuration
310 SFR(P3MDIN, 0xF4); // Port 3 Input Mode Configuration
311 SFR(EMI0TC, 0xF7); // EMIF Timing Control
313 /* Predefined SFR Bit Masks */
315 #define PCON_IDLE 0x01 /* PCON */
316 #define PCON_STOP 0x02 /* PCON */
317 #define T1M 0x08 /* CKCON */
318 #define PSWE 0x01 /* PSCTL */
319 #define PSEE 0x02 /* PSCTL */
320 #define PORSF 0x02 /* RSTSRC */
321 #define SWRSF 0x10 /* RSTSRC */
322 #define ECCF 0x01 /* PCA0CPMn */
323 #define PWM 0x02 /* PCA0CPMn */
324 #define TOG 0x04 /* PCA0CPMn */
325 #define MAT 0x08 /* PCA0CPMn */
326 #define CAPN 0x10 /* PCA0CPMn */
327 #define CAPP 0x20 /* PCA0CPMn */
328 #define ECOM 0x40 /* PCA0CPMn */
329 #define PWM16 0x80 /* PCA0CPMn */
330 #define CP0E 0x10 /* XBR0 */
331 #define CP0AE 0x20 /* XBR0 */
335 #define INT_EXT0 0 // External Interrupt 0
336 #define INT_TIMER0 1 // Timer0 Overflow
337 #define INT_EXT1 2 // External Interrupt 1
338 #define INT_TIMER1 3 // Timer1 Overflow
339 #define INT_UART0 4 // Serial Port 0
340 #define INT_TIMER2 5 // Timer2 Overflow
341 #define INT_SPI0 6 // Serial Peripheral Interface 0
342 #define INT_SMBUS0 7 // SMBus0 Interface
344 #define INT_ADC0_WINDOW 9 // ADC0 Window Comparison
345 #define INT_ADC0_EOC 10 // ADC0 End Of Conversion
346 #define INT_PCA0 11 // PCA0 Peripheral
347 #define INT_COMPARATOR0 12 // Comparator0
348 #define INT_COMPARATOR1 13 // Comparator1
349 #define INT_TIMER3 14 // Timer3 Overflow
351 #define INT_PORT_MATCH 16 // Port Match
projects / debian / cc1111 / blob