1 /*-------------------------------------------------------------------------
2 Register Declarations for the SiLabs C8051F35x Processor Range
4 Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------*/
27 __sfr __at (0x80) P0 ; /* PORT 0 */
28 __sfr __at (0x81) SP ; /* STACK POINTER */
29 __sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
30 __sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
31 __sfr __at (0x87) PCON ; /* POWER CONTROL */
32 __sfr __at (0x88) TCON ; /* TIMER CONTROL */
33 __sfr __at (0x89) TMOD ; /* TIMER MODE */
34 __sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
35 __sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
36 __sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
37 __sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
38 __sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
39 __sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
40 __sfr __at (0x90) P1 ; /* PORT 1 */
41 __sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
42 __sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
43 __sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
44 __sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
45 __sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
46 __sfr __at (0x96) IDA0 ; /* CURRENT MODE DAC 0 */
47 __sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
48 __sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
49 __sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
50 __sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
51 __sfr __at (0x9A) ADC0DECL ; /* ADC DECIMATION LOW */
52 __sfr __at (0x9B) ADC0DECH ; /* ADC DECIMATION HIGH */
53 __sfr __at (0x9C) CPT0CN ; /* COMPARATOR 0 CONTROL */
54 __sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
55 __sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
56 __sfr __at (0xA0) P2 ; /* PORT 2 */
57 __sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
58 __sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
59 __sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
60 __sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
61 __sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
62 __sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
63 __sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
64 __sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
65 __sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
66 __sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
67 __sfr __at (0xAB) ADC0CGL ; /* ADC 0 GAIN CALIBRATION LOW */
68 __sfr __at (0xAC) ADC0CGM ; /* ADC 0 GAIN CALIBRATION MIDDLE */
69 __sfr __at (0xAD) ADC0CGH ; /* ADC 0 GAIN CALIBRATION HIGH */
70 __sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
71 __sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
72 __sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
73 __sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
74 __sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
75 __sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
76 __sfr __at (0xB9) IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
77 __sfr __at (0xBA) ADC0COL ; /* ADC 0 OFFSET CALIBRATION LOW */
78 __sfr __at (0xBB) ADC0COM ; /* ADC 0 OFFSET CALIBRATION MIDDLE */
79 __sfr __at (0xBC) ADC0COH ; /* ADC 0 OFFSET CALIBRATION HIGH */
80 __sfr __at (0xBD) ADC0BUF ; /* ADC 0 BUFFER CONTROL */
81 __sfr __at (0xBE) CLKMUL ; /* CLOCK MULTIPLIER */
82 __sfr __at (0xBF) ADC0DAC ; /* ADC 0 OFFSET DAC */
83 __sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
84 __sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
85 __sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
86 __sfr __at (0xC3) ADC0L ; /* ADC 0 OUTPUT LOW BYTE */
87 __sfr __at (0xC4) ADC0M ; /* ADC 0 OUTPUT MIDDLE BYTE */
88 __sfr __at (0xC5) ADC0H ; /* ADC 0 OUTPUT HIGH BYTE */
89 __sfr __at (0xC6) ADC0MUX ; /* ADC 0 MULTIPLEXER */
90 __sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
91 __sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
92 __sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
93 __sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
94 __sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
95 __sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
96 __sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
97 __sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
98 __sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
99 __sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
100 __sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
101 __sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
102 __sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
103 __sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
104 __sfr __at (0xD7) IDA1CN ; /* CURRENT MODE DAC 1 - CONTROL */
105 __sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
106 __sfr __at (0xD9) PCA0MD ; /* PCA MODE */
107 __sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
108 __sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
109 __sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
110 __sfr __at (0xDD) IDA1 ; /* CURRENT MODE DAC 1 */
111 __sfr __at (0xE0) ACC ; /* ACCUMULATOR */
112 __sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
113 __sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
114 __sfr __at (0xE3) PFE0CN ; /* PREFETCH ENGINE CONTROL */
115 __sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
116 __sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
117 __sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
118 __sfr __at (0xE8) ADC0STA ; /* ADC 0 STATUS */
119 __sfr __at (0xE9) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
120 __sfr __at (0xEA) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
121 __sfr __at (0xEB) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
122 __sfr __at (0xEC) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
123 __sfr __at (0xED) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
124 __sfr __at (0xEE) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
125 __sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
126 __sfr __at (0xF0) B ; /* B REGISTER */
127 __sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
128 __sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
129 __sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
130 __sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
131 __sfr __at (0xF3) ADC0MD ; /* ADC 0 MODE */
132 __sfr __at (0xF4) ADC0CN ; /* ADC 0 CONTROL */
133 __sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
134 __sfr __at (0xF7) ADC0CLK ; /* ADC 0 CLOCK */
135 __sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
136 __sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
137 __sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
138 __sfr __at (0xFB) ADC0CF ; /* ADC 0 CONFIGURATION */
139 __sfr __at (0xFC) ADC0FL ; /* ADC 0 FAST FILTER OUTPUT LOW */
140 __sfr __at (0xFD) ADC0FM ; /* ADC 0 FAST FILTER OUTPUT MIDDLE */
141 __sfr __at (0xFE) ADC0FH ; /* ADC 0 FAST FILTER OUTPUT HIGH */
142 __sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
145 /* WORD/DWORD Registers */
147 __sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
148 __sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
149 __sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
150 __sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
151 __sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
152 __sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
153 __sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
155 __sfr16 __at (0x9B9A) ADC0DEC ; /* ADC 0 DECIMATION RATIO REGISTER WORD */
156 /* Unfortunately the C8051F350 does not have an sfr that always reads 0x00 and */
157 /* ignores what is written to it. That could have enabled sfr32 definitions for */
158 /* the 24 bit ADC0 sfr combinations. */
159 __sfr16 __at (0xC5C4) ADC0 ; /* 16 bit ADC 0 SINC3 FILTER OUTPUT WORD */
160 __sfr16 __at (0xFEFD) ADC0F ; /* 16 bit ADC 0 FAST FILTER OUTPUT WORD */
162 __sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
163 __sfr16 __at (0xEAE9) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
164 __sfr16 __at (0xECEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
165 __sfr16 __at (0xEEED) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
171 __sbit __at (0x80) P0_0 ;
172 __sbit __at (0x81) P0_1 ;
173 __sbit __at (0x82) P0_2 ;
174 __sbit __at (0x83) P0_3 ;
175 __sbit __at (0x84) P0_4 ;
176 __sbit __at (0x85) P0_5 ;
177 __sbit __at (0x86) P0_6 ;
178 __sbit __at (0x87) P0_7 ;
181 __sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
182 __sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
183 __sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
184 __sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
185 __sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
186 __sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
187 __sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
188 __sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
191 __sbit __at (0x90) P1_0 ;
192 __sbit __at (0x91) P1_1 ;
193 __sbit __at (0x92) P1_2 ;
194 __sbit __at (0x93) P1_3 ;
195 __sbit __at (0x94) P1_4 ;
196 __sbit __at (0x95) P1_5 ;
197 __sbit __at (0x96) P1_6 ;
198 __sbit __at (0x97) P1_7 ;
201 __sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
202 __sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
203 __sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
204 __sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
205 __sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
206 __sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
207 __sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
208 __sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
209 __sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
210 __sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
211 __sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
212 __sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
213 __sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
214 __sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
217 __sbit __at (0xA0) P2_0 ;
218 __sbit __at (0xA1) P2_1 ;
219 __sbit __at (0xA2) P2_2 ;
220 __sbit __at (0xA3) P2_3 ;
221 __sbit __at (0xA4) P2_4 ;
222 __sbit __at (0xA5) P2_5 ;
223 __sbit __at (0xA6) P2_6 ;
224 __sbit __at (0xA7) P2_7 ;
227 __sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
228 __sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
229 __sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
230 __sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
231 __sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
232 __sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
233 __sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
234 __sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
235 __sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
238 __sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
239 __sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
240 __sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
241 __sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
242 __sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
243 __sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
244 __sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
245 __sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
248 __sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
249 __sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
250 __sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
251 __sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
252 __sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
253 __sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
254 __sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
255 __sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
258 __sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
259 __sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
260 __sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
261 __sbit __at (0xCD) TF2CEN ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
262 __sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
263 __sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
264 __sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
265 __sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
268 __sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
269 __sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
270 __sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
271 __sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
272 __sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
273 __sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
274 __sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
275 __sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
278 __sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
279 __sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
280 __sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
281 __sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
282 __sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
285 __sbit __at (0xE8) AD0OVR ; /* ADC0CN.0 - ADC 0 OVERRUN FLAG */
286 __sbit __at (0xE9) AD0ERR ; /* ADC0CN.1 - ADC 0 ERROR FLAG */
287 __sbit __at (0xEA) AD0CALC ; /* ADC0CN.2 - ADC 0 CALIBRATION COMPLETE FLAG */
288 __sbit __at (0xEB) AD0FFC ; /* ADC0CN.3 - ADC 0 FAST FILTER CLIP FLAG */
289 __sbit __at (0xEC) AD0S3C ; /* ADC0CN.4 - ADC 0 SINC3 FILTER CLIP FLAG */
290 __sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
291 __sbit __at (0xEE) AD0CBSY ; /* ADC0CN.6 - ADC 0 CALIBRATION IN PROGRESS FLAG */
292 __sbit __at (0xEF) AD0BUSY ; /* ADC0CN.7 - ADC 0 CONVERSION IN PROGRESS FLAG */
295 __sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
296 __sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
297 __sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
298 __sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
299 __sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
300 __sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
301 __sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
302 __sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
305 /* Predefined SFR Bit Masks */
307 #define PCON_IDLE 0x01 /* PCON */
308 #define PCON_STOP 0x02 /* PCON */
309 #define T1M 0x08 /* CKCON */
310 #define PSWE 0x01 /* PSCTL */
311 #define PSEE 0x02 /* PSCTL */
312 #define ECP0 0x20 /* EIE1 */
313 #define PORSF 0x02 /* RSTSRC */
314 #define SWRSF 0x10 /* RSTSRC */
315 #define ECCF 0x01 /* PCA0CPMn */
316 #define PWM 0x02 /* PCA0CPMn */
317 #define TOG 0x04 /* PCA0CPMn */
318 #define MAT 0x08 /* PCA0CPMn */
319 #define CAPN 0x10 /* PCA0CPMn */
320 #define CAPP 0x20 /* PCA0CPMn */
321 #define ECOM 0x40 /* PCA0CPMn */
322 #define PWM16 0x80 /* PCA0CPMn */
323 #define CP0E 0x10 /* XBR0 */
324 #define CP0OEN 0x10 /* XBR0 */
325 #define CP0AE 0x20 /* XBR0 */
326 #define CP0AOEN 0x20 /* XBR0 */
projects / debian / cc1111 / blob