1 /*---------------------------------------------------------------------------
2 Register Declarations for the Cygnal/SiLabs C8051F018-F019 Processor Range
4 Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 ---------------------------------------------------------------------------*/
26 __sfr __at (0x80) P0 ; /* PORT 0 */
27 __sfr __at (0x81) SP ; /* STACK POINTER */
28 __sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
29 __sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
30 __sfr __at (0x87) PCON ; /* POWER CONTROL */
31 __sfr __at (0x88) TCON ; /* TIMER CONTROL */
32 __sfr __at (0x89) TMOD ; /* TIMER MODE */
33 __sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
34 __sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
35 __sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
36 __sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
37 __sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
38 __sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
39 __sfr __at (0x90) P1 ; /* PORT 1 */
40 __sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
41 __sfr __at (0x92) TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
42 __sfr __at (0x93) TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
43 __sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
44 __sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
45 __sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
46 __sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
47 __sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
48 __sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
49 __sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
50 __sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 CONTROL */
51 __sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 CONTROL */
52 __sfr __at (0xA0) P2 ; /* PORT 2 */
53 __sfr __at (0xA4) PRT0CF ; /* PORT 0 CONFIGURATION */
54 __sfr __at (0xA5) PRT1CF ; /* PORT 1 CONFIGURATION */
55 __sfr __at (0xA6) PRT2CF ; /* PORT 2 CONFIGURATION */
56 __sfr __at (0xA7) PRT3CF ; /* PORT 3 CONFIGURATION */
57 __sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
58 __sfr __at (0xAD) PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */
59 __sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
60 __sfr __at (0xAF) _XPAGE ; /* XDATA/PDATA PAGE */
61 __sfr __at (0xB0) P3 ; /* PORT 3 */
62 __sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
63 __sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
64 __sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
65 __sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */
66 __sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
67 __sfr __at (0xBA) AMX0CF ; /* ADC 0 MUX CONFIGURATION */
68 __sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
69 __sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
70 __sfr __at (0xBE) ADC0L ; /* ADC 0 DATA - LOW BYTE */
71 __sfr __at (0xBF) ADC0H ; /* ADC 0 DATA - HIGH BYTE */
72 __sfr __at (0xC0) SMB0CN ; /* SMBUS 0 CONTROL */
73 __sfr __at (0xC1) SMB0STA ; /* SMBUS 0 STATUS */
74 __sfr __at (0xC2) SMB0DAT ; /* SMBUS 0 DATA */
75 __sfr __at (0xC3) SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
76 __sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
77 __sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
78 __sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
79 __sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
80 __sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
81 __sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
82 __sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
83 __sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
84 __sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
85 __sfr __at (0xCF) SMB0CR ; /* SMBUS 0 CLOCK RATE */
86 __sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
87 __sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
88 __sfr __at (0xD8) PCA0CN ; /* PCA 0 COUNTER CONTROL */
89 __sfr __at (0xD9) PCA0MD ; /* PCA 0 COUNTER MODE */
90 __sfr __at (0xDA) PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
91 __sfr __at (0xDB) PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
92 __sfr __at (0xDC) PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
93 __sfr __at (0xDD) PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
94 __sfr __at (0xDE) PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
95 __sfr __at (0xE0) ACC ; /* ACCUMULATOR */
96 __sfr __at (0xE1) XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
97 __sfr __at (0xE2) XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
98 __sfr __at (0xE3) XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
99 __sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
100 __sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
101 __sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
102 __sfr __at (0xE9) PCA0L ; /* PCA 0 TIMER - LOW BYTE */
103 __sfr __at (0xEA) PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
104 __sfr __at (0xEB) PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
105 __sfr __at (0xEC) PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
106 __sfr __at (0xED) PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
107 __sfr __at (0xEE) PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
108 __sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
109 __sfr __at (0xF0) B ; /* B REGISTER */
110 __sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
111 __sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
112 __sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
113 __sfr __at (0xF9) PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
114 __sfr __at (0xFA) PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
115 __sfr __at (0xFB) PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
116 __sfr __at (0xFC) PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
117 __sfr __at (0xFD) PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
118 __sfr __at (0xFE) PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
119 __sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER CONTROL */
122 /* WORD/DWORD Registers */
124 __sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
125 __sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
126 __sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
127 __sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
128 __sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
129 __sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
130 __sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
131 __sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
132 __sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
133 __sfr16 __at (0xF9E9) PCA0 ; /* PCA COUNTER */
134 __sfr16 __at (0xFAEA) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
135 __sfr16 __at (0xFBEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
136 __sfr16 __at (0xFCEC) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
137 __sfr16 __at (0xFDED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
138 __sfr16 __at (0xFEEE) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
144 __sbit __at (0x87) P0_7 ;
145 __sbit __at (0x86) P0_6 ;
146 __sbit __at (0x85) P0_5 ;
147 __sbit __at (0x84) P0_4 ;
148 __sbit __at (0x83) P0_3 ;
149 __sbit __at (0x82) P0_2 ;
150 __sbit __at (0x81) P0_1 ;
151 __sbit __at (0x80) P0_0 ;
154 __sbit __at (0x8F) TF1 ; /* TIMER 1 OVERFLOW FLAG */
155 __sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF CONTROL */
156 __sbit __at (0x8D) TF0 ; /* TIMER 0 OVERFLOW FLAG */
157 __sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF CONTROL */
158 __sbit __at (0x8B) IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
159 __sbit __at (0x8A) IT1 ; /* EXT. INTERRUPT 1 TYPE */
160 __sbit __at (0x89) IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
161 __sbit __at (0x88) IT0 ; /* EXT. INTERRUPT 0 TYPE */
164 __sbit __at (0x97) P1_7 ;
165 __sbit __at (0x96) P1_6 ;
166 __sbit __at (0x95) P1_5 ;
167 __sbit __at (0x94) P1_4 ;
168 __sbit __at (0x93) P1_3 ;
169 __sbit __at (0x92) P1_2 ;
170 __sbit __at (0x91) P1_1 ;
171 __sbit __at (0x90) P1_0 ;
174 __sbit __at (0x9F) SM0 ; /* SERIAL MODE CONTROL BIT 0 */
175 __sbit __at (0x9E) SM1 ; /* SERIAL MODE CONTROL BIT 1 */
176 __sbit __at (0x9D) SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */
177 __sbit __at (0x9C) REN ; /* RECEIVE ENABLE */
178 __sbit __at (0x9B) TB8 ; /* TRANSMIT BIT 8 */
179 __sbit __at (0x9A) RB8 ; /* RECEIVE BIT 8 */
180 __sbit __at (0x99) TI ; /* TRANSMIT INTERRUPT FLAG */
181 __sbit __at (0x98) RI ; /* RECEIVE INTERRUPT FLAG */
184 __sbit __at (0xA7) P2_7 ;
185 __sbit __at (0xA6) P2_6 ;
186 __sbit __at (0xA5) P2_5 ;
187 __sbit __at (0xA4) P2_4 ;
188 __sbit __at (0xA3) P2_3 ;
189 __sbit __at (0xA2) P2_2 ;
190 __sbit __at (0xA1) P2_1 ;
191 __sbit __at (0xA0) P2_0 ;
194 __sbit __at (0xAF) EA ; /* GLOBAL INTERRUPT ENABLE */
195 __sbit __at (0xAD) ET2 ; /* TIMER 2 INTERRUPT ENABLE */
196 __sbit __at (0xAC) ES ; /* SERIAL PORT INTERRUPT ENABLE */
197 __sbit __at (0xAB) ET1 ; /* TIMER 1 INTERRUPT ENABLE */
198 __sbit __at (0xAA) EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
199 __sbit __at (0xA9) ET0 ; /* TIMER 0 INTERRUPT ENABLE */
200 __sbit __at (0xA8) EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
203 __sbit __at (0xB7) P3_7 ;
204 __sbit __at (0xB6) P3_6 ;
205 __sbit __at (0xB5) P3_5 ;
206 __sbit __at (0xB4) P3_4 ;
207 __sbit __at (0xB3) P3_3 ;
208 __sbit __at (0xB2) P3_2 ;
209 __sbit __at (0xB1) P3_1 ;
210 __sbit __at (0xB0) P3_0 ;
213 __sbit __at (0xBD) PT2 ; /* TIMER 2 PRIORITY */
214 __sbit __at (0xBC) PS ; /* SERIAL PORT PRIORITY */
215 __sbit __at (0xBB) PT1 ; /* TIMER 1 PRIORITY */
216 __sbit __at (0xBA) PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
217 __sbit __at (0xB9) PT0 ; /* TIMER 0 PRIORITY */
218 __sbit __at (0xB8) PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
221 __sbit __at (0xC7) BUSY ; /* SMBUS 0 BUSY */
222 __sbit __at (0xC6) ENSMB ; /* SMBUS 0 ENABLE */
223 __sbit __at (0xC5) STA ; /* SMBUS 0 START FLAG */
224 __sbit __at (0xC4) STO ; /* SMBUS 0 STOP FLAG */
225 __sbit __at (0xC3) SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
226 __sbit __at (0xC2) AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
227 __sbit __at (0xC1) SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
228 __sbit __at (0xC0) SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
231 __sbit __at (0xCF) TF2 ; /* TIMER 2 OVERFLOW FLAG */
232 __sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */
233 __sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */
234 __sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */
235 __sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
236 __sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF CONTROL */
237 __sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */
238 __sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT */
241 __sbit __at (0xD7) CY ; /* CARRY FLAG */
242 __sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
243 __sbit __at (0xD5) F0 ; /* USER FLAG 0 */
244 __sbit __at (0xD4) RS1 ; /* REGISTER BANK SELECT 1 */
245 __sbit __at (0xD3) RS0 ; /* REGISTER BANK SELECT 0 */
246 __sbit __at (0xD2) OV ; /* OVERFLOW FLAG */
247 __sbit __at (0xD1) F1 ; /* USER FLAG 1 */
248 __sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
251 __sbit __at (0xDF) CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
252 __sbit __at (0xDE) CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
253 __sbit __at (0xDC) CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
254 __sbit __at (0xDB) CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
255 __sbit __at (0xDA) CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
256 __sbit __at (0xD9) CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
257 __sbit __at (0xD8) CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
260 __sbit __at (0xEF) AD0EN ; /* ADC 0 ENABLE */
261 __sbit __at (0xEE) AD0TM ; /* ADC 0 TRACK MODE */
262 __sbit __at (0xED) AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
263 __sbit __at (0xEC) AD0BUSY ; /* ADC 0 BUSY FLAG */
264 __sbit __at (0xEB) ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
265 __sbit __at (0xEA) ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
266 __sbit __at (0xE9) AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
267 __sbit __at (0xE8) ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
270 __sbit __at (0xFF) SPIF ; /* SPI 0 INTERRUPT FLAG */
271 __sbit __at (0xFE) WCOL ; /* SPI 0 WRITE COLLISION FLAG */
272 __sbit __at (0xFD) MODF ; /* SPI 0 MODE FAULT FLAG */
273 __sbit __at (0xFC) RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
274 __sbit __at (0xFB) TXBSY ; /* SPI 0 TX BUSY FLAG */
275 __sbit __at (0xFA) SLVSEL ; /* SPI 0 SLAVE SELECT */
276 __sbit __at (0xF9) MSTEN ; /* SPI 0 MASTER ENABLE */
277 __sbit __at (0xF8) SPIEN ; /* SPI 0 SPI ENABLE */
280 /* Predefined SFR Bit Masks */
282 #define PCON_IDLE 0x01 /* PCON */
283 #define PCON_STOP 0x02 /* PCON */
284 #define TF3 0x80 /* TMR3CN */
285 #define CPFIF 0x10 /* CPTnCN */
286 #define CPRIF 0x20 /* CPTnCN */
287 #define CPOUT 0x40 /* CPTnCN */
288 #define ECCF 0x01 /* PCA0CPMn */
289 #define PWM 0x02 /* PCA0CPMn */
290 #define TOG 0x04 /* PCA0CPMn */
291 #define MAT 0x08 /* PCA0CPMn */
292 #define CAPN 0x10 /* PCA0CPMn */
293 #define CAPP 0x20 /* PCA0CPMn */
294 #define ECOM 0x40 /* PCA0CPMn */
projects / debian / cc1111 / blob