pull in standard footprints for 0603, 0805, and 1206 parts

diff --git a/packages/0603.fp b/packages/0603.fp
new file mode 100644 (file)
index 0000000..88564d9
--- /dev/null
+++ b/packages/0603.fp
@@ -0,0 +1,32 @@
+##from:pcb
+##for:resistor
+##for:capacitor
+##for:led
+
+       # grab the input values and convert to 1/100 mil
+       # how much to grow the pads by for soldermask [1/100 mil]
+       # clearance from planes [1/100 mil]
+       # silk screen width  [1/100 mil]
+       # courtyard silk screen width  [1/100 mil]
+# element_flags, description, pcb-name, value, mark_x, mark_y,
+# text_x, text_y, text_direction, text_scale, text_flags
+Element[0x00000000 "Standard SMT resistor, capacitor etc" "" "0603" 0 0 -3150 -3150 0 100 ""]
+(
+# 
+# Pad[x1, y1, x2, y2, thickness, clearance, mask, name , pad number, flags]
+       Pad[-2559 -492
+               -2559 492
+               2952 2000 3552 "1" "1" "square"]
+           Pad[2559 -492
+               2559 492
+               2952 2000 3552 "2" "2" "square"]
+#
+# This draws a 1 mil placement courtyard outline in silk.  It should probably
+# not be included since you wont want to try and fab a 1 mil silk line.  Then
+# again, it is most useful during parts placement.  It really is time for some
+# additional non-fab layers...
+#      ElementLine[eval(-1*V1/2) eval(-1*V2/2) eval(-1*V1/2) eval(   V2/2) CYW]
+#      ElementLine[eval(-1*V1/2) eval(-1*V2/2) eval(   V1/2) eval(-1*V2/2) CYW]
+#      ElementLine[eval(   V1/2) eval(   V2/2) eval(   V1/2) eval(-1*V2/2) CYW]
+#      ElementLine[eval(   V1/2) eval(   V2/2) eval(-1*V1/2) eval(   V2/2) CYW]
+)

diff --git a/packages/0805.fp b/packages/0805.fp
new file mode 100644 (file)
index 0000000..6454ad9
--- /dev/null
+++ b/packages/0805.fp
@@ -0,0 +1,34 @@
+##from:pcb
+##for:resistor
+##for:capacitor
+##for:led
+
+       # grab the input values and convert to 1/100 mil
+       # how much to grow the pads by for soldermask [1/100 mil]
+       # clearance from planes [1/100 mil]
+       # silk screen width  [1/100 mil]
+       # courtyard silk screen width  [1/100 mil]
+# element_flags, description, pcb-name, value, mark_x, mark_y,
+# text_x, text_y, text_direction, text_scale, text_flags
+Element[0x00000000 "Standard SMT resistor, capacitor etc" "" "0805" 0 0 -3150 -3150 0 100 ""]
+(
+# 
+# Pad[x1, y1, x2, y2, thickness, clearance, mask, name , pad number, flags]
+       Pad[-3543 -393
+               -3543 393
+               5118 2000 5718 "1" "1" "square"]
+           Pad[3543 -393
+               3543 393
+               5118 2000 5718 "2" "2" "square"]
+       ElementLine[-393 -2755 393 -2755 800]
+           ElementLine[-393 2755 393 2755 800]
+#
+# This draws a 1 mil placement courtyard outline in silk.  It should probably
+# not be included since you wont want to try and fab a 1 mil silk line.  Then
+# again, it is most useful during parts placement.  It really is time for some
+# additional non-fab layers...
+#      ElementLine[eval(-1*V1/2) eval(-1*V2/2) eval(-1*V1/2) eval(   V2/2) CYW]
+#      ElementLine[eval(-1*V1/2) eval(-1*V2/2) eval(   V1/2) eval(-1*V2/2) CYW]
+#      ElementLine[eval(   V1/2) eval(   V2/2) eval(   V1/2) eval(-1*V2/2) CYW]
+#      ElementLine[eval(   V1/2) eval(   V2/2) eval(-1*V1/2) eval(   V2/2) CYW]
+)

diff --git a/packages/1206.fp b/packages/1206.fp
new file mode 100644 (file)
index 0000000..6bddc3c
--- /dev/null
+++ b/packages/1206.fp
@@ -0,0 +1,34 @@
+##from:pcb
+##for:resistor
+##for:capacitor
+##for:led
+
+       # grab the input values and convert to 1/100 mil
+       # how much to grow the pads by for soldermask [1/100 mil]
+       # clearance from planes [1/100 mil]
+       # silk screen width  [1/100 mil]
+       # courtyard silk screen width  [1/100 mil]
+# element_flags, description, pcb-name, value, mark_x, mark_y,
+# text_x, text_y, text_direction, text_scale, text_flags
+Element[0x00000000 "Standard SMT resistor, capacitor etc" "" "1206" 0 0 -3150 -3150 0 100 ""]
+(
+# 
+# Pad[x1, y1, x2, y2, thickness, clearance, mask, name , pad number, flags]
+       Pad[-5905 -1181
+               -5905 1181
+               5118 2000 5718 "1" "1" "square"]
+           Pad[5905 -1181
+               5905 1181
+               5118 2000 5718 "2" "2" "square"]
+       ElementLine[-2362 -3740 2362 -3740 800]
+           ElementLine[-2362 3740 2362 3740 800]
+#
+# This draws a 1 mil placement courtyard outline in silk.  It should probably
+# not be included since you wont want to try and fab a 1 mil silk line.  Then
+# again, it is most useful during parts placement.  It really is time for some
+# additional non-fab layers...
+#      ElementLine[eval(-1*V1/2) eval(-1*V2/2) eval(-1*V1/2) eval(   V2/2) CYW]
+#      ElementLine[eval(-1*V1/2) eval(-1*V2/2) eval(   V1/2) eval(-1*V2/2) CYW]
+#      ElementLine[eval(   V1/2) eval(   V2/2) eval(   V1/2) eval(-1*V2/2) CYW]
+#      ElementLine[eval(   V1/2) eval(   V2/2) eval(-1*V1/2) eval(   V2/2) CYW]
+)

diff --git a/preferred-parts b/preferred-parts
index c2aceb31451abf348fd645956c860b2eb5134efd..4c512cbb70e9d755148b72e5f8e90e3560df2b3a 100644 (file)
--- a/preferred-parts
+++ b/preferred-parts
@@ -163,6 +163,7 @@ IC  W25Q16  SOIJ8   smt     no      W25Q16JVSSIQ    digikey W25Q16JVSSIQ-ND
 IC     W25Q64  SOIJ8   smt     no      MX25L6406EM2I-12G       digikey 1092-1124-ND 
 IC     W25Q80BVSSIG    SOIJ8   smt     no      W25Q80BVSSIG    arrow   W25Q80BVSSIG
 IC     W25Q80DVSSIG    SOIJ8   smt     no      W25Q80DVSSIG    digikey W25Q80DVSSIG-ND
+INDUCTOR       4.7uH   M1040M  smt     no      ETQ-P4M4R7KVC   digikey P19787CT-ND
 INDUCTOR       10uH    0806    smt     no      LQH2MCN100K02L  digikey 490-4046-1-ND
 INDUCTOR       15nH    0402    smt     no      LQG15HS15NJ02D  digikey 490-2625-1-ND
 INDUCTOR       22nH    0402    smt     no      LQG15HS22NJ02D  digikey 490-2627-1-ND