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inline | side by side (from parent 1:
2ef794e)
This is the lowest power state we can reach, and consumes about 15µA
or less.
Signed-off-by: Keith Packard <keithp@keithp.com>
ao_compute_height();
ao_report_altitude();
ao_compute_height();
ao_report_altitude();
ao_sleep(&ao_on_battery);
}
ao_sleep(&ao_on_battery);
}
asm("pop {r0-r7,pc}\n");
}
asm("pop {r0-r7,pc}\n");
}
+static inline void ao_sleep_mode(void) {
+
+ /*
+ WFI (Wait for Interrupt) or WFE (Wait for Event) while:
+ – Set SLEEPDEEP in Cortex ® -M0 System Control register
+ – Set PDDS bit in Power Control register (PWR_CR)
+ – Clear WUF bit in Power Control/Status register (PWR_CSR)
+ */
+
+ ao_arch_block_interrupts();
+
+ stm_scb.scr |= (1 << STM_SCB_SCR_SLEEPDEEP);
+ ao_arch_nop();
+ stm_pwr.cr |= (1 << STM_PWR_CR_PDDS) | (1 << STM_PWR_CR_LPDS);
+ ao_arch_nop();
+ stm_pwr.cr |= (1 << STM_PWR_CR_CWUF);
+ ao_arch_nop();
+ ao_arch_nop();
+ ao_arch_nop();
+ ao_arch_nop();
+ ao_arch_nop();
+ asm("wfi");
+ ao_arch_nop();
+}
+
#ifndef HAS_SAMPLE_PROFILE
#define HAS_SAMPLE_PROFILE 0
#endif
#ifndef HAS_SAMPLE_PROFILE
#define HAS_SAMPLE_PROFILE 0
#endif
extern struct stm_pwr stm_pwr;
extern struct stm_pwr stm_pwr;
+#define stm_pwr (*(struct stm_pwr *) 0x40007000)
+
#define STM_PWR_CR_DBP (8)
#define STM_PWR_CR_PLS (5)
#define STM_PWR_CR_DBP (8)
#define STM_PWR_CR_PLS (5)
#define STM_PWR_CR_CSBF (3)
#define STM_PWR_CR_CWUF (2)
#define STM_PWR_CR_PDDS (1)
#define STM_PWR_CR_CSBF (3)
#define STM_PWR_CR_CWUF (2)
#define STM_PWR_CR_PDDS (1)
-#define STM_PWR_CR_LPSDSR (0)
+#define STM_PWR_CR_LPDS (0)
#define STM_PWR_CSR_EWUP3 (10)
#define STM_PWR_CSR_EWUP2 (9)
#define STM_PWR_CSR_EWUP3 (10)
#define STM_PWR_CSR_EWUP2 (9)
extern struct stm_scb stm_scb;
extern struct stm_scb stm_scb;
+#define stm_scb (*(struct stm_scb *) 0xe000ed00)
+
#define STM_SCB_AIRCR_VECTKEY 16
#define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa
#define STM_SCB_AIRCR_PRIGROUP 8
#define STM_SCB_AIRCR_VECTKEY 16
#define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa
#define STM_SCB_AIRCR_PRIGROUP 8
#define STM_SCB_AIRCR_VECTCLRACTIVE 1
#define STM_SCB_AIRCR_VECTRESET 0
#define STM_SCB_AIRCR_VECTCLRACTIVE 1
#define STM_SCB_AIRCR_VECTRESET 0
+#define STM_SCB_SCR_SEVONPEND 4
+#define STM_SCB_SCR_SLEEPDEEP 2
+#define STM_SCB_SCR_SLEEPONEXIT 1
+
#define STM_ISR_WWDG_POS 0
#define STM_ISR_PVD_VDDIO2_POS 1
#define STM_ISR_RTC_POS 2
#define STM_ISR_WWDG_POS 0
#define STM_ISR_PVD_VDDIO2_POS 1
#define STM_ISR_RTC_POS 2