explicitly do not include frontsilk in the zip file .. the refdes info is not

[hw/telemini] / telemini.pcb

diff --git a/telemini.pcb b/telemini.pcb
index e6af3f71b08483a1f1f3e4c399a937ddf6df1b55..d12ba1ea09e4d079a4820ba71b8a2d4a3feb47d5 100644 (file)
--- a/telemini.pcb
+++ b/telemini.pcb
@@ -1,5 +1,5 @@
 # release: pcb 20100929
-# date:    Thu Apr 21 16:47:23 2011
+# date:    Sun Jun  5 20:09:17 2011
 # user:    bdale (Bdale Garbee,KB0G)
 # host:    rover
 
@@ -1229,7 +1229,7 @@ Element["" "hole-M2.5" "H1" "unknown" 140000 10000 -2352 -3100 0 100 ""]
 
        )
 
-Element["onsolder" "100mil2pin" "J1" "PowerSwitch" 73200 4200 -12500 -3000 2 100 "auto"]
+Element["onsolder" "100mil2pin" "J1" "Power" 73200 4200 -12500 -3000 2 100 "auto"]
 (
        Pin[0 0 6000 2400 7000 3800 "1" "1" "edge2"]
        Pin[-10000 0 6000 2000 7000 3800 "2" "2" "edge2"]
@@ -1718,8 +1718,10 @@ Layer(3 "outline")
 Layer(4 "silk")
 (
        Text[127215 35422 3 100 "` 2011" "auto"]
-       Text[134093 42768 3 100 "TeleMini  v0.2" "auto"]
+       Text[134093 42768 3 100 "TeleMini  v1.0" "auto"]
        Text[121400 43400 3 100 "Bdale Garbee" "auto"]
+       Text[35000 44500 3 100 "apogee    main" "auto"]
+       Text[63100 13500 0 100 "pwr" "clearline,auto"]
        Polygon("clearpoly")
        (
                [134800 34000] [149100 34000] [149100 16000] [134800 16000]