add apogee / main labels to silk screen

[hw/telemini] / telemini.pcb

diff --git a/telemini.pcb b/telemini.pcb
index c4daad0cc3c86d53562526af26e2e37d11508199..9f4e52f4992850d0ff012f9e469773b2699e60d4 100644 (file)
--- a/telemini.pcb
+++ b/telemini.pcb
@@ -1,5 +1,5 @@
 # release: pcb 20100929
-# date:    Thu Apr 21 16:41:50 2011
+# date:    Fri May 13 15:11:33 2011
 # user:    bdale (Bdale Garbee,KB0G)
 # host:    rover
 
@@ -9,11 +9,11 @@ FileVersion[20100606]
 PCB["TeleMini" 150000 50000]
 
 Grid[100.000000 0 0 0]
-Cursor[0 0 0.000000]
+Cursor[0 50000 0.000000]
 PolyArea[200000000.000000]
 Thermal[0.500000]
 DRC[600 1000 600 500 1500 700]
-Flags("nameonpcb,clearnew,snappin,liveroute,hidenames")
+Flags("nameonpcb,clearnew,liveroute,hidenames")
 Groups("1,c:2,s:3")
 Styles["Signal,1000,2900,1500,1000:Power,2500,6000,3500,1000:Fat,2500,6000,3500,1000:Skinny,600,2402,1181,600"]
 
@@ -1229,7 +1229,7 @@ Element["" "hole-M2.5" "H1" "unknown" 140000 10000 -2352 -3100 0 100 ""]
 
        )
 
-Element["onsolder" "100mil2pin" "J1" "PowerSwitch" 73200 4200 -12500 -3000 2 100 "auto"]
+Element["onsolder" "100mil2pin" "J1" "Power" 73200 4200 -12500 -3000 2 100 "auto"]
 (
        Pin[0 0 6000 2400 7000 3800 "1" "1" "edge2"]
        Pin[-10000 0 6000 2000 7000 3800 "2" "2" "edge2"]
@@ -1720,6 +1720,11 @@ Layer(4 "silk")
        Text[127215 35422 3 100 "` 2011" "auto"]
        Text[134093 42768 3 100 "TeleMini  v0.2" "auto"]
        Text[121400 43400 3 100 "Bdale Garbee" "auto"]
+       Text[35000 44500 3 100 "apogee    main" "auto"]
+       Polygon("clearpoly")
+       (
+               [134800 34000] [149100 34000] [149100 16000] [134800 16000] 
+       )
 )
 Layer(5 "silk")
 (