2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #include "ao_product.h"
26 #define USB_DEBUG_DATA 0
29 #ifndef AO_PA11_PA12_RMP
30 #error "must define AO_PA11_PA12_RMP"
33 #ifndef AO_POWER_MANAGEMENT
34 #define AO_POWER_MANAGEMENT 0
38 #define USE_USB_STDIO 1
42 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
44 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
48 #define debug(format, args...) printf(format, ## args);
50 #define debug(format, args...)
54 #define debug_data(format, args...) printf(format, ## args);
56 #define debug_data(format, args...)
60 uint8_t dir_type_recip;
67 static uint8_t ao_usb_ep0_state;
69 /* Pending EP0 IN data */
70 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
71 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
73 /* Temp buffer for smaller EP0 in data */
74 static uint8_t ao_usb_ep0_in_buf[2];
76 /* Pending EP0 OUT data */
77 static uint8_t *ao_usb_ep0_out_data;
78 static uint8_t ao_usb_ep0_out_len;
81 * Objects allocated in special USB memory
84 /* Buffer description tables */
85 static union stm_usb_bdt *ao_usb_bdt;
86 /* USB address of end of allocated storage */
88 static uint16_t ao_usb_sram_addr;
91 /* Pointer to ep0 tx/rx buffers in USB memory */
92 static uint16_t *ao_usb_ep0_tx_buffer;
93 static uint16_t *ao_usb_ep0_rx_buffer;
96 /* Pointer to interrupt buffer in USB memory */
97 static uint16_t ao_usb_int_tx_offset;
100 /* Pointer to bulk data tx/rx buffers in USB memory */
102 static uint16_t ao_usb_in_tx_offset[2];
103 static uint16_t *ao_usb_in_tx_buffer[2];
104 static uint8_t ao_usb_in_tx_which;
105 static uint8_t ao_usb_tx_count;
109 static uint16_t ao_usb_out_rx_offset;
110 static uint16_t *ao_usb_out_rx_buffer;
112 /* System ram shadow of USB buffer; writing individual bytes is
113 * too much of a pain (sigh) */
114 static uint8_t ao_usb_rx_buffer[AO_USB_OUT_SIZE];
115 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
119 static uint16_t ao_usb_in2_tx_offset[2];
120 static uint16_t *ao_usb_in2_tx_buffer[2];
121 static uint8_t ao_usb_in_tx2_which;
122 static uint8_t ao_usb_tx2_count;
126 * End point register indices
129 #define AO_USB_CONTROL_EPR 0
130 #define AO_USB_INT_EPR 1
131 #define AO_USB_OUT_EPR 2
132 #define AO_USB_IN_EPR 3
133 #define AO_USB_IN2_EPR 4
135 /* Marks when we don't need to send an IN packet.
136 * This happens only when the last IN packet is not full,
137 * otherwise the host will expect to keep seeing packets.
138 * Send a zero-length packet as required
140 static uint8_t ao_usb_in_flushed;
142 /* Marks when we have delivered an IN packet to the hardware
143 * and it has not been received yet. ao_sleep on this address
144 * to wait for it to be delivered.
146 static uint8_t ao_usb_in_pending;
149 /* Marks when we have delivered an IN packet to the hardware
150 * and it has not been received yet. ao_sleep on this address
151 * to wait for it to be delivered.
153 static uint8_t ao_usb_in2_pending;
154 static uint16_t in2_count;
155 static uint8_t ao_usb_in2_flushed;
158 /* Marks when an OUT packet has been received by the hardware
159 * but not pulled to the shadow buffer.
161 static uint8_t ao_usb_out_avail;
162 uint8_t ao_usb_running;
163 static uint8_t ao_usb_configuration;
165 #define AO_USB_EP0_GOT_SETUP 1
166 #define AO_USB_EP0_GOT_RX_DATA 2
167 #define AO_USB_EP0_GOT_TX_ACK 4
169 static uint8_t ao_usb_ep0_receive;
170 static uint8_t ao_usb_address;
171 static uint8_t ao_usb_address_pending;
173 static inline uint32_t set_toggle(uint32_t current_value,
175 uint32_t desired_value)
177 return (current_value ^ desired_value) & mask;
180 static inline uint16_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
182 return (uint16_t *) (void *) (stm_usb_sram + sram_addr);
185 static inline uint16_t ao_usb_packet_buffer_offset(uint16_t *addr)
187 return (uint16_t) ((uint8_t *) addr - stm_usb_sram);
190 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
191 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
194 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
195 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
198 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
199 return (epr >> STM_USB_EPR_CTR_RX) & 1;
202 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
203 return (epr >> STM_USB_EPR_CTR_TX) & 1;
206 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
207 return (epr >> STM_USB_EPR_SETUP) & 1;
210 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
211 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
214 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
215 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
219 * Set current device address and mark the
220 * interface as active
223 ao_usb_set_address(uint8_t address)
225 debug("ao_usb_set_address %02x\n", address);
226 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
227 ao_usb_address_pending = 0;
231 * Write these values to preserve register contents under HW changes
234 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
235 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
236 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
237 (1 << STM_USB_EPR_CTR_TX) | \
238 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
239 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
241 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
242 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
243 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
244 (1 << STM_USB_EPR_CTR_TX) | \
245 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
246 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
249 * These bits are purely under sw control, so preserve them in the
250 * register by re-writing what was read
252 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
253 (1 << STM_USB_EPR_EP_KIND) | \
254 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
260 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
261 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
263 #define _tx_dbg0(msg)
264 #define _tx_dbg1(msg,value)
268 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
269 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
271 #define _rx_dbg0(msg)
272 #define _rx_dbg1(msg,value)
276 static void _dbg(int line, char *msg, uint32_t value);
280 * Set the state of the specified endpoint register to a new
281 * value. This is tricky because the bits toggle where the new
282 * value is one, and we need to write invariant values in other
283 * spots of the register. This hardware is strange...
286 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
288 uint16_t epr_write, epr_old;
290 _tx_dbg1("set_stat_tx top", stat_tx);
291 epr_old = epr_write = stm_usb.epr[ep].r;
292 epr_write &= STM_USB_EPR_PRESERVE_MASK;
293 epr_write |= STM_USB_EPR_INVARIANT;
294 epr_write |= set_toggle(epr_old,
295 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
296 stat_tx << STM_USB_EPR_STAT_TX);
297 stm_usb.epr[ep].r = epr_write;
298 _tx_dbg1("set_stat_tx bottom", epr_write);
302 _ao_usb_toggle_dtog(int ep, uint32_t dtog_rx, uint32_t dtog_tx)
306 _tx_dbg1("toggle_dtog top", dtog_rx);
307 epr_write = stm_usb.epr[ep].r;
308 epr_write &= STM_USB_EPR_PRESERVE_MASK;
309 epr_write |= STM_USB_EPR_INVARIANT;
310 epr_write |= ((dtog_rx << STM_USB_EPR_DTOG_RX) |
311 (dtog_tx << STM_USB_EPR_DTOG_TX));
312 stm_usb.epr[ep].r = epr_write;
313 _tx_dbg1("toggle_dtog bottom", epr_write);
317 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
319 ao_arch_block_interrupts();
320 _ao_usb_set_stat_tx(ep, stat_tx);
321 ao_arch_release_interrupts();
325 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
326 uint16_t epr_write, epr_old;
328 epr_write = epr_old = stm_usb.epr[ep].r;
329 epr_write &= STM_USB_EPR_PRESERVE_MASK;
330 epr_write |= STM_USB_EPR_INVARIANT;
331 epr_write |= set_toggle(epr_old,
332 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
333 stat_rx << STM_USB_EPR_STAT_RX);
334 stm_usb.epr[ep].r = epr_write;
338 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
339 ao_arch_block_interrupts();
340 _ao_usb_set_stat_rx(ep, stat_rx);
341 ao_arch_release_interrupts();
345 * Set just endpoint 0, for use during startup
349 ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint32_t stat_tx, uint32_t kind, uint32_t dtog_rx, uint32_t dtog_tx)
353 ao_arch_block_interrupts();
354 epr = stm_usb.epr[ep].r;
355 epr = ((0 << STM_USB_EPR_CTR_RX) |
356 (type << STM_USB_EPR_EP_TYPE) |
357 (kind << STM_USB_EPR_EP_KIND) |
358 (0 << STM_USB_EPR_CTR_TX) |
359 (addr << STM_USB_EPR_EA) |
362 (1 << STM_USB_EPR_DTOG_RX) |
363 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) |
364 (1 << STM_USB_EPR_DTOG_TX) |
365 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
367 (dtog_rx << STM_USB_EPR_DTOG_RX) |
368 (stat_rx << STM_USB_EPR_STAT_RX) |
369 (dtog_tx << STM_USB_EPR_DTOG_TX) |
370 (stat_tx << STM_USB_EPR_STAT_TX)));
371 stm_usb.epr[ep].r = epr;
372 ao_arch_release_interrupts();
373 debug ("writing epr[%d] 0x%04x wrote 0x%04x\n",
374 ep, epr, stm_usb.epr[ep].r);
378 ao_usb_alloc_buffers(void)
380 uint16_t sram_addr = 0;
382 ao_usb_bdt = (void *) stm_usb_sram;
383 sram_addr += 8 * STM_USB_BDT_SIZE;
385 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(sram_addr);
386 sram_addr += AO_USB_CONTROL_SIZE;
388 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(sram_addr);
389 sram_addr += AO_USB_CONTROL_SIZE;
393 sram_addr += (sram_addr & 1);
394 ao_usb_int_tx_offset = sram_addr;
395 sram_addr += AO_USB_INT_SIZE;
399 sram_addr += (sram_addr & 1);
400 ao_usb_out_rx_buffer = ao_usb_packet_buffer_addr(sram_addr);
401 ao_usb_out_rx_offset = sram_addr;
402 sram_addr += AO_USB_OUT_SIZE;
406 sram_addr += (sram_addr & 1);
407 ao_usb_in_tx_buffer[0] = ao_usb_packet_buffer_addr(sram_addr);
408 ao_usb_in_tx_offset[0] = sram_addr;
409 sram_addr += AO_USB_IN_SIZE;
410 ao_usb_in_tx_buffer[1] = ao_usb_packet_buffer_addr(sram_addr);
411 ao_usb_in_tx_offset[1] = sram_addr;
412 sram_addr += AO_USB_IN_SIZE;
413 ao_usb_in_tx_which = 0;
417 sram_addr += (sram_addr & 1);
418 ao_usb_in2_tx_buffer[0] = ao_usb_packet_buffer_addr(sram_addr);
419 ao_usb_in2_tx_offset[0] = sram_addr;
420 sram_addr += AO_USB_IN_SIZE;
422 sram_addr += (sram_addr & 1);
423 ao_usb_in2_tx_buffer[1] = ao_usb_packet_buffer_addr(sram_addr);
424 ao_usb_in2_tx_offset[1] = sram_addr;
425 sram_addr += AO_USB_IN_SIZE;
426 ao_usb_in2_tx_which = 0;
430 sram_addr += (sram_addr & 1);
431 ao_usb_sram_addr = sram_addr;
436 ao_usb_init_btable(void)
438 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
440 ao_usb_bdt[0].single.addr_tx = ao_usb_packet_buffer_offset(ao_usb_ep0_tx_buffer);
441 ao_usb_bdt[0].single.count_tx = 0;
443 ao_usb_bdt[0].single.addr_rx = ao_usb_packet_buffer_offset(ao_usb_ep0_rx_buffer);
444 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
445 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
453 ao_usb_init_btable();
455 /* buffer table is at the start of USB memory */
458 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
459 STM_USB_EPR_EP_TYPE_CONTROL,
460 STM_USB_EPR_STAT_RX_VALID,
461 STM_USB_EPR_STAT_TX_NAK,
462 STM_USB_EPR_EP_KIND_NO_STATUS_OUT, 0, 0);
464 /* Clear all of the other endpoints */
465 for (e = 1; e < 8; e++) {
467 STM_USB_EPR_EP_TYPE_CONTROL,
468 STM_USB_EPR_STAT_RX_DISABLED,
469 STM_USB_EPR_STAT_TX_DISABLED,
470 STM_USB_EPR_EP_KIND_SNGL_BUF, 0, 0);
473 ao_usb_set_address(0);
477 /* Reset our internal state
480 ao_usb_ep0_state = AO_USB_EP0_IDLE;
482 ao_usb_ep0_in_data = NULL;
483 ao_usb_ep0_in_len = 0;
485 ao_usb_ep0_out_data = 0;
486 ao_usb_ep0_out_len = 0;
490 ao_usb_set_configuration(void)
492 debug ("ao_usb_set_configuration\n");
495 /* Set up the INT end point */
496 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_int_tx_offset;
497 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
499 ao_usb_init_ep(AO_USB_INT_EPR,
501 STM_USB_EPR_EP_TYPE_INTERRUPT,
502 STM_USB_EPR_STAT_RX_DISABLED,
503 STM_USB_EPR_STAT_TX_NAK,
504 STM_USB_EPR_EP_KIND_SNGL_BUF, 0, 0);
508 /* Set up the OUT end point */
509 ao_usb_bdt[AO_USB_OUT_EPR].single.addr_rx = ao_usb_out_rx_offset;
510 ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
511 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
513 ao_usb_init_ep(AO_USB_OUT_EPR,
515 STM_USB_EPR_EP_TYPE_BULK,
516 STM_USB_EPR_STAT_RX_VALID,
517 STM_USB_EPR_STAT_TX_DISABLED,
518 STM_USB_EPR_EP_KIND_SNGL_BUF, 0, 0);
522 /* Set up the IN end point */
523 ao_usb_bdt[AO_USB_IN_EPR].double_tx[0].addr = ao_usb_in_tx_offset[0];
524 ao_usb_bdt[AO_USB_IN_EPR].double_tx[0].count = 0;
525 ao_usb_bdt[AO_USB_IN_EPR].double_tx[1].addr = ao_usb_in_tx_offset[1];
526 ao_usb_bdt[AO_USB_IN_EPR].double_tx[1].count = 0;
528 /* set 'our' buffer to 0, and the device buffer to 1 */
529 ao_usb_init_ep(AO_USB_IN_EPR,
531 STM_USB_EPR_EP_TYPE_BULK,
532 STM_USB_EPR_STAT_RX_DISABLED,
533 STM_USB_EPR_STAT_TX_NAK,
534 STM_USB_EPR_EP_KIND_DBL_BUF,
539 /* Set up the IN2 end point */
540 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = 0;
541 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = 0;
543 ao_usb_init_ep(AO_USB_IN2_EPR,
545 STM_USB_EPR_EP_TYPE_BULK,
546 STM_USB_EPR_STAT_RX_DISABLED,
547 STM_USB_EPR_STAT_TX_NAK,
548 STM_USB_EPR_EP_KIND_DBL_BUF,
552 ao_usb_in_flushed = 0;
553 ao_usb_in_pending = 0;
554 ao_wakeup(&ao_usb_in_pending);
556 ao_usb_in2_flushed = 0;
557 ao_usb_in2_pending = 0;
558 ao_wakeup(&ao_usb_in2_pending);
561 ao_usb_out_avail = 0;
562 ao_usb_configuration = 0;
564 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
568 ao_wakeup(&ao_usb_running);
573 static uint16_t control_count;
574 static uint16_t int_count;
575 static uint16_t in_count;
576 static uint16_t out_count;
577 static uint16_t reset_count;
580 /* The USB memory must be accessed in 16-bit units
584 ao_usb_copy_tx(const uint8_t *src, uint16_t *base, uint16_t bytes)
587 *base++ = src[0] | (src[1] << 8);
596 ao_usb_copy_rx(uint8_t *dst, uint16_t *base, uint16_t bytes)
599 uint16_t s = *base++;
610 ao_usb_tx_byte(uint16_t *base, uint8_t tx_count, char byte)
613 base[tx_count >> 1] |= ((uint16_t) byte) << 8;
615 base[tx_count >> 1] = (uint16_t) (uint8_t) byte;
619 /* Send an IN data packet */
621 ao_usb_ep0_flush(void)
625 /* Check to see if the endpoint is still busy */
626 if (ao_usb_epr_stat_tx(stm_usb.epr[0].r) == STM_USB_EPR_STAT_TX_VALID) {
627 debug("EP0 not accepting IN data\n");
631 this_len = ao_usb_ep0_in_len;
632 if (this_len > AO_USB_CONTROL_SIZE)
633 this_len = AO_USB_CONTROL_SIZE;
635 if (this_len < AO_USB_CONTROL_SIZE)
636 ao_usb_ep0_state = AO_USB_EP0_IDLE;
638 ao_usb_ep0_in_len -= this_len;
640 debug_data ("Flush EP0 len %d:", this_len);
641 ao_usb_copy_tx(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, this_len);
643 ao_usb_ep0_in_data += this_len;
645 /* Mark the endpoint as TX valid to send the packet */
646 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
647 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
648 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
651 /* Read data from the ep0 OUT fifo */
653 ao_usb_ep0_fill(void)
655 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
657 if (len > ao_usb_ep0_out_len)
658 len = ao_usb_ep0_out_len;
659 ao_usb_ep0_out_len -= len;
661 /* Pull all of the data out of the packet */
662 debug_data ("Fill EP0 len %d:", len);
663 ao_usb_copy_rx(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, len);
665 ao_usb_ep0_out_data += len;
668 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
672 ao_usb_ep0_in_reset(void)
674 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
675 ao_usb_ep0_in_len = 0;
679 ao_usb_ep0_in_queue_byte(uint8_t a)
681 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
682 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
686 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
688 ao_usb_ep0_in_data = data;
689 ao_usb_ep0_in_len = len;
693 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
695 ao_usb_ep0_out_data = data;
696 ao_usb_ep0_out_len = len;
700 ao_usb_ep0_in_start(uint16_t max)
702 /* Don't send more than asked for */
703 if (ao_usb_ep0_in_len > max)
704 ao_usb_ep0_in_len = max;
708 struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
710 #if AO_USB_DEVICE_ID_SERIAL
711 static uint8_t ao_usb_serial[2 + 48];
713 /* Convert a 32-bit value to 8 hexidecimal UCS2 characters */
715 hex_to_ucs2(uint32_t in, uint8_t *out)
719 for (i = 28; i >= 0; i -= 4) {
720 uint8_t bits = (in >> i) & 0xf;
721 *out++ = ((bits < 10) ? '0' : ('a' - 10)) + bits;
726 /* Encode the device ID (96 bits) in hexidecimal to use as a device
730 ao_usb_serial_init(void)
732 ao_usb_serial[0] = 50; /* length */
733 ao_usb_serial[1] = AO_USB_DESC_STRING;
734 hex_to_ucs2(stm_device_id.u_id0, ao_usb_serial + 2 + 0);
735 hex_to_ucs2(stm_device_id.u_id1, ao_usb_serial + 2 + 16);
736 hex_to_ucs2(stm_device_id.u_id2, ao_usb_serial + 2 + 32);
740 /* Walk through the list of descriptors and find a match
743 ao_usb_get_descriptor(uint16_t value, uint16_t length)
745 const uint8_t *descriptor;
746 uint8_t type = value >> 8;
747 uint8_t index = value;
749 descriptor = ao_usb_descriptors;
750 while (descriptor[0] != 0) {
751 if (descriptor[1] == type && index-- == 0) {
753 if (type == AO_USB_DESC_CONFIGURATION)
757 #if AO_USB_DEVICE_ID_SERIAL
758 /* Slightly hacky - the serial number is string 3 */
759 if (type == AO_USB_DESC_STRING && (value & 0xff) == 3) {
760 descriptor = ao_usb_serial;
761 len = sizeof (ao_usb_serial);
766 ao_usb_ep0_in_set(descriptor, len);
769 descriptor += descriptor[0];
774 ao_usb_ep0_setup(void)
776 /* Pull the setup packet out of the fifo */
777 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
779 if (ao_usb_ep0_out_len != 0) {
780 debug ("invalid setup packet length\n");
784 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
785 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
787 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
789 ao_usb_ep0_in_reset();
791 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
792 case AO_USB_TYPE_STANDARD:
793 debug ("Standard setup packet\n");
794 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
795 case AO_USB_RECIP_DEVICE:
796 debug ("Device setup packet\n");
797 switch(ao_usb_setup.request) {
798 case AO_USB_REQ_GET_STATUS:
799 debug ("get status\n");
800 ao_usb_ep0_in_queue_byte(0);
801 ao_usb_ep0_in_queue_byte(0);
803 case AO_USB_REQ_SET_ADDRESS:
804 debug ("set address %d\n", ao_usb_setup.value);
805 ao_usb_address = ao_usb_setup.value;
806 ao_usb_address_pending = 1;
808 case AO_USB_REQ_GET_DESCRIPTOR:
809 debug ("get descriptor %d\n", ao_usb_setup.value);
810 ao_usb_get_descriptor(ao_usb_setup.value, ao_usb_setup.length);
812 case AO_USB_REQ_GET_CONFIGURATION:
813 debug ("get configuration %d\n", ao_usb_configuration);
814 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
816 case AO_USB_REQ_SET_CONFIGURATION:
817 ao_usb_configuration = ao_usb_setup.value;
818 debug ("set configuration %d\n", ao_usb_configuration);
819 ao_usb_set_configuration();
823 case AO_USB_RECIP_INTERFACE:
824 debug ("Interface setup packet\n");
825 switch(ao_usb_setup.request) {
826 case AO_USB_REQ_GET_STATUS:
827 ao_usb_ep0_in_queue_byte(0);
828 ao_usb_ep0_in_queue_byte(0);
830 case AO_USB_REQ_GET_INTERFACE:
831 ao_usb_ep0_in_queue_byte(0);
833 case AO_USB_REQ_SET_INTERFACE:
837 case AO_USB_RECIP_ENDPOINT:
838 debug ("Endpoint setup packet\n");
839 switch(ao_usb_setup.request) {
840 case AO_USB_REQ_GET_STATUS:
841 ao_usb_ep0_in_queue_byte(0);
842 ao_usb_ep0_in_queue_byte(0);
848 case AO_USB_TYPE_CLASS:
849 debug ("Class setup packet\n");
850 switch (ao_usb_setup.request) {
851 case AO_USB_SET_LINE_CODING:
852 debug ("set line coding\n");
853 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
855 case AO_USB_GET_LINE_CODING:
856 debug ("get line coding\n");
857 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
859 case AO_USB_SET_CONTROL_LINE_STATE:
865 /* If we're not waiting to receive data from the host,
866 * queue an IN response
868 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
869 ao_usb_ep0_in_start(ao_usb_setup.length);
873 ao_usb_ep0_handle(uint8_t receive)
875 ao_usb_ep0_receive = 0;
876 if (receive & AO_USB_EP0_GOT_SETUP) {
880 if (receive & AO_USB_EP0_GOT_RX_DATA) {
881 debug ("\tgot rx data\n");
882 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
884 if (ao_usb_ep0_out_len == 0) {
885 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
886 ao_usb_ep0_in_start(0);
890 if (receive & AO_USB_EP0_GOT_TX_ACK) {
891 debug ("\tgot tx ack\n");
893 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
894 ao_flight_force_idle = 1;
896 /* Wait until the IN packet is received from addr 0
897 * before assigning our local address
899 if (ao_usb_address_pending)
900 ao_usb_set_address(ao_usb_address);
901 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
906 #if AO_POWER_MANAGEMENT
910 stm_usb.cntr |= (1 << STM_USB_CNTR_FSUSP);
912 stm_usb.cntr |= (1 << STM_USB_CNTR_LP_MODE);
920 stm_usb.cntr &= ~(1 << STM_USB_CNTR_FSUSP);
928 uint32_t istr = stm_usb.istr;
930 stm_usb.istr = ~istr;
931 if (istr & (1 << STM_USB_ISTR_CTR)) {
932 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
933 uint16_t epr, epr_write;
935 /* Preserve the SW write bits, don't mess with most HW writable bits,
936 * clear the CTR_RX and CTR_TX bits
938 epr = stm_usb.epr[ep].r;
940 epr_write &= STM_USB_EPR_PRESERVE_MASK;
941 epr_write |= STM_USB_EPR_INVARIANT;
942 epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
943 epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
944 stm_usb.epr[ep].r = epr_write;
951 if (ao_usb_epr_ctr_rx(epr)) {
952 if (ao_usb_epr_setup(epr))
953 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
955 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
957 if (ao_usb_epr_ctr_tx(epr))
958 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
959 ao_usb_ep0_handle(ao_usb_ep0_receive);
965 if (ao_usb_epr_ctr_rx(epr)) {
966 _rx_dbg1("RX ISR", epr);
967 ao_usb_out_avail = 1;
968 _rx_dbg0("out avail set");
969 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
970 _rx_dbg0("stdin awoken");
977 _tx_dbg1("TX ISR", epr);
978 if (ao_usb_epr_ctr_tx(epr)) {
979 ao_usb_in_pending = 0;
980 ao_wakeup(&ao_usb_in_pending);
986 _tx_dbg1("TX2 ISR", epr);
987 if (ao_usb_epr_ctr_tx(epr)) {
988 ao_usb_in2_pending = 0;
989 ao_wakeup(&ao_usb_in2_pending);
997 if (ao_usb_epr_ctr_tx(epr))
998 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
1004 if (istr & (1 << STM_USB_ISTR_RESET)) {
1008 debug ("\treset\n");
1011 #if AO_POWER_MANAGEMENT
1012 if (istr & (1 << STM_USB_ISTR_SUSP)) {
1013 debug ("\tsuspend\n");
1016 if (istr & (1 << STM_USB_ISTR_WKUP)) {
1017 debug ("\twakeup\n");
1024 /* Queue the current IN buffer for transmission */
1026 _ao_usb_in_send(void)
1028 _tx_dbg0("in_send start");
1029 debug ("send %d\n", ao_usb_tx_count);
1030 while (ao_usb_in_pending)
1031 ao_sleep(&ao_usb_in_pending);
1032 ao_usb_in_pending = 1;
1033 if (ao_usb_tx_count != AO_USB_IN_SIZE)
1034 ao_usb_in_flushed = 1;
1035 ao_usb_bdt[AO_USB_IN_EPR].double_tx[ao_usb_in_tx_which].count = ao_usb_tx_count;
1036 ao_usb_tx_count = 0;
1038 /* Toggle our usage */
1039 ao_usb_in_tx_which = 1 - ao_usb_in_tx_which;
1041 /* Toggle the SW_BUF flag */
1042 _ao_usb_toggle_dtog(AO_USB_IN_EPR, 1, 0);
1044 /* Mark the outgoing buffer as valid */
1045 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
1047 _tx_dbg0("in_send end");
1050 /* Wait for a free IN buffer. Interrupts are blocked */
1052 _ao_usb_in_wait(void)
1055 /* Check if the current buffer is writable */
1056 if (ao_usb_tx_count < AO_USB_IN_SIZE)
1059 _tx_dbg0("in_wait top");
1060 /* Wait for an IN buffer to be ready */
1061 while (ao_usb_in_pending)
1062 ao_sleep(&ao_usb_in_pending);
1063 _tx_dbg0("in_wait bottom");
1070 if (!ao_usb_running)
1073 /* Anytime we've sent a character since
1074 * the last time we flushed, we'll need
1075 * to send a packet -- the only other time
1076 * we would send a packet is when that
1077 * packet was full, in which case we now
1078 * want to send an empty packet
1080 ao_arch_block_interrupts();
1081 while (!ao_usb_in_flushed) {
1082 _tx_dbg0("flush top");
1084 _tx_dbg0("flush end");
1086 ao_arch_release_interrupts();
1090 ao_usb_putchar(char c)
1092 if (!ao_usb_running)
1095 ao_arch_block_interrupts();
1098 ao_usb_in_flushed = 0;
1099 ao_usb_tx_count = ao_usb_tx_byte(ao_usb_in_tx_buffer[ao_usb_in_tx_which], ao_usb_tx_count, c);
1101 /* Send the packet when full */
1102 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
1103 _tx_dbg0("putchar full");
1105 _tx_dbg0("putchar flushed");
1107 ao_arch_release_interrupts();
1112 /* Queue the current IN buffer for transmission */
1114 _ao_usb_in2_send(void)
1116 _tx_dbg0("in2_send start");
1117 debug ("send2 %d\n", ao_usb_tx_count);
1118 while (ao_usb_in2_pending)
1119 ao_sleep(&ao_usb_in2_pending);
1120 ao_usb_in2_pending = 1;
1121 if (ao_usb_tx2_count != AO_USB_IN_SIZE)
1122 ao_usb_in2_flushed = 1;
1123 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_in2_tx_offset[ao_usb_in2_tx_which];
1124 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = ao_usb_tx2_count;
1125 ao_usb_tx2_count = 0;
1126 ao_usb_in2_tx_which = 1 - ao_usb_in2_tx_which;
1127 _ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
1128 _tx_dbg0("in2_send end");
1131 /* Wait for a free IN buffer. Interrupts are blocked */
1133 _ao_usb_in2_wait(void)
1136 /* Check if the current buffer is writable */
1137 if (ao_usb_tx2_count < AO_USB_IN_SIZE)
1140 _tx_dbg0("in2_wait top");
1141 /* Wait for an IN buffer to be ready */
1142 while (ao_usb_in2_pending)
1143 ao_sleep(&ao_usb_in2_pending);
1144 _tx_dbg0("in_wait bottom");
1151 if (!ao_usb_running)
1154 /* Anytime we've sent a character since
1155 * the last time we flushed, we'll need
1156 * to send a packet -- the only other time
1157 * we would send a packet is when that
1158 * packet was full, in which case we now
1159 * want to send an empty packet
1161 ao_arch_block_interrupts();
1162 while (!ao_usb_in2_flushed) {
1163 _tx_dbg0("flush2 top");
1165 _tx_dbg0("flush2 end");
1167 ao_arch_release_interrupts();
1171 ao_usb_putchar2(char c)
1173 if (!ao_usb_running)
1176 ao_arch_block_interrupts();
1179 ao_usb_in2_flushed = 0;
1180 ao_usb_tx2_count = ao_usb_tx_byte(ao_usb_in2_tx_buffer[ao_usb_in2_tx_which], ao_usb_tx2_count, c);
1182 /* Send the packet when full */
1183 if (ao_usb_tx2_count == AO_USB_IN_SIZE) {
1184 _tx_dbg0("putchar2 full");
1186 _tx_dbg0("putchar2 flushed");
1188 ao_arch_release_interrupts();
1194 _ao_usb_out_recv(void)
1196 _rx_dbg0("out_recv top");
1197 ao_usb_out_avail = 0;
1199 ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
1201 _rx_dbg1("out_recv count", ao_usb_rx_count);
1202 debug ("recv %d\n", ao_usb_rx_count);
1203 debug_data("Fill OUT len %d:", ao_usb_rx_count);
1204 ao_usb_copy_rx(ao_usb_rx_buffer, ao_usb_out_rx_buffer, ao_usb_rx_count);
1208 /* ACK the packet */
1209 _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
1213 _ao_usb_pollchar(void)
1217 if (!ao_usb_running)
1218 return AO_READ_AGAIN;
1221 if (ao_usb_rx_pos != ao_usb_rx_count)
1224 _rx_dbg0("poll check");
1225 /* Check to see if a packet has arrived */
1226 if (!ao_usb_out_avail) {
1227 _rx_dbg0("poll none");
1228 return AO_READ_AGAIN;
1233 /* Pull a character out of the fifo */
1234 c = ao_usb_rx_buffer[ao_usb_rx_pos++];
1239 ao_usb_getchar(void)
1243 ao_arch_block_interrupts();
1244 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
1245 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
1246 ao_arch_release_interrupts();
1257 buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
1258 ao_usb_sram_addr += AO_USB_IN_SIZE;
1263 ao_usb_write(uint16_t *buffer, uint16_t len)
1265 ao_arch_block_interrupts();
1267 /* Wait for everything to be ready at the same time */
1269 /* Make sure USB is connected */
1270 if (!ao_usb_running) {
1271 ao_sleep(&ao_usb_running);
1275 /* Flush any pending regular I/O */
1276 if (ao_usb_tx_count) {
1281 /* Wait for an idle IN buffer */
1282 if (ao_usb_in_pending) {
1283 ao_sleep(&ao_usb_in_pending);
1289 ao_usb_in_pending = 1;
1290 ao_usb_in_flushed = (len != AO_USB_IN_SIZE);
1291 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
1292 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = len;
1293 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
1294 ao_arch_release_interrupts();
1299 ao_usb_write2(uint16_t *buffer, uint16_t len)
1301 ao_arch_block_interrupts();
1303 /* Wait for everything to be ready at the same time */
1305 /* Make sure USB is connected */
1306 if (!ao_usb_running) {
1307 ao_sleep(&ao_usb_running);
1311 /* Flush any pending regular I/O */
1312 if (ao_usb_tx2_count) {
1317 /* Wait for an idle IN buffer */
1318 if (ao_usb_in2_pending) {
1319 ao_sleep(&ao_usb_in2_pending);
1325 ao_usb_in2_pending = 1;
1326 ao_usb_in2_flushed = (len != AO_USB_IN_SIZE);
1327 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
1328 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = len;
1329 _ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
1330 ao_arch_release_interrupts();
1336 ao_usb_disable(void)
1338 ao_arch_block_interrupts();
1339 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1342 /* Disable USB pull-up */
1343 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1345 /* Switch off the device */
1346 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
1348 /* Disable the interface */
1349 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
1350 ao_arch_release_interrupts();
1358 /* Select HSI48 as USB clock source */
1359 stm_rcc.cfgr3 &= ~(1 << STM_RCC_CFGR3_USBSW);
1361 /* Enable USB device */
1362 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
1364 /* Clear reset condition */
1365 stm_rcc.apb1rstr &= ~(1 << STM_RCC_APB1RSTR_USBRST);
1367 /* Disable USB pull-up */
1368 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1370 /* Do not touch the GPIOA configuration; USB takes priority
1371 * over GPIO on pins A11 and A12, but if you select alternate
1372 * input 10 (the documented correct selection), then USB is
1373 * pulled low and doesn't work at all
1376 ao_arch_block_interrupts();
1378 /* Route interrupts */
1379 stm_nvic_set_enable(STM_ISR_USB_POS);
1380 stm_nvic_set_priority(STM_ISR_USB_POS, 3);
1382 ao_usb_configuration = 0;
1384 /* Set up buffer descriptors */
1385 ao_usb_init_btable();
1387 /* Reset the USB controller */
1388 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1390 /* Clear the reset bit */
1393 /* Clear any spurious interrupts */
1398 debug ("ao_usb_enable\n");
1400 /* Enable interrupts */
1401 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1402 (0 << STM_USB_CNTR_PMAOVRM) |
1403 (0 << STM_USB_CNTR_ERRM) |
1404 (AO_POWER_MANAGEMENT << STM_USB_CNTR_WKUPM) |
1405 (AO_POWER_MANAGEMENT << STM_USB_CNTR_SUSPM) |
1406 (1 << STM_USB_CNTR_RESETM) |
1407 (0 << STM_USB_CNTR_SOFM) |
1408 (0 << STM_USB_CNTR_ESOFM) |
1409 (0 << STM_USB_CNTR_RESUME) |
1410 (0 << STM_USB_CNTR_FSUSP) |
1411 (0 << STM_USB_CNTR_LP_MODE) |
1412 (0 << STM_USB_CNTR_PDWN) |
1413 (0 << STM_USB_CNTR_FRES));
1415 ao_arch_release_interrupts();
1417 for (t = 0; t < 1000; t++)
1420 /* Enable USB pull-up */
1421 stm_usb.bcdr |= (1 << STM_USB_BCDR_DPPU);
1425 struct ao_task ao_usb_echo_task;
1433 c = ao_usb_getchar();
1444 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1445 control_count, out_count, in_count, int_count, reset_count);
1448 __code struct ao_cmds ao_usb_cmds[] = {
1449 { ao_usb_irq, "I\0Show USB interrupt counts" },
1457 /* Turn on syscfg */
1458 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
1460 /* Set PA11/PA12 remapping bit */
1461 stm_syscfg.cfgr1 |= (AO_PA11_PA12_RMP << STM_SYSCFG_CFGR1_PA11_PA12_RMP);
1463 #ifndef AO_USB_START_DISABLED
1467 #if AO_USB_DEVICE_ID_SERIAL
1468 ao_usb_serial_init();
1471 debug ("ao_usb_init\n");
1472 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1474 ao_usb_alloc_buffers();
1477 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1480 ao_cmd_register(&ao_usb_cmds[0]);
1484 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1489 #if TX_DBG || RX_DBG
1499 uint32_t in_pending;
1501 uint32_t in_flushed;
1511 #define NUM_USB_DBG 128
1513 static struct ao_usb_dbg dbg[128];
1516 static void _dbg(int line, char *msg, uint32_t value)
1519 dbg[dbg_i].line = line;
1520 dbg[dbg_i].msg = msg;
1521 dbg[dbg_i].value = value;
1522 asm("mrs %0,primask" : "=&r" (primask));
1523 dbg[dbg_i].primask = primask;
1525 dbg[dbg_i].in_count = in_count;
1526 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1527 dbg[dbg_i].in_pending = ao_usb_in_pending;
1528 dbg[dbg_i].tx_count = ao_usb_tx_count;
1529 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1532 dbg[dbg_i].rx_count = ao_usb_rx_count;
1533 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1534 dbg[dbg_i].out_avail = ao_usb_out_avail;
1535 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR];
1537 if (++dbg_i == NUM_USB_DBG)