add many more attributes

[hw/telescience] / telescience.sch

diff --git a/telescience.sch b/telescience.sch
index 39d2c912b757ad40d1e45e79d8c893addaf59d2d..5c3dec4f88d2c371e843d49fba2aa4fd47fd8554 100644 (file)
--- a/telescience.sch
+++ b/telescience.sch
@@ -603,7 +603,7 @@ C 61800 54100 1 90 0 capacitor.sym
 T 61100 54300 5 10 0 0 90 0 1
 device=CAPACITOR
 T 61400 54900 5 10 1 1 180 0 1
-refdes=C30
+refdes=C8
 T 60900 54300 5 10 0 0 90 0 1
 symversion=0.1
 T 61000 54200 5 10 1 1 0 0 1
@@ -622,7 +622,7 @@ C 63500 54100 1 90 0 capacitor.sym
 T 62800 54300 5 10 0 0 90 0 1
 device=CAPACITOR
 T 63800 54900 5 10 1 1 180 0 1
-refdes=C31
+refdes=C9
 T 62600 54300 5 10 0 0 90 0 1
 symversion=0.1
 T 63500 54200 5 10 1 1 0 0 1
@@ -1136,89 +1136,74 @@ C 43800 61200 1 0 0 capacitor.sym
 T 44000 61900 5 10 0 0 0 0 1
 device=CAPACITOR
 T 43900 61700 5 10 1 1 0 0 1
-refdes=C?
+refdes=C11
 T 44000 62100 5 10 0 0 0 0 1
 symversion=0.1
+T 43800 61200 5 10 1 1 0 0 1
+footprint=0402
+T 43800 61200 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 42100 58800 1 90 0 capacitor.sym
 {
 T 41400 59000 5 10 0 0 90 0 1
 device=CAPACITOR
 T 42300 59500 5 10 1 1 180 0 1
-refdes=C?
+refdes=C10
 T 41200 59000 5 10 0 0 90 0 1
 symversion=0.1
+T 42100 58800 5 10 1 1 0 0 1
+footprint=0402
+T 42100 58800 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 43800 60600 1 0 0 resistor.sym
 {
 T 44100 61000 5 10 0 0 0 0 1
 device=RESISTOR
 T 43900 60900 5 10 1 1 0 0 1
-refdes=R?
+refdes=R3
+T 43800 60600 5 10 1 1 0 0 1
+footprint=0402
+T 43800 60600 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 42400 59600 1 0 0 resistor.sym
 {
 T 42700 60000 5 10 0 0 0 0 1
 device=RESISTOR
 T 42500 59900 5 10 1 1 0 0 1
-refdes=R?
+refdes=R2
+T 42400 59600 5 10 1 1 0 0 1
+footprint=0402
+T 42400 59600 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 41400 59700 1 90 0 resistor.sym
 {
 T 41000 60000 5 10 0 0 90 0 1
 device=RESISTOR
 T 41700 60400 5 10 1 1 180 0 1
-refdes=R?
+refdes=R1
+T 41400 59700 5 10 1 1 0 0 1
+footprint=0402
+T 41400 59700 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 43500 59100 1 0 0 LMV344-1.sym
 {
-T 43700 61400 5 10 0 0 0 0 1
-device=QUAD_OPAMP
+T 43700 61400 5 10 1 1 0 0 1
+device=LMV344
 T 44300 59800 5 10 1 1 0 0 1
-refdes=U6A
+refdes=U6
 T 43700 61600 5 10 0 0 0 0 1
 symversion=0.2
 T 44300 59200 5 10 1 1 0 0 1
 device=LMV344
-}
-C 43500 55300 1 0 0 LMV344-2.sym
-{
-T 43700 57600 5 10 0 0 0 0 1
-device=QUAD_OPAMP
-T 43700 56200 5 10 1 1 0 0 1
-refdes=U6B
-T 43700 57200 5 10 0 0 0 0 1
+T 43500 59100 5 10 1 1 0 0 1
 footprint=TI-SO-14
-T 43700 57400 5 10 0 0 0 0 1
-symversion=0.2
-T 44300 55400 5 10 1 1 0 0 1
-device=LMV344
-}
-C 43500 51500 1 0 0 LMV344-3.sym
-{
-T 43700 53800 5 10 0 0 0 0 1
-device=QUAD_OPAMP
-T 43700 52400 5 10 1 1 0 0 1
-refdes=U6C
-T 43700 53400 5 10 0 0 0 0 1
-footprint=TI-SO-14
-T 43700 53600 5 10 0 0 0 0 1
-symversion=0.2
-T 44300 51600 5 10 1 1 0 0 1
-device=LMV344
-}
-C 43500 47600 1 0 0 LMV344-4.sym
-{
-T 43700 49900 5 10 0 0 0 0 1
-device=QUAD_OPAMP
-T 43700 48500 5 10 1 1 0 0 1
-refdes=U6D
-T 43700 49500 5 10 0 0 0 0 1
-footprint=TI-SO-14
-T 43700 49700 5 10 0 0 0 0 1
-symversion=0.2
-T 44300 47700 5 10 1 1 0 0 1
-device=LMV344
+T 43500 59100 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 43400 58500 1 0 0 gnd-1.sym
 C 43800 59900 1 0 0 3.3V-plus-1.sym
@@ -1248,39 +1233,59 @@ C 43800 57400 1 0 0 capacitor.sym
 T 44000 58100 5 10 0 0 0 0 1
 device=CAPACITOR
 T 43900 57900 5 10 1 1 0 0 1
-refdes=C?
+refdes=C13
 T 44000 58300 5 10 0 0 0 0 1
 symversion=0.1
+T 43800 57400 5 10 1 1 0 0 1
+footprint=0402
+T 43800 57400 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 42100 55000 1 90 0 capacitor.sym
 {
 T 41400 55200 5 10 0 0 90 0 1
 device=CAPACITOR
 T 42300 55700 5 10 1 1 180 0 1
-refdes=C?
+refdes=C12
 T 41200 55200 5 10 0 0 90 0 1
 symversion=0.1
+T 42100 55000 5 10 1 1 0 0 1
+footprint=0402
+T 42100 55000 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 43800 56800 1 0 0 resistor.sym
 {
 T 44100 57200 5 10 0 0 0 0 1
 device=RESISTOR
 T 43900 57100 5 10 1 1 0 0 1
-refdes=R?
+refdes=R6
+T 43800 56800 5 10 1 1 0 0 1
+footprint=0402
+T 43800 56800 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 42400 55800 1 0 0 resistor.sym
 {
 T 42700 56200 5 10 0 0 0 0 1
 device=RESISTOR
 T 42500 56100 5 10 1 1 0 0 1
-refdes=R?
+refdes=R5
+T 42400 55800 5 10 1 1 0 0 1
+footprint=0402
+T 42400 55800 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 41400 55900 1 90 0 resistor.sym
 {
 T 41000 56200 5 10 0 0 90 0 1
 device=RESISTOR
 T 41700 56600 5 10 1 1 180 0 1
-refdes=R?
+refdes=R4
+T 41400 55900 5 10 1 1 0 0 1
+footprint=0402
+T 41400 55900 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 43400 54700 1 0 0 gnd-1.sym
 N 43500 55000 43500 55500 4
@@ -1308,39 +1313,59 @@ C 43800 53600 1 0 0 capacitor.sym
 T 44000 54300 5 10 0 0 0 0 1
 device=CAPACITOR
 T 43900 54100 5 10 1 1 0 0 1
-refdes=C?
+refdes=C15
 T 44000 54500 5 10 0 0 0 0 1
 symversion=0.1
+T 43800 53600 5 10 1 1 0 0 1
+footprint=0402
+T 43800 53600 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 42100 51200 1 90 0 capacitor.sym
 {
 T 41400 51400 5 10 0 0 90 0 1
 device=CAPACITOR
 T 42300 51900 5 10 1 1 180 0 1
-refdes=C?
+refdes=C14
 T 41200 51400 5 10 0 0 90 0 1
 symversion=0.1
+T 42100 51200 5 10 1 1 0 0 1
+footprint=0402
+T 42100 51200 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 43800 53000 1 0 0 resistor.sym
 {
 T 44100 53400 5 10 0 0 0 0 1
 device=RESISTOR
 T 43900 53300 5 10 1 1 0 0 1
-refdes=R?
+refdes=R9
+T 43800 53000 5 10 1 1 0 0 1
+footprint=0402
+T 43800 53000 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 42400 52000 1 0 0 resistor.sym
 {
 T 42700 52400 5 10 0 0 0 0 1
 device=RESISTOR
 T 42500 52300 5 10 1 1 0 0 1
-refdes=R?
+refdes=R8
+T 42400 52000 5 10 1 1 0 0 1
+footprint=0402
+T 42400 52000 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 41400 52100 1 90 0 resistor.sym
 {
 T 41000 52400 5 10 0 0 90 0 1
 device=RESISTOR
 T 41700 52800 5 10 1 1 180 0 1
-refdes=R?
+refdes=R7
+T 41400 52100 5 10 1 1 0 0 1
+footprint=0402
+T 41400 52100 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 43400 50900 1 0 0 gnd-1.sym
 N 43500 51200 43500 51700 4
@@ -1368,39 +1393,59 @@ C 43800 49700 1 0 0 capacitor.sym
 T 44000 50400 5 10 0 0 0 0 1
 device=CAPACITOR
 T 43900 50200 5 10 1 1 0 0 1
-refdes=C?
+refdes=C17
 T 44000 50600 5 10 0 0 0 0 1
 symversion=0.1
+T 43800 49700 5 10 1 1 0 0 1
+footprint=0402
+T 43800 49700 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 42100 47300 1 90 0 capacitor.sym
 {
 T 41400 47500 5 10 0 0 90 0 1
 device=CAPACITOR
 T 42300 48000 5 10 1 1 180 0 1
-refdes=C?
+refdes=C16
 T 41200 47500 5 10 0 0 90 0 1
 symversion=0.1
+T 42100 47300 5 10 1 1 0 0 1
+footprint=0402
+T 42100 47300 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 43800 49100 1 0 0 resistor.sym
 {
 T 44100 49500 5 10 0 0 0 0 1
 device=RESISTOR
 T 43900 49400 5 10 1 1 0 0 1
-refdes=R?
+refdes=R12
+T 43800 49100 5 10 1 1 0 0 1
+footprint=0402
+T 43800 49100 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 42400 48100 1 0 0 resistor.sym
 {
 T 42700 48500 5 10 0 0 0 0 1
 device=RESISTOR
 T 42500 48400 5 10 1 1 0 0 1
-refdes=R?
+refdes=R11
+T 42400 48100 5 10 1 1 0 0 1
+footprint=0402
+T 42400 48100 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 41400 48200 1 90 0 resistor.sym
 {
 T 41000 48500 5 10 0 0 90 0 1
 device=RESISTOR
-T 41700 48900 5 10 1 1 180 0 1
-refdes=R?
+T 41800 48900 5 10 1 1 180 0 1
+refdes=R10
+T 41400 48200 5 10 1 1 0 0 1
+footprint=0402
+T 41400 48200 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 43400 47000 1 0 0 gnd-1.sym
 N 43500 47300 43500 47800 4
@@ -1428,89 +1473,59 @@ C 50400 61200 1 0 0 capacitor.sym
 T 50600 61900 5 10 0 0 0 0 1
 device=CAPACITOR
 T 50500 61700 5 10 1 1 0 0 1
-refdes=C?
+refdes=C19
 T 50600 62100 5 10 0 0 0 0 1
 symversion=0.1
+T 50400 61200 5 10 1 1 0 0 1
+footprint=0402
+T 50400 61200 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 48700 58800 1 90 0 capacitor.sym
 {
 T 48000 59000 5 10 0 0 90 0 1
 device=CAPACITOR
 T 48900 59500 5 10 1 1 180 0 1
-refdes=C?
+refdes=C18
 T 47800 59000 5 10 0 0 90 0 1
 symversion=0.1
+T 48700 58800 5 10 1 1 0 0 1
+footprint=0402
+T 48700 58800 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 50400 60600 1 0 0 resistor.sym
 {
 T 50700 61000 5 10 0 0 0 0 1
 device=RESISTOR
 T 50500 60900 5 10 1 1 0 0 1
-refdes=R?
+refdes=R15
+T 50400 60600 5 10 1 1 0 0 1
+footprint=0402
+T 50400 60600 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 49000 59600 1 0 0 resistor.sym
 {
 T 49300 60000 5 10 0 0 0 0 1
 device=RESISTOR
 T 49100 59900 5 10 1 1 0 0 1
-refdes=R?
+refdes=R14
+T 49000 59600 5 10 1 1 0 0 1
+footprint=0402
+T 49000 59600 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 48000 59700 1 90 0 resistor.sym
 {
 T 47600 60000 5 10 0 0 90 0 1
 device=RESISTOR
-T 48300 60400 5 10 1 1 180 0 1
-refdes=R?
-}
-C 50100 59100 1 0 0 LMV344-1.sym
-{
-T 50300 61400 5 10 0 0 0 0 1
-device=QUAD_OPAMP
-T 50900 59800 5 10 1 1 0 0 1
-refdes=U7A
-T 50300 61600 5 10 0 0 0 0 1
-symversion=0.2
-T 50900 59200 5 10 1 1 0 0 1
-device=LMV344
-}
-C 50100 55300 1 0 0 LMV344-2.sym
-{
-T 50300 57600 5 10 0 0 0 0 1
-device=QUAD_OPAMP
-T 50300 56200 5 10 1 1 0 0 1
-refdes=U7B
-T 50300 57200 5 10 0 0 0 0 1
-footprint=TI-SO-14
-T 50300 57400 5 10 0 0 0 0 1
-symversion=0.2
-T 50900 55400 5 10 1 1 0 0 1
-device=LMV344
-}
-C 50100 51500 1 0 0 LMV344-3.sym
-{
-T 50300 53800 5 10 0 0 0 0 1
-device=QUAD_OPAMP
-T 50300 52400 5 10 1 1 0 0 1
-refdes=U7C
-T 50300 53400 5 10 0 0 0 0 1
-footprint=TI-SO-14
-T 50300 53600 5 10 0 0 0 0 1
-symversion=0.2
-T 50900 51600 5 10 1 1 0 0 1
-device=LMV344
-}
-C 50100 47600 1 0 0 LMV344-4.sym
-{
-T 50300 49900 5 10 0 0 0 0 1
-device=QUAD_OPAMP
-T 50300 48500 5 10 1 1 0 0 1
-refdes=U7D
-T 50300 49500 5 10 0 0 0 0 1
-footprint=TI-SO-14
-T 50300 49700 5 10 0 0 0 0 1
-symversion=0.2
-T 50900 47700 5 10 1 1 0 0 1
-device=LMV344
+T 48400 60400 5 10 1 1 180 0 1
+refdes=R13
+T 48000 59700 5 10 1 1 0 0 1
+footprint=0402
+T 48000 59700 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 50000 58500 1 0 0 gnd-1.sym
 C 50400 59900 1 0 0 3.3V-plus-1.sym
@@ -1540,39 +1555,59 @@ C 50400 57400 1 0 0 capacitor.sym
 T 50600 58100 5 10 0 0 0 0 1
 device=CAPACITOR
 T 50500 57900 5 10 1 1 0 0 1
-refdes=C?
+refdes=C21
 T 50600 58300 5 10 0 0 0 0 1
 symversion=0.1
+T 50400 57400 5 10 1 1 0 0 1
+footprint=0402
+T 50400 57400 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 48700 55000 1 90 0 capacitor.sym
 {
 T 48000 55200 5 10 0 0 90 0 1
 device=CAPACITOR
 T 48900 55700 5 10 1 1 180 0 1
-refdes=C?
+refdes=C20
 T 47800 55200 5 10 0 0 90 0 1
 symversion=0.1
+T 48700 55000 5 10 1 1 0 0 1
+footprint=0402
+T 48700 55000 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 50400 56800 1 0 0 resistor.sym
 {
 T 50700 57200 5 10 0 0 0 0 1
 device=RESISTOR
 T 50500 57100 5 10 1 1 0 0 1
-refdes=R?
+refdes=R18
+T 50400 56800 5 10 1 1 0 0 1
+footprint=0402
+T 50400 56800 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 49000 55800 1 0 0 resistor.sym
 {
 T 49300 56200 5 10 0 0 0 0 1
 device=RESISTOR
 T 49100 56100 5 10 1 1 0 0 1
-refdes=R?
+refdes=R17
+T 49000 55800 5 10 1 1 0 0 1
+footprint=0402
+T 49000 55800 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 48000 55900 1 90 0 resistor.sym
 {
 T 47600 56200 5 10 0 0 90 0 1
 device=RESISTOR
-T 48300 56600 5 10 1 1 180 0 1
-refdes=R?
+T 48400 56600 5 10 1 1 180 0 1
+refdes=R16
+T 48000 55900 5 10 1 1 0 0 1
+footprint=0402
+T 48000 55900 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 50000 54700 1 0 0 gnd-1.sym
 N 50100 55000 50100 55500 4
@@ -1600,39 +1635,59 @@ C 50400 53600 1 0 0 capacitor.sym
 T 50600 54300 5 10 0 0 0 0 1
 device=CAPACITOR
 T 50500 54100 5 10 1 1 0 0 1
-refdes=C?
+refdes=C23
 T 50600 54500 5 10 0 0 0 0 1
 symversion=0.1
+T 50400 53600 5 10 1 1 0 0 1
+footprint=0402
+T 50400 53600 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 48700 51200 1 90 0 capacitor.sym
 {
 T 48000 51400 5 10 0 0 90 0 1
 device=CAPACITOR
 T 48900 51900 5 10 1 1 180 0 1
-refdes=C?
+refdes=C22
 T 47800 51400 5 10 0 0 90 0 1
 symversion=0.1
+T 48700 51200 5 10 1 1 0 0 1
+footprint=0402
+T 48700 51200 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 50400 53000 1 0 0 resistor.sym
 {
 T 50700 53400 5 10 0 0 0 0 1
 device=RESISTOR
 T 50500 53300 5 10 1 1 0 0 1
-refdes=R?
+refdes=R21
+T 50400 53000 5 10 1 1 0 0 1
+footprint=0402
+T 50400 53000 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 49000 52000 1 0 0 resistor.sym
 {
 T 49300 52400 5 10 0 0 0 0 1
 device=RESISTOR
 T 49100 52300 5 10 1 1 0 0 1
-refdes=R?
+refdes=R20
+T 49000 52000 5 10 1 1 0 0 1
+footprint=0402
+T 49000 52000 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 48000 52100 1 90 0 resistor.sym
 {
 T 47600 52400 5 10 0 0 90 0 1
 device=RESISTOR
-T 48300 52800 5 10 1 1 180 0 1
-refdes=R?
+T 48400 52800 5 10 1 1 180 0 1
+refdes=R19
+T 48000 52100 5 10 1 1 0 0 1
+footprint=0402
+T 48000 52100 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 50000 50900 1 0 0 gnd-1.sym
 N 50100 51200 50100 51700 4
@@ -1660,39 +1715,59 @@ C 50400 49700 1 0 0 capacitor.sym
 T 50600 50400 5 10 0 0 0 0 1
 device=CAPACITOR
 T 50500 50200 5 10 1 1 0 0 1
-refdes=C?
+refdes=C25
 T 50600 50600 5 10 0 0 0 0 1
 symversion=0.1
+T 50400 49700 5 10 1 1 0 0 1
+footprint=0402
+T 50400 49700 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 48700 47300 1 90 0 capacitor.sym
 {
 T 48000 47500 5 10 0 0 90 0 1
 device=CAPACITOR
 T 48900 48000 5 10 1 1 180 0 1
-refdes=C?
+refdes=C24
 T 47800 47500 5 10 0 0 90 0 1
 symversion=0.1
+T 48700 47300 5 10 1 1 0 0 1
+footprint=0402
+T 48700 47300 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 50400 49100 1 0 0 resistor.sym
 {
 T 50700 49500 5 10 0 0 0 0 1
 device=RESISTOR
 T 50500 49400 5 10 1 1 0 0 1
-refdes=R?
+refdes=R24
+T 50400 49100 5 10 1 1 0 0 1
+footprint=0402
+T 50400 49100 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 49000 48100 1 0 0 resistor.sym
 {
 T 49300 48500 5 10 0 0 0 0 1
 device=RESISTOR
 T 49100 48400 5 10 1 1 0 0 1
-refdes=R?
+refdes=R23
+T 49000 48100 5 10 1 1 0 0 1
+footprint=0402
+T 49000 48100 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 48000 48200 1 90 0 resistor.sym
 {
 T 47600 48500 5 10 0 0 90 0 1
 device=RESISTOR
-T 48300 48900 5 10 1 1 180 0 1
-refdes=R?
+T 48400 48900 5 10 1 1 180 0 1
+refdes=R22
+T 48000 48200 5 10 1 1 0 0 1
+footprint=0402
+T 48000 48200 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 50000 47000 1 0 0 gnd-1.sym
 N 50100 47300 50100 47800 4
@@ -1720,89 +1795,59 @@ C 57000 61200 1 0 0 capacitor.sym
 T 57200 61900 5 10 0 0 0 0 1
 device=CAPACITOR
 T 57100 61700 5 10 1 1 0 0 1
-refdes=C?
+refdes=C27
 T 57200 62100 5 10 0 0 0 0 1
 symversion=0.1
+T 57000 61200 5 10 1 1 0 0 1
+footprint=0402
+T 57000 61200 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 55300 58800 1 90 0 capacitor.sym
 {
 T 54600 59000 5 10 0 0 90 0 1
 device=CAPACITOR
 T 55500 59500 5 10 1 1 180 0 1
-refdes=C?
+refdes=C26
 T 54400 59000 5 10 0 0 90 0 1
 symversion=0.1
+T 55300 58800 5 10 1 1 0 0 1
+footprint=0402
+T 55300 58800 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 57000 60600 1 0 0 resistor.sym
 {
 T 57300 61000 5 10 0 0 0 0 1
 device=RESISTOR
 T 57100 60900 5 10 1 1 0 0 1
-refdes=R?
+refdes=R27
+T 57000 60600 5 10 1 1 0 0 1
+footprint=0402
+T 57000 60600 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 55600 59600 1 0 0 resistor.sym
 {
 T 55900 60000 5 10 0 0 0 0 1
 device=RESISTOR
 T 55700 59900 5 10 1 1 0 0 1
-refdes=R?
+refdes=R26
+T 55600 59600 5 10 1 1 0 0 1
+footprint=0402
+T 55600 59600 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 54600 59700 1 90 0 resistor.sym
 {
 T 54200 60000 5 10 0 0 90 0 1
 device=RESISTOR
-T 54900 60400 5 10 1 1 180 0 1
-refdes=R?
-}
-C 56700 59100 1 0 0 LMV344-1.sym
-{
-T 56900 61400 5 10 0 0 0 0 1
-device=QUAD_OPAMP
-T 57500 59800 5 10 1 1 0 0 1
-refdes=U8A
-T 56900 61600 5 10 0 0 0 0 1
-symversion=0.2
-T 57500 59200 5 10 1 1 0 0 1
-device=LMV344
-}
-C 56700 55300 1 0 0 LMV344-2.sym
-{
-T 56900 57600 5 10 0 0 0 0 1
-device=QUAD_OPAMP
-T 56900 56200 5 10 1 1 0 0 1
-refdes=U8B
-T 56900 57200 5 10 0 0 0 0 1
-footprint=TI-SO-14
-T 56900 57400 5 10 0 0 0 0 1
-symversion=0.2
-T 57500 55400 5 10 1 1 0 0 1
-device=LMV344
-}
-C 56700 51500 1 0 0 LMV344-3.sym
-{
-T 56900 53800 5 10 0 0 0 0 1
-device=QUAD_OPAMP
-T 56900 52400 5 10 1 1 0 0 1
-refdes=U8C
-T 56900 53400 5 10 0 0 0 0 1
-footprint=TI-SO-14
-T 56900 53600 5 10 0 0 0 0 1
-symversion=0.2
-T 57500 51600 5 10 1 1 0 0 1
-device=LMV344
-}
-C 56700 47600 1 0 0 LMV344-4.sym
-{
-T 56900 49900 5 10 0 0 0 0 1
-device=QUAD_OPAMP
-T 56900 48500 5 10 1 1 0 0 1
-refdes=U8D
-T 56900 49500 5 10 0 0 0 0 1
-footprint=TI-SO-14
-T 56900 49700 5 10 0 0 0 0 1
-symversion=0.2
-T 57500 47700 5 10 1 1 0 0 1
-device=LMV344
+T 55000 60400 5 10 1 1 180 0 1
+refdes=R25
+T 54600 59700 5 10 1 1 0 0 1
+footprint=0402
+T 54600 59700 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 56600 58500 1 0 0 gnd-1.sym
 C 57000 59900 1 0 0 3.3V-plus-1.sym
@@ -1832,39 +1877,59 @@ C 57000 57400 1 0 0 capacitor.sym
 T 57200 58100 5 10 0 0 0 0 1
 device=CAPACITOR
 T 57100 57900 5 10 1 1 0 0 1
-refdes=C?
+refdes=C29
 T 57200 58300 5 10 0 0 0 0 1
 symversion=0.1
+T 57000 57400 5 10 1 1 0 0 1
+footprint=0402
+T 57000 57400 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 55300 55000 1 90 0 capacitor.sym
 {
 T 54600 55200 5 10 0 0 90 0 1
 device=CAPACITOR
 T 55500 55700 5 10 1 1 180 0 1
-refdes=C?
+refdes=C28
 T 54400 55200 5 10 0 0 90 0 1
 symversion=0.1
+T 55300 55000 5 10 1 1 0 0 1
+footprint=0402
+T 55300 55000 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 57000 56800 1 0 0 resistor.sym
 {
 T 57300 57200 5 10 0 0 0 0 1
 device=RESISTOR
 T 57100 57100 5 10 1 1 0 0 1
-refdes=R?
+refdes=R30
+T 57000 56800 5 10 1 1 0 0 1
+footprint=0402
+T 57000 56800 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 55600 55800 1 0 0 resistor.sym
 {
 T 55900 56200 5 10 0 0 0 0 1
 device=RESISTOR
 T 55700 56100 5 10 1 1 0 0 1
-refdes=R?
+refdes=R29
+T 55600 55800 5 10 1 1 0 0 1
+footprint=0402
+T 55600 55800 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 54600 55900 1 90 0 resistor.sym
 {
 T 54200 56200 5 10 0 0 90 0 1
 device=RESISTOR
-T 54900 56600 5 10 1 1 180 0 1
-refdes=R?
+T 55000 56600 5 10 1 1 180 0 1
+refdes=R28
+T 54600 55900 5 10 1 1 0 0 1
+footprint=0402
+T 54600 55900 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 56600 54700 1 0 0 gnd-1.sym
 N 56700 55000 56700 55500 4
@@ -1892,39 +1957,59 @@ C 57000 53600 1 0 0 capacitor.sym
 T 57200 54300 5 10 0 0 0 0 1
 device=CAPACITOR
 T 57100 54100 5 10 1 1 0 0 1
-refdes=C?
+refdes=C31
 T 57200 54500 5 10 0 0 0 0 1
 symversion=0.1
+T 57000 53600 5 10 1 1 0 0 1
+footprint=0402
+T 57000 53600 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 55300 51200 1 90 0 capacitor.sym
 {
 T 54600 51400 5 10 0 0 90 0 1
 device=CAPACITOR
 T 55500 51900 5 10 1 1 180 0 1
-refdes=C?
+refdes=C30
 T 54400 51400 5 10 0 0 90 0 1
 symversion=0.1
+T 55300 51200 5 10 1 1 0 0 1
+footprint=0402
+T 55300 51200 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 57000 53000 1 0 0 resistor.sym
 {
 T 57300 53400 5 10 0 0 0 0 1
 device=RESISTOR
 T 57100 53300 5 10 1 1 0 0 1
-refdes=R?
+refdes=R33
+T 57000 53000 5 10 1 1 0 0 1
+footprint=0402
+T 57000 53000 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 55600 52000 1 0 0 resistor.sym
 {
 T 55900 52400 5 10 0 0 0 0 1
 device=RESISTOR
 T 55700 52300 5 10 1 1 0 0 1
-refdes=R?
+refdes=R32
+T 55600 52000 5 10 1 1 0 0 1
+footprint=0402
+T 55600 52000 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 54600 52100 1 90 0 resistor.sym
 {
 T 54200 52400 5 10 0 0 90 0 1
 device=RESISTOR
-T 54900 52800 5 10 1 1 180 0 1
-refdes=R?
+T 55000 52800 5 10 1 1 180 0 1
+refdes=R31
+T 54600 52100 5 10 1 1 0 0 1
+footprint=0402
+T 54600 52100 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 56600 50900 1 0 0 gnd-1.sym
 N 56700 51200 56700 51700 4
@@ -1952,39 +2037,59 @@ C 57000 49700 1 0 0 capacitor.sym
 T 57200 50400 5 10 0 0 0 0 1
 device=CAPACITOR
 T 57100 50200 5 10 1 1 0 0 1
-refdes=C?
+refdes=C33
 T 57200 50600 5 10 0 0 0 0 1
 symversion=0.1
+T 57000 49700 5 10 1 1 0 0 1
+footprint=0402
+T 57000 49700 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 55300 47300 1 90 0 capacitor.sym
 {
 T 54600 47500 5 10 0 0 90 0 1
 device=CAPACITOR
 T 55500 48000 5 10 1 1 180 0 1
-refdes=C?
+refdes=C32
 T 54400 47500 5 10 0 0 90 0 1
 symversion=0.1
+T 55300 47300 5 10 1 1 0 0 1
+footprint=0402
+T 55300 47300 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 57000 49100 1 0 0 resistor.sym
 {
 T 57300 49500 5 10 0 0 0 0 1
 device=RESISTOR
 T 57100 49400 5 10 1 1 0 0 1
-refdes=R?
+refdes=R36
+T 57000 49100 5 10 1 1 0 0 1
+footprint=0402
+T 57000 49100 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 55600 48100 1 0 0 resistor.sym
 {
 T 55900 48500 5 10 0 0 0 0 1
 device=RESISTOR
 T 55700 48400 5 10 1 1 0 0 1
-refdes=R?
+refdes=R35
+T 55600 48100 5 10 1 1 0 0 1
+footprint=0402
+T 55600 48100 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 54600 48200 1 90 0 resistor.sym
 {
 T 54200 48500 5 10 0 0 90 0 1
 device=RESISTOR
-T 54900 48900 5 10 1 1 180 0 1
-refdes=R?
+T 55000 48900 5 10 1 1 180 0 1
+refdes=R34
+T 54600 48200 5 10 1 1 0 0 1
+footprint=0402
+T 54600 48200 5 10 1 1 0 0 1
+loadstatus=smt
 }
 C 56600 47000 1 0 0 gnd-1.sym
 N 56700 47300 56700 47800 4
@@ -2011,6 +2116,8 @@ C 46000 45800 1 90 0 conn-8.sym
 {
 T 42945 46405 5 10 1 1 0 8 1
 refdes=J10
+T 46000 45800 5 10 1 1 0 0 1
+footprint=282834-8
 }
 C 48500 45400 1 0 0 gnd-1.sym
 N 43100 45700 54200 45700 4
@@ -2020,31 +2127,43 @@ C 41200 43300 1 0 1 conn-3.sym
 {
 T 40900 44600 5 10 1 1 0 6 1
 refdes=J12
+T 41200 43300 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 41200 41700 1 0 1 conn-3.sym
 {
 T 40900 43000 5 10 1 1 0 6 1
 refdes=J14
+T 41200 41700 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 41200 40100 1 0 1 conn-3.sym
 {
 T 40900 41400 5 10 1 1 0 6 1
 refdes=J16
+T 41200 40100 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 43500 43300 1 0 0 conn-3.sym
 {
 T 43800 44600 5 10 1 1 0 0 1
 refdes=J13
+T 43500 43300 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 43500 41700 1 0 0 conn-3.sym
 {
 T 43800 43000 5 10 1 1 0 0 1
 refdes=J15
+T 43500 41700 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 43500 40100 1 0 0 conn-3.sym
 {
 T 43800 41400 5 10 1 1 0 0 1
 refdes=J17
+T 43500 40100 5 10 1 1 0 0 1
+footprint=530470310
 }
 N 43500 45800 43500 45400 4
 N 43500 45400 41700 45400 4
@@ -2110,31 +2229,43 @@ C 45300 43300 1 0 1 conn-3.sym
 {
 T 45000 44600 5 10 1 1 0 6 1
 refdes=J18
+T 45300 43300 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 45300 41700 1 0 1 conn-3.sym
 {
 T 45000 43000 5 10 1 1 0 6 1
 refdes=J20
+T 45300 41700 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 45300 40100 1 0 1 conn-3.sym
 {
 T 45000 41400 5 10 1 1 0 6 1
 refdes=J22
+T 45300 40100 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 47600 43300 1 0 0 conn-3.sym
 {
 T 47900 44600 5 10 1 1 0 0 1
 refdes=J19
+T 47600 43300 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 47600 41700 1 0 0 conn-3.sym
 {
 T 47900 43000 5 10 1 1 0 0 1
 refdes=J21
+T 47600 41700 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 47600 40100 1 0 0 conn-3.sym
 {
 T 47900 41400 5 10 1 1 0 0 1
 refdes=J23
+T 47600 40100 5 10 1 1 0 0 1
+footprint=530470310
 }
 N 45800 43900 45300 43900 4
 N 45300 44300 47600 44300 4
@@ -2200,6 +2331,8 @@ C 54300 45800 1 90 0 conn-8.sym
 {
 T 51245 46405 5 10 1 1 0 8 1
 refdes=J11
+T 54300 45800 5 10 1 1 0 0 1
+footprint=282834-8
 }
 N 51400 45700 51400 45800 4
 N 54200 45700 54200 45800 4
@@ -2207,31 +2340,43 @@ C 49500 43300 1 0 1 conn-3.sym
 {
 T 49200 44600 5 10 1 1 0 6 1
 refdes=J24
+T 49500 43300 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 49500 41700 1 0 1 conn-3.sym
 {
 T 49200 43000 5 10 1 1 0 6 1
 refdes=J26
+T 49500 41700 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 49500 40100 1 0 1 conn-3.sym
 {
 T 49200 41400 5 10 1 1 0 6 1
 refdes=J28
+T 49500 40100 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 51800 43300 1 0 0 conn-3.sym
 {
 T 52100 44600 5 10 1 1 0 0 1
 refdes=J25
+T 51800 43300 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 51800 41700 1 0 0 conn-3.sym
 {
 T 52100 43000 5 10 1 1 0 0 1
 refdes=J27
+T 51800 41700 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 51800 40100 1 0 0 conn-3.sym
 {
 T 52100 41400 5 10 1 1 0 0 1
 refdes=J29
+T 51800 40100 5 10 1 1 0 0 1
+footprint=530470310
 }
 N 51800 45800 51800 45400 4
 N 51800 45400 50000 45400 4
@@ -2297,31 +2442,43 @@ C 53600 43300 1 0 1 conn-3.sym
 {
 T 53300 44600 5 10 1 1 0 6 1
 refdes=J30
+T 53600 43300 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 53600 41700 1 0 1 conn-3.sym
 {
 T 53300 43000 5 10 1 1 0 6 1
 refdes=J32
+T 53600 41700 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 53600 40100 1 0 1 conn-3.sym
 {
 T 53300 41400 5 10 1 1 0 6 1
 refdes=J34
+T 53600 40100 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 55900 43300 1 0 0 conn-3.sym
 {
 T 56200 44600 5 10 1 1 0 0 1
 refdes=J31
+T 55900 43300 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 55900 41700 1 0 0 conn-3.sym
 {
 T 56200 43000 5 10 1 1 0 0 1
 refdes=J33
+T 55900 41700 5 10 1 1 0 0 1
+footprint=530470310
 }
 C 55900 40100 1 0 0 conn-3.sym
 {
 T 56200 41400 5 10 1 1 0 0 1
 refdes=J35
+T 55900 40100 5 10 1 1 0 0 1
+footprint=530470310
 }
 N 54100 43900 53600 43900 4
 N 53600 44300 55900 44300 4
@@ -2383,3 +2540,158 @@ N 54500 45100 54500 42300 4
 N 53800 45800 53800 45400 4
 N 53800 45400 54900 45400 4
 N 54900 45400 54900 40700 4
+C 43500 55300 1 0 0 LMV344-2.sym
+{
+T 43700 57800 5 10 1 1 0 0 1
+device=LMV344
+T 43700 56200 5 10 1 1 0 0 1
+refdes=U6
+T 43700 57600 5 10 0 0 0 0 1
+footprint=TI-SO-14
+T 44300 55400 5 10 1 1 0 0 1
+device=LMV344
+T 43500 55300 5 10 1 1 0 0 1
+loadstatus=smt
+}
+C 43500 51500 1 0 0 LMV344-2.sym
+{
+T 43700 54000 5 10 1 1 0 0 1
+device=LMV344
+T 43700 52400 5 10 1 1 0 0 1
+refdes=U6
+T 43700 53800 5 10 0 0 0 0 1
+footprint=TI-SO-14
+T 44300 51600 5 10 1 1 0 0 1
+device=LMV344
+T 43500 51500 5 10 0 0 0 0 1
+slot=3
+T 43500 51500 5 10 1 1 0 0 1
+loadstatus=smt
+}
+C 43500 47600 1 0 0 LMV344-2.sym
+{
+T 43700 50100 5 10 1 1 0 0 1
+device=LMV344
+T 43700 48500 5 10 1 1 0 0 1
+refdes=U6
+T 43700 49900 5 10 0 0 0 0 1
+footprint=TI-SO-14
+T 44300 47700 5 10 1 1 0 0 1
+device=LMV344
+T 43500 47600 5 10 0 0 0 0 1
+slot=4
+T 43500 47600 5 10 1 1 0 0 1
+loadstatus=smt
+}
+C 50100 59100 1 0 0 LMV344-1.sym
+{
+T 50300 61600 5 10 1 1 0 0 1
+device=LMV344
+T 50300 60000 5 10 1 1 0 0 1
+refdes=U7
+T 50300 61400 5 10 0 0 0 0 1
+footprint=TI-SO-14
+T 50900 59200 5 10 1 1 0 0 1
+device=LMV344
+T 50100 59100 5 10 1 1 0 0 1
+loadstatus=smt
+}
+C 56700 59100 1 0 0 LMV344-1.sym
+{
+T 56900 61600 5 10 1 1 0 0 1
+device=LMV344
+T 56900 60000 5 10 1 1 0 0 1
+refdes=U8
+T 56900 61400 5 10 0 0 0 0 1
+footprint=TI-SO-14
+T 57500 59200 5 10 1 1 0 0 1
+device=LMV344
+T 56700 59100 5 10 1 1 0 0 1
+loadstatus=smt
+}
+C 50100 55300 1 0 0 LMV344-2.sym
+{
+T 50300 57800 5 10 1 1 0 0 1
+device=LMV344
+T 50300 56200 5 10 1 1 0 0 1
+refdes=U7
+T 50300 57600 5 10 0 0 0 0 1
+footprint=TI-SO-14
+T 50900 55400 5 10 1 1 0 0 1
+device=LMV344
+T 50100 55300 5 10 1 1 0 0 1
+loadstatus=smt
+}
+C 56700 55300 1 0 0 LMV344-2.sym
+{
+T 56900 57800 5 10 1 1 0 0 1
+device=LMV344
+T 56900 56200 5 10 1 1 0 0 1
+refdes=U8
+T 56900 57600 5 10 0 0 0 0 1
+footprint=TI-SO-14
+T 57500 55400 5 10 1 1 0 0 1
+device=LMV344
+T 56700 55300 5 10 1 1 0 0 1
+loadstatus=smt
+}
+C 50100 51500 1 0 0 LMV344-2.sym
+{
+T 50300 54000 5 10 1 1 0 0 1
+device=LMV344
+T 50300 52400 5 10 1 1 0 0 1
+refdes=U7
+T 50300 53800 5 10 0 0 0 0 1
+footprint=TI-SO-14
+T 50900 51600 5 10 1 1 0 0 1
+device=LMV344
+T 50100 51500 5 10 0 1 0 0 1
+slot=3
+T 50100 51500 5 10 1 1 0 0 1
+loadstatus=smt
+}
+C 56700 51500 1 0 0 LMV344-2.sym
+{
+T 56900 54000 5 10 1 1 0 0 1
+device=LMV344
+T 56900 52400 5 10 1 1 0 0 1
+refdes=U8
+T 56900 53800 5 10 0 0 0 0 1
+footprint=TI-SO-14
+T 57500 51600 5 10 1 1 0 0 1
+device=LMV344
+T 56700 51500 5 10 0 0 0 0 1
+slot=3
+T 56700 51500 5 10 1 1 0 0 1
+loadstatus=smt
+}
+C 56700 47600 1 0 0 LMV344-2.sym
+{
+T 56900 50100 5 10 1 1 0 0 1
+device=LMV344
+T 56900 48500 5 10 1 1 0 0 1
+refdes=U8
+T 56900 49900 5 10 0 0 0 0 1
+footprint=TI-SO-14
+T 57500 47700 5 10 1 1 0 0 1
+device=LMV344
+T 56700 47600 5 10 0 1 0 0 1
+slot=4
+T 56700 47600 5 10 1 1 0 0 1
+loadstatus=smt
+}
+C 50100 47600 1 0 0 LMV344-2.sym
+{
+T 50300 50100 5 10 1 1 0 0 1
+device=LMV344
+T 50300 48500 5 10 1 1 0 0 1
+refdes=U7
+T 50300 49900 5 10 0 0 0 0 1
+footprint=TI-SO-14
+T 50900 47700 5 10 1 1 0 0 1
+device=LMV344
+T 50100 47600 5 10 0 1 0 0 1
+slot=4
+T 50100 47600 5 10 1 1 0 0 1
+loadstatus=smt
+}