change debug header to 50 mil pitch

diff --git a/telenano.pcb b/telenano.pcb
index 38e2728db3832a1ae15ade244fe2b92080252e2e..d7fc442a89fec9c71c9ac63e034ec23704422dc5 100644 (file)
--- a/telenano.pcb
+++ b/telenano.pcb
@@ -1,5 +1,5 @@
 # release: pcb 20100929
-# date:    Tue Mar 29 17:38:22 2011
+# date:    Tue Apr 19 01:54:08 2011
 # user:    bdale (Bdale Garbee,KB0G)
 # host:    rover
 
@@ -979,15 +979,6 @@ Element["" "0402" "C23" "8.2pF" 73807 16274 -2959 -4751 1 100 ""]
 
        )
 
-Element["" "530470410" "J6" "Debug" 18300 47800 1000 -7300 0 100 ""]
-(
-       Pin[14764 0 3500 1200 4100 2047 "4" "4" "edge2"]
-       Pin[9843 0 3500 1200 4100 2047 "3" "3" "edge2"]
-       Pin[4921 0 3500 1200 4100 2047 "2" "2" "edge2"]
-       Pin[0 0 3500 1200 4100 2047 "1" "1" "square,edge2,thermal(1t)"]
-
-       )
-
 Element["" "0402" "C24" "5.6pF" 77793 16274 -3016 -4522 1 100 ""]
 (
        Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"]
@@ -1244,6 +1235,15 @@ Element["" "100mil2pin" "J1" "Power" 4200 4200 12500 -3000 0 100 ""]
        Pin[0 0 6000 2400 7000 3800 "1" "1" "square,edge2"]
        Pin[10000 0 6000 2400 7000 3800 "2" "2" "edge2"]
 
+       )
+
+Element["" "50mil4pin" "J6" "Debug" 18400 47300 0 0 0 100 ""]
+(
+       Pin[15000 0 4200 1200 4800 2800 "4" "4" "edge2"]
+       Pin[10000 0 4200 1200 4800 2800 "3" "3" "edge2"]
+       Pin[5000 0 4200 1200 4800 2800 "2" "2" "edge2"]
+       Pin[0 0 4200 1200 4800 2800 "1" "1" "square,edge2,thermal(1S)"]
+
        )
 Layer(1 "top")
 (
@@ -1330,14 +1330,14 @@ Layer(1 "top")
        Line[49000 44400 49000 36914 1000 2000 "clearline"]
        Line[49000 36914 48936 36850 1000 2000 "clearline"]
        Line[86000 25000 81386 25000 2500 2000 "clearline"]
-       Line[27900 47900 30500 44900 1000 2000 "clearline"]
-       Line[30500 44900 44200 44900 1000 2000 "clearline"]
-       Line[44200 44900 47000 42400 1000 2000 "clearline"]
+       Line[27900 47900 31200 44100 1000 2000 "clearline"]
+       Line[31200 44100 45000 44100 1000 2000 "clearline"]
+       Line[45300 44100 47000 42400 1000 2000 "clearline"]
        Line[47000 42400 47000 36882 1000 2000 "clearline"]
        Line[47000 36882 46968 36850 1000 2000 "clearline"]
-       Line[41100 43000 41100 40600 1000 2000 "clearline"]
+       Line[41100 42400 41100 40600 1000 2000 "clearline"]
        Line[41100 40600 40700 40200 1000 2000 "clearline"]
-       Line[41100 43100 26700 43100 1000 2000 "clearline"]
+       Line[41100 42400 26700 42400 1000 2000 "clearline"]
        Line[48936 8555 48574 8193 1000 2000 "clearline"]
        Line[58800 42900 58800 40000 2500 2000 "clearline"]
        Line[18314 39500 17914 39900 1000 2000 "clearline"]
@@ -1408,7 +1408,7 @@ Layer(1 "top")
        Line[77800 44600 77800 47600 2500 2000 "clearline"]
        Line[74700 47600 81300 47600 2500 2000 "clearline"]
        Line[29500 10700 28500 9700 2500 2000 "clearline"]
-       Line[25900 43900 26700 43100 1000 2000 "clearline"]
+       Line[25900 43900 26700 42400 1000 2000 "clearline"]
        Line[66200 13300 67800 11700 2500 2000 "clearline"]
        Line[29500 13100 29500 10600 2500 2000 "clearline"]
        Line[31000 10700 29500 10700 2500 2000 "clearline"]
@@ -1521,6 +1521,10 @@ Layer(2 "bottom")
 )
 Layer(3 "outline")
 (
+       Line[0 0 0 50000 1000 0 ""]
+       Line[0 50000 100000 50000 1000 0 ""]
+       Line[100000 50000 100000 0 1000 0 ""]
+       Line[100000 0 0 0 1000 0 ""]
 )
 Layer(4 "silk")
 (

diff --git a/telenano.sch b/telenano.sch
index 1e8f62a89e8611fabde1f9211f635c2c22bf1e51..0cb9353dbcd38ba1ad62643428c689d83d8fc6dc 100644 (file)
--- a/telenano.sch
+++ b/telenano.sch
@@ -1,26 +1,26 @@
-v 20100214 2
+v 20110115 2
 C 40000 40000 0 0 0 EMBEDDEDtitle-C-bdale.sym
 [
-T 31100 40800 5 10 0 0 0 0 1
+T 43200 41100 5 10 0 0 0 0 1
 graphical=1
-B 40000 40000 22000 17000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
-L 54400 41400 62000 41400 15 0 0 0 -1 -1
-T 54900 40800 9 10 1 0 0 0 2
-                Copyright 2010 by Bdale Garbee <bdale@gag.com>
-Licensed under the TAPR Open Hardware License, http://www.tapr.org/OHL
-T 54500 40100 15 10 1 0 0 0 1
-Project URL:
-L 54400 40600 62000 40600 15 0 0 0 -1 -1
-B 54400 40000 7600 2700 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
-T 58200 40400 15 8 1 0 0 0 1
-OF
-T 57400 40400 15 8 1 0 0 0 1
-PAGE
-T 59500 40400 15 8 1 0 0 0 1
-REVISION:
 T 54500 40400 15 8 1 0 0 0 1
 FILE:
-T 43200 41100 5 10 0 0 0 0 1
+T 59500 40400 15 8 1 0 0 0 1
+REVISION:
+T 57400 40400 15 8 1 0 0 0 1
+PAGE
+T 58200 40400 15 8 1 0 0 0 1
+OF
+B 54400 40000 7600 2700 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+L 54400 40600 62000 40600 15 0 0 0 -1 -1
+T 54500 40100 15 10 1 0 0 0 1
+Project URL:
+T 54900 40800 9 10 1 0 0 0 2
+                Copyright 2011 by Bdale Garbee <bdale@gag.com>
+Licensed under the TAPR Open Hardware License, http://www.tapr.org/OHL
+L 54400 41400 62000 41400 15 0 0 0 -1 -1
+B 40000 40000 22000 17000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 31100 40800 5 10 0 0 0 0 1
 graphical=1
 ]
 C 43800 54400 1 0 0 gnd-1.sym
@@ -756,7 +756,7 @@ C 42700 51900 1 0 1 conn-4.sym
 T 42400 53500 5 10 1 1 0 6 1
 refdes=J6
 T 42700 51900 5 10 0 0 0 6 1
-footprint=530470410
+footprint=50mil4pin
 T 42500 51600 5 10 1 1 0 6 1
 value=Debug
 T 42700 51900 5 10 0 0 0 6 1
@@ -766,7 +766,7 @@ device=CONNECTOR
 T 42700 51900 5 10 0 1 0 0 1
 vendor=digikey
 T 42700 51900 5 10 0 1 0 0 1
-vendor_part_number=WM1733-ND
+vendor_part_number=S9014E-04-ND
 }
 C 47500 43700 1 90 0 resistor.sym
 {