make sure all silk elements are within board outline fab-v0.1
authorBdale Garbee <bdale@gag.com>
Tue, 23 Nov 2010 06:16:59 +0000 (23:16 -0700)
committerBdale Garbee <bdale@gag.com>
Tue, 23 Nov 2010 06:16:59 +0000 (23:16 -0700)
commite68a05bed23ff47982fb23ff91dc40f3cd1f5d10
tree48af983dbdb56b1111c4fb72c2fc620c82568844
parent0239b00a2e1146f1596bd768c9c21207f15f9f9f
make sure all silk elements are within board outline
telenano.pcb