From 41ef8d5e5bdc1129ae201d37c87a3b9b49dc312b Mon Sep 17 00:00:00 2001 From: Bdale Garbee Date: Mon, 22 Nov 2010 23:18:17 -0700 Subject: [PATCH] make sure all silk elements are within board outline --- telemini.pcb | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/telemini.pcb b/telemini.pcb index 598775e..fa8d205 100644 --- a/telemini.pcb +++ b/telemini.pcb @@ -1,10 +1,10 @@ -# release: pcb 20091103 -# date: Thu Nov 18 16:19:27 2010 +# release: pcb 20100929 +# date: Mon Nov 22 23:18:13 2010 # user: bdale (Bdale Garbee,KB0G) # host: rover -# To read pcb files, the pcb version (or the cvs source date) must be >= the file version -FileVersion[20070407] +# To read pcb files, the pcb version (or the git source date) must be >= the file version +FileVersion[20100606] PCB["TeleMini" 150000 50000] @@ -13,7 +13,7 @@ Cursor[0 50000 0.000000] PolyArea[200000000.000000] Thermal[0.500000] DRC[600 1000 600 500 1500 700] -Flags("nameonpcb,clearnew,liveroute,hidenames") +Flags("nameonpcb,clearnew,liveroute") Groups("1,c:2,s:3") Styles["Signal,1000,2900,1500,1000:Power,2500,6000,3500,1000:Fat,2500,6000,3500,1000:Skinny,600,2402,1181,600"] @@ -1181,7 +1181,7 @@ Element["" "0402" "C11" "47pF" 103807 3574 -183 18726 1 100 ""] ) -Element["" "hole-M2.5" "H2" "unknown" 140000 40000 -4900 -1000 0 100 ""] +Element["" "hole-M2.5" "H2" "unknown" 140000 40000 -3700 -2700 0 100 ""] ( Pin[0 0 12000 2000 12600 9800 "1" "1" "usetherm,thermal(1S)"] ElementArc [0 0 8000 8000 0 360 1000] @@ -1309,7 +1309,7 @@ Element["" "SO8" "Q1" "FDS9926A" 35900 24700 -6000 2000 1 100 ""] ) -Element["" "530470410" "J6" "Debug" 67800 47600 0 0 0 100 ""] +Element["" "530470410" "J6" "Debug" 67800 47600 500 -7200 0 100 ""] ( Pin[14764 0 3500 1200 4100 2047 "4" "4" "edge2"] Pin[9843 0 3500 1200 4100 2047 "3" "3" "edge2"] -- 2.30.2