N 46500 69100 51700 69100 4
N 44500 70000 44500 70400 4
N 45700 70000 45700 70400 4
-N 43700 69100 43300 69100 4
-C 43100 69100 1 0 0 3.3V-plus-1.sym
C 44800 66800 1 0 0 gnd-1.sym
N 44900 67100 44900 67800 4
N 43700 68700 43300 68700 4
a CP2103 GPIO interface to the debug port suggests
we may need a stiff pullup. Consider 10k a placeholder
for experimentation once we have real boards in hand.
+N 42400 69100 43700 69100 4
+{
+T 42400 69200 5 10 1 1 0 0 1
+netname=v_lipo
+}