From: Bdale Garbee <bdale@gag.com>
Date: Wed, 13 Jun 2012 16:42:04 +0000 (-0600)
Subject: move Vlcd to 3.3V instead of the analog rail
X-Git-Tag: fab-v0.2~51
X-Git-Url: https://git.gag.com/?p=hw%2Ftelemega;a=commitdiff_plain;h=6fefe66696336e65ea361a9561b4a83a391e1b63

move Vlcd to 3.3V instead of the analog rail
---

diff --git a/megametrum.pcb b/megametrum.pcb
index bebbe1d..482545b 100644
--- a/megametrum.pcb
+++ b/megametrum.pcb
@@ -6,7 +6,7 @@ FileVersion[20070407]
 PCB["MegaMetrum" 325000 125000]
 
 Grid[100.0 0 0 0]
-Cursor[20000 400 0.000000]
+Cursor[126204 17508 0.000000]
 PolyArea[200000000.000000]
 Thermal[0.500000]
 DRC[600 1000 600 500 1500 700]
@@ -2191,13 +2191,6 @@ Element["hidename,onsolder" "TDK_PS12" "U8" "TDK_PS12" 135500 62542 8100 -3316 1
 
 	)
 
-Element["hidename" "0402" "R29" "1.5k" 149674 29600 -4572 -7350 0 100 ""]
-(
-	Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"]
-	Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"]
-
-	)
-
 Element["hidename" "lqfp100" "U7" "STM32L151" 183000 62500 -2700 -8600 0 100 ""]
 (
 	Pad[23621 28739 23621 32282 1181 787 1811 "PA2/USART2_TX/ADC_IN2/TIM2_CH3/TIM9_CH1" "25" "square,edge2"]
@@ -3066,16 +3059,6 @@ Layer(1 "top")
 	Line[199000 87900 197900 86800 1000 2000 "clearline"]
 	Line[197900 86800 195500 86800 1000 2000 "clearline"]
 	Line[195500 86800 192600 83900 1000 2000 "clearline"]
-	Line[200716 93010 200700 89500 1000 2000 "clearline"]
-	Line[200716 89716 200600 89600 1000 2000 "clearline"]
-	Line[200500 89500 193100 89500 1000 2000 "clearline"]
-	Line[193100 89500 187800 84200 1000 2000 "clearline"]
-	Line[187800 84200 174200 84200 1000 2000 "clearline"]
-	Line[174200 84200 169200 89200 1000 2000 "clearline"]
-	Line[169200 89200 169200 92990 1000 2000 "clearline"]
-	Line[169200 92990 169220 93010 1000 2000 "clearline"]
-	Line[148100 29600 148100 26600 1000 2000 "clearline"]
-	Line[151248 29600 156000 29600 1000 2000 "clearline"]
 	Line[202684 23584 200800 21700 1000 2000 "clearline"]
 	Line[200800 21700 200800 11900 1000 2000 "clearline"]
 	Line[202684 23584 202684 36384 1000 2000 "clearline"]
@@ -3341,6 +3324,9 @@ Layer(1 "top")
 	Line[26900 10300 28400 11800 1000 2000 "clearline"]
 	Line[28400 11800 30176 11800 1000 2000 "clearline"]
 	Line[30176 11800 30181 11795 1000 2000 "clearline"]
+	Line[169220 93010 169220 89680 1000 2000 "clearline"]
+	Line[169220 89680 170100 88800 1000 2000 "clearline"]
+	Line[170100 88800 179063 88800 1000 2000 "clearline"]
 	Polygon("")
 	(
 		[308000 1000] [324000 1000] [324000 55500] [308000 55500] 
@@ -3822,7 +3808,6 @@ NetList()
 		Connect("J20-6")
 		Connect("L5-2")
 		Connect("L600-1")
-		Connect("R29-1")
 		Connect("R36-1")
 		Connect("R171-1")
 		Connect("U3-9")
@@ -3839,6 +3824,7 @@ NetList()
 		Connect("U6-25")
 		Connect("U6-27")
 		Connect("U6-28")
+		Connect("U7-6")
 		Connect("U7-11")
 		Connect("U7-21")
 		Connect("U7-28")
@@ -4571,7 +4557,6 @@ NetList()
 	Net("usbdp" "(unknown)")
 	(
 		Connect("J5-3")
-		Connect("R29-2")
 		Connect("U7-71")
 	)
 	Net("v_batt" "(unknown)")
@@ -4627,7 +4612,6 @@ NetList()
 		Connect("C601-1")
 		Connect("C602-1")
 		Connect("L600-2")
-		Connect("U7-6")
 		Connect("U7-22")
 	)
 )
diff --git a/megametrum.sch b/megametrum.sch
index cc013a8..d5bf4ff 100644
--- a/megametrum.sch
+++ b/megametrum.sch
@@ -1696,7 +1696,7 @@ loadstatus=smt
 }
 C 59700 73000 1 0 0 3.3V-plus.sym
 N 59900 72000 59900 73000 4
-N 59900 72100 61500 72100 4
+N 59900 72100 61900 72100 4
 N 61500 72100 61500 72000 4
 N 60700 72100 60700 72000 4
 N 60300 72100 60300 72000 4
@@ -3253,7 +3253,6 @@ N 56300 58800 55000 58800 4
 T 55000 58900 5 10 1 1 0 0 1
 netname=v_pbatt
 }
-N 61900 72100 62300 72100 4
 N 43800 65400 43300 65400 4
 N 43300 64500 43300 63400 4
 N 43800 65800 42600 65800 4