From: Keith Packard Date: Mon, 30 Jul 2012 04:09:29 +0000 (-0700) Subject: switch to STM152LRBT6 X-Git-Tag: v0.1~21 X-Git-Url: https://git.gag.com/?p=hw%2Ftelelco;a=commitdiff_plain;h=6e94c1160784e81ac50104d6fdcb407d4f3576ba switch to STM152LRBT6 Need the LCD controller in the 152 version Signed-off-by: Keith Packard --- diff --git a/symbols/STM32L152-64.sym b/symbols/STM32L152-64.sym new file mode 100644 index 0000000..664c2aa --- /dev/null +++ b/symbols/STM32L152-64.sym @@ -0,0 +1,718 @@ +v 20110115 2 +P 9500 18400 9100 18400 1 0 0 +{ +T 9195 18445 5 10 1 1 0 0 1 +pinnumber=11 +T 9045 18395 3 10 1 1 0 6 1 +pinlabel=PC3/ADC_IN13/SEG21 +T 9900 18500 5 10 0 1 0 6 1 +pinseq=3 +T 9500 18400 5 10 0 1 0 6 1 +pintype=io +} +P 5800 0 5800 400 1 0 0 +{ +T 5750 305 5 10 1 1 90 6 1 +pinnumber=12 +T 5800 455 3 10 1 1 90 0 1 +pinlabel=VSSA +T 5700 -400 5 10 0 1 90 0 1 +pinseq=21 +T 5800 0 5 10 0 1 90 0 1 +pintype=pwr +} +B 400 400 8700 19600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T -6400 -2200 8 10 0 0 0 0 1 +description=STMicro Cortex-M3 +T -6400 -1300 8 10 0 0 0 0 1 +numslots=1 +T -6400 -1600 8 10 0 0 0 0 1 +device=STM32L152RBT6 +T 2750 17450 9 30 1 0 0 0 1 +STM32L152RBT6 +T -6400 -1000 8 10 0 0 0 0 1 +slot=1 +T 400 20100 8 10 1 1 0 0 1 +refdes=U? +P 0 15200 400 15200 1 0 0 +{ +T 305 15245 5 10 1 1 0 6 1 +pinnumber=7 +T 455 15195 3 10 1 1 0 0 1 +pinlabel=NRST +T 0 15200 5 10 0 1 0 6 1 +pinseq=25 +T 0 15200 5 10 0 1 0 6 1 +pintype=io +} +P 9500 19600 9100 19600 1 0 0 +{ +T 9195 19645 5 10 1 1 0 0 1 +pinnumber=8 +T 9045 19595 3 10 1 1 0 6 1 +pinlabel=PC0/ADC_IN10/SEG18 +T 9500 19600 5 10 0 1 0 0 1 +pinseq=25 +T 9500 19600 5 10 0 1 0 0 1 +pintype=io +} +P 9500 18800 9100 18800 1 0 0 +{ +T 9195 18845 5 10 1 1 0 0 1 +pinnumber=10 +T 9045 18795 3 10 1 1 0 6 1 +pinlabel=PC2/ADC_IN12/SEG20 +T 9500 18800 5 10 0 1 0 0 1 +pinseq=25 +T 9500 18800 5 10 0 1 0 0 1 +pintype=io +} +P 9500 19200 9100 19200 1 0 0 +{ +T 9195 19245 5 10 1 1 0 0 1 +pinnumber=9 +T 9045 19195 3 10 1 1 0 6 1 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455 3195 3 10 1 1 0 0 1 +pinlabel=PB11/I2C2_SDA/USART3_RX/TIM2_CH4/SEG11 +T -400 3300 5 10 0 1 0 0 1 +pinseq=21 +T 0 3200 5 10 0 1 0 0 1 +pintype=io +} +P 3800 0 3800 400 1 0 0 +{ +T 3750 305 5 10 1 1 90 6 1 +pinnumber=31 +T 3800 455 3 10 1 1 90 0 1 +pinlabel=VSS1 +T 3800 0 5 10 0 1 90 6 1 +pinseq=25 +T 3800 0 5 10 0 1 90 6 1 +pintype=pwr +} +P 3600 20400 3600 20000 1 0 0 +{ +T 3550 20095 5 10 1 1 90 0 1 +pinnumber=32 +T 3600 19945 3 10 1 1 90 6 1 +pinlabel=VDD1 +T 3500 20800 5 10 0 1 270 2 1 +pinseq=21 +T 3600 20400 5 10 0 1 270 2 1 +pintype=pwr +} +P 9500 17600 9100 17600 1 0 0 +{ +T 9195 17645 5 10 1 1 0 0 1 +pinnumber=25 +T 9045 17595 3 10 1 1 0 6 1 +pinlabel=PC5/ADC_IN15/SEG23 +T 9900 17700 5 10 0 1 0 6 1 +pinseq=18 +T 9500 17600 5 10 0 1 0 6 1 +pintype=io +} +P 0 2000 400 2000 1 0 0 +{ +T 305 2045 5 10 1 1 0 6 1 +pinnumber=35 +T 455 1995 3 10 1 1 0 0 1 +pinlabel=PB14/SPI2_MISO/USART3_RTS/ADC_IN20/TIM9_CH2/SEG14 +T -400 2100 5 10 0 1 0 0 1 +pinseq=18 +T 0 2000 5 10 0 1 0 0 1 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1 0 0 1 +pinlabel=PA11/USART1_CTS/USBDM/SPI1_MISO +T 0 9600 5 10 0 1 0 6 1 +pinseq=25 +T 0 9600 5 10 0 1 0 6 1 +pintype=io +} +P 9500 16800 9100 16800 1 0 0 +{ +T 9195 16845 5 10 1 1 0 0 1 +pinnumber=38 +T 9045 16795 3 10 1 1 0 6 1 +pinlabel=PC7/TIM3_CH2/SEG25 +T 9500 16800 5 10 0 1 0 0 1 +pinseq=25 +T 9500 16800 5 10 0 1 0 0 1 +pintype=io +} +P 9500 16400 9100 16400 1 0 0 +{ +T 9195 16445 5 10 1 1 0 0 1 +pinnumber=39 +T 9045 16395 3 10 1 1 0 6 1 +pinlabel=PC8/TIM3_CH3/SEG26 +T 9500 16400 5 10 0 1 0 0 1 +pinseq=25 +T 9500 16400 5 10 0 1 0 0 1 +pintype=io +} +P 0 10800 400 10800 1 0 0 +{ +T 305 10845 5 10 1 1 0 6 1 +pinnumber=41 +T 455 10795 3 10 1 1 0 0 1 +pinlabel=PA8/USART1_CK/MCO/COM0 +T 0 10800 5 10 0 1 0 6 1 +pinseq=25 +T 0 10800 5 10 0 1 0 6 1 +pintype=io +} +P 9500 16000 9100 16000 1 0 0 +{ +T 9195 16045 5 10 1 1 0 0 1 +pinnumber=40 +T 9045 15995 3 10 1 1 0 6 1 +pinlabel=PC9/TIM3_CH4/SEG27 +T 9500 16000 5 10 0 1 0 0 1 +pinseq=25 +T 9500 16000 5 10 0 1 0 0 1 +pintype=io +} +P 9500 17200 9100 17200 1 0 0 +{ +T 9195 17245 5 10 1 1 0 0 1 +pinnumber=37 +T 9045 17195 3 10 1 1 0 6 1 +pinlabel=PC6/TIM3_CH1/SEG24 +T 9500 17200 5 10 0 1 0 0 1 +pinseq=25 +T 9500 17200 5 10 0 1 0 0 1 +pintype=io +} +P 0 9200 400 9200 1 0 0 +{ +T 100 9300 5 10 1 1 0 0 1 +pinnumber=45 +T 500 9200 3 10 1 1 0 0 1 +pinlabel=PA12/USART1_RTS/USBDP/SPI1_MOSI +T -400 9300 5 10 0 1 0 0 1 +pinseq=21 +T 0 9200 5 10 0 1 0 0 1 +pintype=io +} +P 0 1600 400 1600 1 0 0 +{ +T 305 1645 5 10 1 1 0 6 1 +pinnumber=36 +T 455 1595 3 10 1 1 0 0 1 +pinlabel=PB15/SPI2_MOSI/ADC_IN21/TIM11_CH1/RTC_50_60HZ/SEG15 +T -400 1700 5 10 0 1 0 0 1 +pinseq=18 +T 0 1600 5 10 0 1 0 0 1 +pintype=io +} +P 0 8800 400 8800 1 0 0 +{ +T 100 8900 5 10 1 1 0 0 1 +pinnumber=46 +T 500 8800 3 10 1 1 0 0 1 +pinlabel=PA13/JTMS/SWDIO +T -400 8900 5 10 0 1 0 0 1 +pinseq=3 +T 0 8800 5 10 0 1 0 0 1 +pintype=io +} +P 4200 0 4200 400 1 0 0 +{ +T 4150 305 5 10 1 1 90 6 1 +pinnumber=47 +T 4200 455 3 10 1 1 90 0 1 +pinlabel=VSS2 +T 4200 0 5 10 0 1 90 6 1 +pinseq=25 +T 4200 0 5 10 0 1 90 6 1 +pintype=pwr +} +P 4000 20400 4000 20000 1 0 0 +{ +T 3950 20095 5 10 1 1 90 0 1 +pinnumber=48 +T 4000 19945 3 10 1 1 90 6 1 +pinlabel=VDD2 +T 3900 20800 5 10 0 1 270 2 1 +pinseq=21 +T 4000 20400 5 10 0 1 270 2 1 +pintype=pwr +} +P 9500 15600 9100 15600 1 0 0 +{ +T 9195 15645 5 10 1 1 0 0 1 +pinnumber=51 +T 9045 15595 3 10 1 1 0 6 1 +pinlabel=PC10/USART3_TX/COM4/SEG28/SEG40 +T 9900 15700 5 10 0 1 0 6 1 +pinseq=18 +T 9500 15600 5 10 0 1 0 6 1 +pintype=io +} +P 0 8000 400 8000 1 0 0 +{ +T 100 8100 5 10 1 1 0 0 1 +pinnumber=50 +T 500 8000 3 10 1 1 0 0 1 +pinlabel=PA15/JTDI/TIM2_CH1_ETR/SPI1_NSS/SEG17 +T -400 8100 5 10 0 1 0 0 1 +pinseq=4 +T 0 8000 5 10 0 1 0 0 1 +pintype=io +} +P 0 8400 400 8400 1 0 0 +{ +T 100 8500 5 10 1 1 0 0 1 +pinnumber=49 +T 500 8400 3 10 1 1 0 0 1 +pinlabel=PA14/JTCK/SWCLK +T -400 8500 5 10 0 1 0 0 1 +pinseq=20 +T 0 8400 5 10 0 1 0 0 1 +pintype=io +} +P 0 4800 400 4800 1 0 0 +{ +T 305 4845 5 10 1 1 0 6 1 +pinnumber=59 +T 455 4795 3 10 1 1 0 0 1 +pinlabel=PB7/I2C1_SDA/TIM4_CH2/USART1_RX/PVD_IN +T -400 4900 5 10 0 1 0 0 1 +pinseq=3 +T 0 4800 5 10 0 1 0 0 1 +pintype=io +} +P 0 16000 400 16000 1 0 0 +{ +T 100 16100 5 10 1 1 0 0 1 +pinnumber=60 +T 500 16000 3 10 1 1 0 0 1 +pinlabel=BOOT0 +T -400 16100 5 10 0 1 0 0 1 +pinseq=21 +T 0 16000 5 10 0 1 0 0 1 +pintype=in +} +P 0 4400 400 4400 1 0 0 +{ +T 305 4445 5 10 1 1 0 6 1 +pinnumber=61 +T 455 4395 3 10 1 1 0 0 1 +pinlabel=PB8/TIM4_CH3/I2C1_SCL/TIM10_CH1/SEG16 +T 0 4400 5 10 0 1 0 6 1 +pinseq=25 +T 0 4400 5 10 0 1 0 6 1 +pintype=io +} +P 0 6400 400 6400 1 0 0 +{ +T 305 6445 5 10 1 1 0 6 1 +pinnumber=55 +T 455 6395 3 10 1 1 0 0 1 +pinlabel=PB3/JTDO/TIM2_CH2/TRACESWO/SPI1_SCK/SEG7 +T 0 6400 5 10 0 1 0 6 1 +pinseq=25 +T 0 6400 5 10 0 1 0 6 1 +pintype=io +} +P 0 6000 400 6000 1 0 0 +{ +T 305 6045 5 10 1 1 0 6 1 +pinnumber=56 +T 455 5995 3 10 1 1 0 0 1 +pinlabel=PB4/JNTRSTSPI1_MISO/TIM3_CH1/SEG8 +T 0 6000 5 10 0 1 0 6 1 +pinseq=25 +T 0 6000 5 10 0 1 0 6 1 +pintype=io +} +P 0 5200 400 5200 1 0 0 +{ +T 305 5245 5 10 1 1 0 6 1 +pinnumber=58 +T 455 5195 3 10 1 1 0 0 1 +pinlabel=PB6/I2C1_SCL/TIM4_CH1/USART1_TX +T 0 5200 5 10 0 1 0 6 1 +pinseq=25 +T 0 5200 5 10 0 1 0 6 1 +pintype=io +} +P 0 5600 400 5600 1 0 0 +{ +T 305 5645 5 10 1 1 0 6 1 +pinnumber=57 +T 455 5595 3 10 1 1 0 0 1 +pinlabel=PB5/I2C1_SMBA/TIM3_CH2/SPI1_MOSI/SEG9 +T 0 5600 5 10 0 1 0 6 1 +pinseq=25 +T 0 5600 5 10 0 1 0 6 1 +pintype=io +} +P 0 4000 400 4000 1 0 0 +{ +T 305 4045 5 10 1 1 0 6 1 +pinnumber=62 +T 455 3995 3 10 1 1 0 0 1 +pinlabel=PB9/TIM4_CH4/I2C1_SDA/TIM11_CH1/COM3 +T -400 4100 5 10 0 1 0 0 1 +pinseq=21 +T 0 4000 5 10 0 1 0 0 1 +pintype=io +} +P 9500 15200 9100 15200 1 0 0 +{ +T 9195 15245 5 10 1 1 0 0 1 +pinnumber=52 +T 9045 15195 3 10 1 1 0 6 1 +pinlabel=PC11/USART3_RX/COM5/SEG29/SEG41 +T 9900 15300 5 10 0 1 0 6 1 +pinseq=18 +T 9500 15200 5 10 0 1 0 6 1 +pintype=io +} +P 9500 14800 9100 14800 1 0 0 +{ +T 9195 14845 5 10 1 1 0 0 1 +pinnumber=53 +T 9045 14795 3 10 1 1 0 6 1 +pinlabel=PC12/USART3_CK/COM6/SEG30/SEG42 +T 9900 14900 5 10 0 1 0 6 1 +pinseq=20 +T 9500 14800 5 10 0 1 0 6 1 +pintype=io +} +P 9500 12400 9100 12400 1 0 0 +{ +T 9195 12445 5 10 1 1 0 0 1 +pinnumber=54 +T 9045 12395 3 10 1 1 0 6 1 +pinlabel=PD2/TIM3_ETR/COM7/SEG31/SEG43 +T 9900 12500 5 10 0 1 0 6 1 +pinseq=18 +T 9500 12400 5 10 0 1 0 6 1 +pintype=io +} +P 4600 0 4600 400 1 0 0 +{ +T 4550 305 5 10 1 1 90 6 1 +pinnumber=63 +T 4600 455 3 10 1 1 90 0 1 +pinlabel=VSS3 +T 4600 0 5 10 0 1 90 6 1 +pinseq=25 +T 4600 0 5 10 0 1 90 6 1 +pintype=pwr +} +P 4400 20400 4400 20000 1 0 0 +{ +T 4350 20095 5 10 1 1 90 0 1 +pinnumber=64 +T 4400 19945 3 10 1 1 90 6 1 +pinlabel=VDD3 +T 4300 20800 5 10 0 1 270 2 1 +pinseq=21 +T 4400 20400 5 10 0 1 270 2 1 +pintype=pwr +} diff --git a/telelco.pcb b/telelco.pcb index 7fab79c..e360454 100644 --- a/telelco.pcb +++ b/telelco.pcb @@ -6,7 +6,7 @@ FileVersion[20070407] PCB["TeleLco" 450000 375000] Grid[100.0 0 0 0] -Cursor[76300 17200 0.000000] +Cursor[0 0 0.000000] PolyArea[200000000.000000] Thermal[0.500000] DRC[500 1000 500 500 1500 650] @@ -2512,8 +2512,6 @@ Layer(1 "top") Line[173800 162200 173800 156400 1000 2000 "clearline"] Line[173800 156400 177600 152600 1000 2000 "clearline"] Line[177600 152600 180600 152600 1000 2000 "clearline"] - Line[202143 113427 202143 109857 1000 2000 "clearline"] - Line[202143 109857 202200 109800 1000 2000 "clearline"] Line[238000 113000 214000 113000 1000 2000 "clearline"] Line[214000 113000 210900 109900 1000 2000 "clearline"] Line[210900 109900 202143 109900 1000 2000 "clearline"] @@ -2722,9 +2720,6 @@ Layer(1 "top") Line[131600 82200 131600 76100 1000 2000 "clearline"] Line[135500 94900 135500 76852 1000 2000 "clearline"] Line[135500 76852 134748 76100 1000 2000 "clearline"] - Line[191700 109000 190400 110300 1000 2000 "clearline"] - Line[190400 110300 190400 113360 1000 2000 "clearline"] - Line[190400 113360 190333 113427 1000 2000 "clearline"] Line[178522 113427 178522 109022 1000 2000 "clearline"] Line[178522 109022 178500 109000 1000 2000 "clearline"] Line[178500 109000 178500 105000 1000 2000 "clearline"] @@ -2931,6 +2926,12 @@ Layer(1 "top") Line[73500 110000 65100 118400 1000 2000 "clearline"] Line[65100 118400 65100 120679 1000 2000 "clearline"] Line[65100 120679 65104 120683 1000 2000 "clearline"] + Line[194269 113427 194269 110069 1000 2000 "clearline"] + Line[194269 110069 194200 110000 1000 2000 "clearline"] + Line[194200 110000 194200 109900 1000 2000 "clearline"] + Line[194200 109900 193300 109000 1000 2000 "clearline"] + Line[193300 109000 191700 109000 1000 2000 "clearline"] + Line[202143 109900 202143 113427 1000 2000 "clearline"] ) Layer(2 "bottom") ( @@ -3367,7 +3368,7 @@ NetList() ) Net("seg_dp" "(unknown)") ( - Connect("U7-57") + Connect("U7-55") Connect("U20-9") Connect("U20-10") Connect("U21-9") diff --git a/telelco.sch b/telelco.sch index 60f8230..2f5425e 100644 --- a/telelco.sch +++ b/telelco.sch @@ -336,9 +336,9 @@ N 53600 69900 52300 69900 4 T 52300 70000 5 10 1 1 0 0 1 netname=seg_c } -N 53600 62700 52300 62700 4 +N 53600 63500 52300 63500 4 { -T 52900 62800 5 10 1 1 0 6 1 +T 52900 63600 5 10 1 1 0 6 1 netname=seg_dp } C 66000 74000 1 180 0 resistor.sym @@ -1575,7 +1575,7 @@ T 58300 77900 5 10 0 0 0 0 1 footprint=0402 } C 58200 77800 1 0 0 gnd.sym -C 53600 57100 1 0 0 STM32L151-64.sym +C 53600 57100 1 0 0 STM32L152-64.sym { T 47200 55500 5 10 0 0 0 0 1 device=ATmega328P