From: Keith Packard Date: Tue, 11 Sep 2012 05:48:37 +0000 (-0700) Subject: Fix DRC errors found by freedfm X-Git-Tag: fab-v2.0~48 X-Git-Url: https://git.gag.com/?p=hw%2Ftelelco;a=commitdiff_plain;h=2eb52eb443ee706a9a17c636bc712dcc32e20148 Fix DRC errors found by freedfm A couple of vias were mis-placed by 1mil, making traces too close together. The internal DRC rules checking code didn't find them. Signed-off-by: Keith Packard --- diff --git a/telelco.pcb b/telelco.pcb index e683b71..9833562 100644 --- a/telelco.pcb +++ b/telelco.pcb @@ -6,7 +6,7 @@ FileVersion[20070407] PCB["TeleLco" 450000 375000] Grid[100.0 0 0 0] -Cursor[70500 0 0.000000] +Cursor[85500 116800 0.000000] PolyArea[200000000.000000] Thermal[0.500000] DRC[500 1000 500 500 1500 650] @@ -877,7 +877,7 @@ Via[167300 229500 3000 2000 0 1500 "" ""] Via[164900 232200 3000 2000 0 1500 "" ""] Via[169000 171700 3000 2000 0 1500 "" ""] Via[155500 148300 3000 2000 0 1500 "" ""] -Via[151900 148200 3000 2000 0 1500 "" ""] +Via[151900 148300 3000 2000 0 1500 "" ""] Via[148300 148300 3000 2000 0 1500 "" ""] Via[186500 105000 3000 2000 0 1500 "" ""] Via[191800 105000 3000 2000 0 1500 "" ""] @@ -916,7 +916,7 @@ Via[156200 54600 3000 2000 0 1500 "" ""] Via[156200 39100 3000 2000 0 1500 "" ""] Via[330700 271500 3000 2000 0 1500 "" ""] Via[179800 296500 3000 2000 0 1500 "" ""] -Via[170100 296500 3000 2000 0 1500 "" ""] +Via[169700 296500 3000 2000 0 1500 "" ""] Element["" "TDK_PS12" "U8" "TDK_PS12" 225000 277558 -4600 -3632 0 100 ""] ( @@ -2890,7 +2890,6 @@ Layer(1 "top") Line[130300 95500 130300 97848 1000 2000 "clearline"] Line[130300 97848 130352 97900 1000 2000 "clearline"] Line[156200 39100 156200 7600 1000 2000 "clearline"] - Line[105000 296500 170100 296500 1000 2000 "clearline"] Line[282900 296500 179800 296500 1000 2000 "clearline"] Line[74060 133576 75624 133576 1000 2000 "clearline"] Line[75624 133576 76700 132500 1000 2000 "clearline"] @@ -2902,6 +2901,7 @@ Layer(1 "top") Line[78200 54400 74700 50900 1000 2000 "clearline"] Line[82100 105752 82100 53200 1000 2000 "clearline"] Line[82100 53200 84500 50800 1000 2000 "clearline"] + Line[105000 296500 169700 296500 1000 2000 "clearline"] ) Layer(2 "bottom") ( @@ -2944,10 +2944,6 @@ Layer(2 "bottom") Line[164900 232200 182600 232200 1000 2000 "clearline"] Line[161400 128900 161400 142400 1000 2000 "clearline"] Line[161400 142400 155500 148300 1000 2000 "clearline"] - Line[157800 128900 157800 142300 1000 2000 "clearline"] - Line[157800 142300 151900 148200 1000 2000 "clearline"] - Line[154200 128900 154200 142400 1000 2000 "clearline"] - Line[154200 142400 148300 148300 1000 2000 "clearline"] Line[191800 105000 186500 105000 1000 2000 "clearline"] Line[150700 113500 150700 142300 1000 2000 "clearline"] Line[150700 142300 144700 148300 1000 2000 "clearline"] @@ -2982,7 +2978,11 @@ Layer(2 "bottom") Line[156200 54600 156200 39100 1000 2000 "clearline"] Line[330700 271500 303700 271500 1000 2000 "clearline"] Line[303700 271500 283700 291500 1000 2000 "clearline"] - Line[170100 296500 179800 296500 1000 2000 "clearline"] + Line[179800 296500 169700 296500 1000 2000 "clearline"] + Line[157800 128900 157800 142400 1000 2000 "clearline"] + Line[157800 142400 151900 148300 1000 2000 "clearline"] + Line[154200 128900 154200 142400 1000 2000 "clearline"] + Line[154200 142400 148300 148300 1000 2000 "clearline"] Polygon("clearpoly") ( [1000 1000] [449000 1000] [449000 374000] [1000 374000]