switch to STM152LRBT6

[hw/telelco] / telelco.pcb

diff --git a/telelco.pcb b/telelco.pcb
index 7fab79cd9a97767eb03c74e7a4e7ac90f15c4ae0..e3604549286ecbe37272b0ed98ab4d9dbc47d587 100644 (file)
--- a/telelco.pcb
+++ b/telelco.pcb
@@ -6,7 +6,7 @@ FileVersion[20070407]
 PCB["TeleLco" 450000 375000]
 
 Grid[100.0 0 0 0]
-Cursor[76300 17200 0.000000]
+Cursor[0 0 0.000000]
 PolyArea[200000000.000000]
 Thermal[0.500000]
 DRC[500 1000 500 500 1500 650]
@@ -2512,8 +2512,6 @@ Layer(1 "top")
        Line[173800 162200 173800 156400 1000 2000 "clearline"]
        Line[173800 156400 177600 152600 1000 2000 "clearline"]
        Line[177600 152600 180600 152600 1000 2000 "clearline"]
-       Line[202143 113427 202143 109857 1000 2000 "clearline"]
-       Line[202143 109857 202200 109800 1000 2000 "clearline"]
        Line[238000 113000 214000 113000 1000 2000 "clearline"]
        Line[214000 113000 210900 109900 1000 2000 "clearline"]
        Line[210900 109900 202143 109900 1000 2000 "clearline"]
@@ -2722,9 +2720,6 @@ Layer(1 "top")
        Line[131600 82200 131600 76100 1000 2000 "clearline"]
        Line[135500 94900 135500 76852 1000 2000 "clearline"]
        Line[135500 76852 134748 76100 1000 2000 "clearline"]
-       Line[191700 109000 190400 110300 1000 2000 "clearline"]
-       Line[190400 110300 190400 113360 1000 2000 "clearline"]
-       Line[190400 113360 190333 113427 1000 2000 "clearline"]
        Line[178522 113427 178522 109022 1000 2000 "clearline"]
        Line[178522 109022 178500 109000 1000 2000 "clearline"]
        Line[178500 109000 178500 105000 1000 2000 "clearline"]
@@ -2931,6 +2926,12 @@ Layer(1 "top")
        Line[73500 110000 65100 118400 1000 2000 "clearline"]
        Line[65100 118400 65100 120679 1000 2000 "clearline"]
        Line[65100 120679 65104 120683 1000 2000 "clearline"]
+       Line[194269 113427 194269 110069 1000 2000 "clearline"]
+       Line[194269 110069 194200 110000 1000 2000 "clearline"]
+       Line[194200 110000 194200 109900 1000 2000 "clearline"]
+       Line[194200 109900 193300 109000 1000 2000 "clearline"]
+       Line[193300 109000 191700 109000 1000 2000 "clearline"]
+       Line[202143 109900 202143 113427 1000 2000 "clearline"]
 )
 Layer(2 "bottom")
 (
@@ -3367,7 +3368,7 @@ NetList()
        )
        Net("seg_dp" "(unknown)")
        (
-               Connect("U7-57")
+               Connect("U7-55")
                Connect("U20-9")
                Connect("U20-10")
                Connect("U21-9")