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eliminate spurious feature in outline layer
[hw/telelco]
/
Makefile
diff --git
a/Makefile
b/Makefile
index 188ce4c7d6ba80292a3d6ebb4e2b3e8f87e2a2f7..a740498b6c8ddba0250bb83ec20878f45099d21a 100644
(file)
--- a/
Makefile
+++ b/
Makefile
@@
-1,8
+1,4
@@
PROJECT=telelco
-
SCHEMATICS=telelco.sch
-LAYERS=2
-
-SILK=both
-include ../altusmetrum/pcb.mk
+include ../altusmetrum/pcb
-rnd
.mk