generate silk both sides, but hide all refdes fab-v2.0
authorBdale Garbee <bdale@gag.com>
Thu, 10 Aug 2017 03:23:11 +0000 (23:23 -0400)
committerBdale Garbee <bdale@gag.com>
Thu, 10 Aug 2017 03:23:11 +0000 (23:23 -0400)
commit1dfca760c1d496e9b1cc30a75c108231258fed39
tree785976ca7ce2db59c8c5a6f5f8cfb68e01360859
parent89516292336d161f3a24ec56b8e9ee79e8c7c4eb
generate silk both sides, but hide all refdes
Makefile
telegps.pcb