From cd23d8d06effd21d7e806eafb976d7809909d593 Mon Sep 17 00:00:00 2001 From: Bdale Garbee Date: Sat, 2 Jan 2010 23:09:08 -0700 Subject: [PATCH] pull ends of traces used to clear milled corners in from board edge 10 mils --- teledongle.pcb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/teledongle.pcb b/teledongle.pcb index cf1fc8c..97cbdb4 100644 --- a/teledongle.pcb +++ b/teledongle.pcb @@ -1569,10 +1569,10 @@ Layer(2 "bottom") Line[8600 75000 4600 71000 1000 2000 "clearline"] Line[4600 71000 4600 50100 1000 2000 "clearline"] Line[4600 50100 11200 43500 1000 2000 "clearline"] - Line[88400 0 88400 9750 600 2000 "clearline"] - Line[100250 21600 110000 21600 600 2000 "clearline"] - Line[21600 110000 21600 100250 600 2000 "clearline"] - Line[9750 88400 0 88400 600 2000 "clearline"] + Line[88400 1000 88400 9750 600 2000 "clearline"] + Line[100250 21600 109000 21600 600 2000 "clearline"] + Line[21600 109000 21600 100250 600 2000 "clearline"] + Line[9750 88400 1000 88400 600 2000 "clearline"] Arc[100250 9750 11800 11800 600 2000 0 90 "clearline"] Arc[9750 100250 11800 11800 600 2000 180 90 "clearline"] Polygon("clearpoly") -- 2.30.2