From: Bdale Garbee <bdale@gag.com>
Date: Sun, 3 Jan 2010 03:25:33 +0000 (-0700)
Subject: use traces at board outline to force bottom layer plane away from
X-Git-Tag: quote-v0.2~19
X-Git-Url: https://git.gag.com/?p=hw%2Fteledongle;a=commitdiff_plain;h=66815d0e1da23a52d0df26688c7020e5d1d7262b

use traces at board outline to force bottom layer plane away from
notched corners .. can't think of a better way to do it right now?
---

diff --git a/teledongle.pcb b/teledongle.pcb
index b15dc8f..cf1fc8c 100644
--- a/teledongle.pcb
+++ b/teledongle.pcb
@@ -1,5 +1,5 @@
 # release: pcb 20091103
-# date:    Sat Jan  2 20:15:50 2010
+# date:    Sat Jan  2 20:25:26 2010
 # user:    bdale (Bdale Garbee,KB0G)
 # host:    rover
 
@@ -1569,6 +1569,12 @@ Layer(2 "bottom")
 	Line[8600 75000 4600 71000 1000 2000 "clearline"]
 	Line[4600 71000 4600 50100 1000 2000 "clearline"]
 	Line[4600 50100 11200 43500 1000 2000 "clearline"]
+	Line[88400 0 88400 9750 600 2000 "clearline"]
+	Line[100250 21600 110000 21600 600 2000 "clearline"]
+	Line[21600 110000 21600 100250 600 2000 "clearline"]
+	Line[9750 88400 0 88400 600 2000 "clearline"]
+	Arc[100250 9750 11800 11800 600 2000 0 90 "clearline"]
+	Arc[9750 100250 11800 11800 600 2000 180 90 "clearline"]
 	Polygon("clearpoly")
 	(
 		[1000 109000] [108800 109000] [108800 1000] [1000 1000]