move to purpose-made USB cable footprint and minimum diameter vias

diff --git a/README.panel b/README.panel
new file mode 100644 (file)
index 0000000..75d4bcf
--- /dev/null
+++ b/README.panel
@@ -0,0 +1,4 @@
+$ ./pcb2panel board1.pcb board2.pcb board3.pcb > boards.pcb
+$ pcb boards.pcb
+$ ./panel2pcb boards.pcb
+$ pcb boards.panel.pcb

diff --git a/panel.pl b/panel.pl
new file mode 100644 (file)
index 0000000..fc482b2
--- /dev/null
+++ b/panel.pl
@@ -0,0 +1,100 @@
+#!/usr/bin/perl
+# -*- perl -*-
+
+# Copyright 2006 DJ Delorie <dj@delorie.com>
+# Released under the terms of the GNU General Public License, version 2
+
+sub baseboard {
+    my ($file, $width, $height, $nbase) = @_;
+    if (! $nbase) {
+       $base = $file;
+       $base =~ s@.*/@@;
+    } else {
+       $base = $nbase;
+    }
+
+    $pscript = "$base.pscript";
+    open(PS, ">$pscript");
+    push(@files_to_remove, "$base.pscript");
+
+    open(S, $file) || die("$file: $!");
+    $outname = "$base.panel.pcb";
+    $outname =~ s/pnl\.panel\.pcb/pcb/;
+    open(O, ">$outname");
+    while (<S>) {
+       if (/PCB\[.* (\d+) (\d+)\]/) {
+           s/ (\d+) (\d+)\]/ $width $height\]/;
+       }
+       s/Cursor\[.*\]/Cursor[0 0 0.0]/;
+       next if /\b(Via|Pin|Pad|ElementLine|Line|Arc|ElementArc|Text)/;
+       if (/Polygon|Element/) {
+           while (<S>) {
+               last if /^\s*\)\s*$/;
+           }
+           next;
+       }
+       if (/Layer/) {
+           if (@panelvias) {
+               print O @panelvias;
+               @panelvias = ();
+           }
+       }
+       print O;
+       if (/Layer/) {
+           print O scalar <S>;
+           print O @panelcopper;
+       }
+    }
+    close O;
+    close S;
+
+    print PS "LoadFrom(Layout,$outname)\n";
+
+    $ox = $oy = 0;
+}
+
+sub loadboard {
+    my ($file) = @_;
+    $seq = 1 + $seq;
+
+    open(S, $file);
+    open(O, ">temp-panel.$seq");
+    while (<S>) {
+       if (/PCB\[.* (\d+) (\d+)\]/) {
+           $width = $1;
+           $height = $2;
+       }
+       s/Cursor\[.*\]/Cursor[0 0 0.0]/;
+       print O;
+    }
+    close O;
+    close S;
+    print PS "LoadFrom(LayoutToBuffer,temp-panel.$seq)\n";
+    push(@files_to_remove, "temp-panel.$seq");
+}
+
+sub opaste {
+    $vx = $ox;
+    $vy = $oy + $height;
+    print PS "PasteBuffer(ToLayout,$ox,$oy)\n";
+    $ox += $width;
+    $oy = 0;
+}
+
+sub vpaste {
+    print PS "PasteBuffer(ToLayout,$vx,$vy)\n";
+    $vy += $height;
+}
+
+sub done {
+    print PS "SaveTo(LayoutAs,$outname)\n";
+    print PS "Quit()\n";
+
+    close PS;
+
+    system "set -x; pcb --action-script $pscript";
+    #system "pcb -x ps $base.panel.pcb";
+    #unlink @files_to_remove;
+}
+
+1;

diff --git a/panel2pcb b/panel2pcb
new file mode 100755 (executable)
index 0000000..565230c
--- /dev/null
+++ b/panel2pcb
@@ -0,0 +1,93 @@
+#!/usr/bin/perl
+# -*- perl -*-
+
+# Copyright 2006 DJ Delorie <dj@delorie.com>
+# Released under the terms of the GNU General Public License, version 2
+
+if (! @ARGV) {
+    print "Usage: pcb2panel board1.pcb board2.pcb board3.pcb > boards.pcb";
+    print "Then edit boards.pcb, putting each outline where you want it\n";
+    print "and sizing the board.  Then:\n";
+    print "panel2pcb boards.pcb\n";
+    print "and edit/print boards.panel.pcb\n";
+    exit 0;
+}
+
+$mydir = $0;
+if ($mydir =~ m@/@) {
+    $mydir =~ s@[^/]*$@@;
+} else {
+    $mydir = ".";
+}
+    require "$mydir/panel.pl";
+
+$panel = shift;
+
+open(P, $panel);
+while (<P>) {
+    if (/PCB\[.* (\d+) (\d+)\]/) {
+       $panel_width = $1;
+       $panel_height = $2;
+    }
+    if (/Element\[\"[^\"]*\" \"([^\"]*)\" \"([^\"]*)\" \"([^\"]*)\" (\d+) (\d+)/) {
+       $pcb = $1;
+       $base = $2;
+       $value = $3;
+       $mx = $4;
+       $my = $5;
+       %pinx = ();
+       %piny = ();
+    }
+    if (/Pin\[([\d-]+) ([\d-]+) \d+ \d+ \d+ \d+ \"(\d)\"/) {
+       $pinx{$3} = $1;
+       $piny{$3} = $2;
+    }
+    if ($pcb && /\)/) {
+       if ($pinx{'1'} < $pinx{'2'}) {
+           $rot = 0;
+       } elsif ($pinx{'1'} > $pinx{'2'}) {
+           $rot = 2;
+       } elsif ($piny{'1'} < $piny{'2'}) {
+           $rot = 3;
+       } elsif ($piny{'1'} > $piny{'2'}) {
+           $rot = 1;
+       }
+       push (@paste, "$pcb\0$rot\0$mx\0$my");
+       $pcb = undef;
+    }
+    if (/Via/) {
+       push (@panelvias, $_);
+    }
+    if (/^Layer\([^)]*\)$/) {
+       $junk = <P>; # The opening '('
+       while ($junk = <P>) {
+           last if $junk =~ /^\)/;
+           push (@panelcopper, $junk);
+       }
+    }
+}
+
+$tmp = "/tmp/panel$$.pcb";
+
+$start = $paste[0];
+$start =~ s/\0.*//;
+
+$panel =~ s/\.pcb$//;
+&baseboard($start, $panel_width, $panel_height, $panel);
+
+$lastboard = undef;
+for $paste (sort @paste) {
+    ($pcb, $rot, $mx, $my) = split(/\0/, $paste);
+    if ($lastboard ne $pcb) {
+       &loadboard ($pcb);
+       $lastboard = $pcb;
+       $lastrot = 0;
+    }
+    while ($lastrot != $rot) {
+       print PS "PasteBuffer(Rotate,1)\n";
+       $lastrot = ($lastrot+1) % 4;
+    }
+    print PS "PasteBuffer(ToLayout,$mx,$my)\n";
+}
+
+&done();

diff --git a/pcb2panel b/pcb2panel
new file mode 100755 (executable)
index 0000000..63206dc
--- /dev/null
+++ b/pcb2panel
@@ -0,0 +1,70 @@
+#!/usr/bin/perl
+# -*- perl -*-
+
+# Copyright 2006 DJ Delorie <dj@delorie.com>
+# Released under the terms of the GNU General Public License, version 2
+
+if (! @ARGV) {
+    print "Usage: pcb2panel board1.pcb board2.pcb board3.pcb > boards.pcb\n";
+    print "Then edit boards.pcb, putting each outline where you want it\n";
+    print "and sizing the board.  Then:\n";
+    print "panel2pcb boards.pcb\n";
+    print "and edit/print boards.panel.pcb\n";
+    exit 0;
+}
+
+for $pcb (@ARGV) {
+    $base = $pcb;
+    $base =~ s@.*/@@;
+    $base =~ s@\.pcb$@@;
+    $base{$pcb} = $base;
+    push (@pcbs, $pcb);
+    open(PCB, $pcb);
+    while (<PCB>) {
+       if (/^PCB\[".*" (\d+) (\d+)\]/) {
+           $width{$pcb} = $1;
+           $height{$pcb} = $2;
+           break;
+       }
+    }
+    close PCB;
+}
+
+$pw = 10000;
+$ph = 0;
+for $pcb (@pcbs) {
+    $pw += 10000;
+    $pw += $width{$pcb};
+    $ph = $height{$pcb} if $ph < $height{$pcb};
+}
+$ph += 20000;
+
+print "PCB[\"\" $pw $ph]\n";
+print "Grid[10000.0 0 0 1]\n";
+print "Groups(\"1,c:2,s\")\n";
+
+$x = 10000;
+$y = 10000;
+for $pcb (@pcbs) {
+    $desc = $pcb;
+    $name = $base{$pcb};
+    $value = "$width{$pcb} x $height{$pcb}";
+    $w = $width{$pcb};
+    $h = $height{$pcb};
+    print "Element[\"\" \"$desc\" \"$name\" \"$value\" $x $y 2000 2000 0 50 \"\"] (\n";
+    print "  Pin[0 0 300 0 0 100 \"1\" \"1\" \"\"]\n";
+    print "  Pin[$w 0 300 0 0 100 \"2\" \"2\" \"\"]\n";
+    print "  ElementLine[0 0 $w 0 100]\n";
+    print "  ElementLine[0 0 0 $h 100]\n";
+    print "  ElementLine[$w 0 $w $h 100]\n";
+    print "  ElementLine[0 $h $w $h 100]\n";
+    print ")\n";
+    $x += $w + 10000;
+}
+
+print "Layer(1 \"component\")()\n";
+print "Layer(2 \"solder\")()\n";
+print "Layer(3 \"silk\")()\n";
+print "Layer(4 \"silk\")()\n";
+
+exit 0;

diff --git a/teledongle.pcb b/teledongle.pcb
index 97cbdb4ba5a939e9d749a6a48a1df3fca4810eec..5bb3ae0ac4e3588e28b790dfd5abcb6cb841da5d 100644 (file)
--- a/teledongle.pcb
+++ b/teledongle.pcb
@@ -1,5 +1,5 @@
 # release: pcb 20091103
-# date:    Sat Jan  2 20:25:26 2010
+# date:    Tue Jan 26 22:15:53 2010
 # user:    bdale (Bdale Garbee,KB0G)
 # host:    rover
 
@@ -15,7 +15,7 @@ Thermal[0.500000]
 DRC[600 1000 600 500 1500 650]
 Flags("nameonpcb,clearnew,snappin")
 Groups("1,c:2,s:3")
-Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,24000,23600,1000:Skinny,600,2402,1181,600"]
+Styles["Signal,1000,3000,1500,1000:Power,2500,6000,3500,1000:Fat,4000,24000,23600,1000:Skinny,600,2402,1181,600"]
 
 Symbol(' ' 18)
 (
@@ -801,37 +801,36 @@ Via[45200 13100 3600 2000 0 2000 "" "thermal(1X)"]
 Via[70700 74000 3600 2000 0 2000 "" "thermal(1X)"]
 Via[45200 3100 3600 2000 0 2000 "" "thermal(1X)"]
 Via[65200 3100 3600 2000 0 2000 "" "thermal(1X)"]
-Via[70600 50800 3600 2000 0 2000 "" "thermal(1X)"]
+Via[79700 32600 3000 2000 0 1500 "" "thermal(1X)"]
 Via[84400 77000 3600 2000 0 2000 "" "thermal(1X)"]
-Via[14400 71600 3600 2000 0 2000 "" ""]
-Via[46100 24300 3600 2000 0 2000 "" "thermal(1X)"]
-Via[51800 87800 3600 2000 0 2000 "" ""]
-Via[80100 92000 3600 2000 0 2000 "" ""]
-Via[70900 97000 3600 2000 0 2000 "" "thermal(1X)"]
-Via[81300 69100 3600 2000 0 2000 "" ""]
-Via[75900 87800 3600 2000 0 2000 "" ""]
-Via[20600 87300 3600 2000 0 2000 "" ""]
-Via[86700 63200 3600 2000 0 2000 "" ""]
-Via[56800 81000 3600 2000 0 2000 "" ""]
+Via[31300 67200 3000 2000 0 1500 "" ""]
+Via[29000 52000 3000 2000 0 1500 "" "thermal(1X)"]
+Via[88800 86100 3000 2000 0 1500 "" ""]
+Via[55800 47900 3000 2000 0 1500 "" ""]
+Via[75100 91300 3000 2000 0 1500 "" "thermal(0X,1X)"]
+Via[86700 63200 3000 2000 0 1500 "" ""]
+Via[48000 49800 3000 2000 0 1500 "" ""]
+Via[56800 81600 3000 2000 0 1500 "" ""]
+Via[74900 56500 3000 2000 0 1500 "" ""]
+Via[45200 88800 3000 2000 0 1500 "" ""]
 Via[65200 13100 3600 2000 0 2000 "" "thermal(1X)"]
-Via[36800 82600 3600 2000 0 2000 "" "thermal(1X)"]
-Via[41500 78300 3600 2000 0 2000 "" ""]
-Via[12600 78300 3600 2000 0 2000 "" ""]
-Via[23000 75100 3600 2000 0 2000 "" ""]
-Via[79600 32600 3600 2000 0 2000 "" "thermal(1X)"]
-Via[37600 75100 3600 2000 0 2000 "" ""]
-Via[37600 70800 3600 2000 0 2000 "" ""]
-Via[27400 74800 3600 2000 0 2000 "" "thermal(0X,1X)"]
-Via[30800 67100 3600 2000 0 2000 "" ""]
-Via[42900 41400 3600 2000 0 2000 "" "thermal(1X)"]
-Via[74900 56400 3600 2000 0 2000 "" ""]
-Via[39700 53700 3600 2000 0 2000 "" ""]
-Via[47900 49900 3600 2000 0 2000 "" ""]
-Via[29000 51900 3600 2000 0 2000 "" "thermal(0X,1X)"]
-Via[55800 47200 3600 2000 0 2000 "" ""]
-Via[59300 39600 3600 2000 0 2000 "" "thermal(1X)"]
-Via[41100 90800 3600 2000 0 2000 "" ""]
-Via[91100 86000 3600 2000 0 2000 "" ""]
+Via[27500 74700 3000 2000 0 1500 "" "thermal(1X)"]
+Via[36800 82600 3000 2000 0 1500 "" "thermal(0X,1X)"]
+Via[14500 71600 3000 2000 0 1500 "" ""]
+Via[20600 87300 3000 2000 0 1500 "" ""]
+Via[59600 39400 3000 2000 0 1500 "" "thermal(1X)"]
+Via[41600 78300 3000 2000 0 1500 "" ""]
+Via[57000 89300 3000 2000 0 1500 "" ""]
+Via[23200 75000 3000 2000 0 1500 "" ""]
+Via[37700 70800 3000 2000 0 1500 "" ""]
+Via[45800 24200 3000 2000 0 1500 "" "thermal(0X,1X)"]
+Via[70700 50900 3000 2000 0 1500 "" "thermal(1X)"]
+Via[40200 41400 3000 2000 0 1500 "" "thermal(1X)"]
+Via[39600 53800 3000 2000 0 1500 "" ""]
+Via[12600 78300 3000 2000 0 1500 "" ""]
+Via[75100 87400 3000 2000 0 1500 "" ""]
+Via[37700 75000 3000 2000 0 1500 "" ""]
+Via[81400 69100 3000 2000 0 1500 "" ""]
 
 Element["" "0402" "C23" "8.2pF" 50174 26893 -15172 -3129 0 100 ""]
 (
@@ -854,10 +853,10 @@ Element["" "0402" "C12" "0.1uF" 42201 82587 -6161 872 0 100 ""]
 
        )
 
-Element["" "0402" "R6" "1.5k" 81500 87600 6958 -3091 3 100 ""]
+Element["" "0402" "R6" "1.5k" 93300 86100 -2791 742 0 100 ""]
 (
-       Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"]
-       Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"]
+       Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"]
+       Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"]
 
        )
 
@@ -868,7 +867,7 @@ Element["" "0402" "R13" "270" 51768 82254 3958 2991 3 100 ""]
 
        )
 
-Element["" "0402" "R7" "33" 56807 87774 2530 -10291 3 100 ""]
+Element["" "0402" "R7" "33" 61207 87726 2630 -9391 3 100 ""]
 (
        Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"]
        Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"]
@@ -895,7 +894,7 @@ Element["" "0402" "L4" "27nH" 49821 36326 -1948 -5677 3 100 ""]
 
        )
 
-Element["" "QFN36" "U9" "CC1111" 52880 63980 0 0 0 100 ""]
+Element["" "QFN36" "U9" "CC1111" 52880 63980 13360 -4240 0 100 ""]
 (
        Pin[-5919 -5919 2800 1000 0 1500 "GND Exposed" "37" "via,thermal(1X)"]
        Pin[0 -5919 2800 1000 0 1500 "GND Exposed" "37" "via,thermal(1X)"]
@@ -1002,7 +1001,7 @@ Element["" "0402" "C30" "22pF" 75074 32293 -4557 -6958 0 100 ""]
 
        )
 
-Element["" "0603diode" "D2" "red" 75392 94241 2957 5576 3 100 ""]
+Element["" "0603diode" "D2" "red" 79000 89400 2757 5876 3 100 ""]
 (
        Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "square"]
        Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "square"]
@@ -1029,20 +1028,6 @@ Element["" "ABM8" "X1" "48mhz" 75158 41765 -3600 -3169 0 100 ""]
 
        )
 
-Element["" "530470510" "J5" "USBcable" 39752 91472 800 6100 0 100 ""]
-(
-       Pin[5906 4528 3500 600 4100 2047 "GND" "5" "edge2,thermal(0X,1X)"]
-       Pin[10827 4528 3500 600 4100 2047 "HS" "4" "edge2,thermal(1X)"]
-       Pin[15748 4528 3500 600 4100 2047 "DATA+" "3" "edge2"]
-       Pin[20669 4528 3500 600 4100 2047 "DATA-" "2" "edge2"]
-       Pin[25591 4528 3500 600 4100 2047 "VBUS" "1" "square,edge2"]
-       ElementLine [31496 0 0 0 600]
-       ElementLine [31496 12598 31496 0 600]
-       ElementLine [0 12598 31496 12598 600]
-       ElementLine [0 0 0 12598 600]
-
-       )
-
 Element["" "0402" "R12" "270" 48068 82254 2858 2891 3 100 ""]
 (
        Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"]
@@ -1150,7 +1135,7 @@ Element["" "0402" "C2" "47pF" 67807 76974 3158 -10491 3 100 ""]
 
        )
 
-Element["" "0402" "C5" "1uF" 81393 80274 -944 -2291 3 100 ""]
+Element["" "0402" "C5" "1uF" 81393 80274 -944 -1691 3 100 ""]
 (
        Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"]
        Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"]
@@ -1171,21 +1156,21 @@ Element["" "0402" "L3" "27nH" 55207 25626 2314 -2895 0 100 ""]
 
        )
 
-Element["" "0402" "R8" "33" 61307 87826 2914 -10295 3 100 ""]
+Element["" "0402" "R8" "33" 65007 87726 3314 -9195 3 100 ""]
 (
        Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"]
        Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"]
 
        )
 
-Element["" "0402" "C37" "1uF" 81393 73526 -1063 -6110 3 100 ""]
+Element["" "0402" "C37" "1uF" 81393 73526 -1063 -6710 3 100 ""]
 (
        Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"]
        Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"]
 
        )
 
-Element["" "0603diode" "D1" "green" 31792 94341 3090 6109 3 100 ""]
+Element["" "0603diode" "D1" "green" 32192 89441 3090 6109 3 100 ""]
 (
        Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "square"]
        Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "square"]
@@ -1202,14 +1187,14 @@ Element["" "0402" "C28" "0.1uF" 55993 43574 6871 -1572 3 100 ""]
 
        )
 
-Element["" "0402" "C9" "0.1uF" 47693 45926 -4687 -1831 3 100 ""]
+Element["" "0402" "C9" "0.1uF" 47593 44126 -7801 -2583 3 100 ""]
 (
        Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"]
        Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"]
 
        )
 
-Element["" "0402" "R16" "56k" 43907 45926 -5566 -3395 3 100 ""]
+Element["" "0402" "R16" "56k" 43407 44226 -5566 -3395 3 100 ""]
 (
        Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"]
        Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"]
@@ -1263,16 +1248,26 @@ Element["" "0402" "L1" "27nH" 59288 35345 -693 -7055 0 100 ""]
        Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"]
        Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"]
 
+       )
+
+Element["" "usbcable" "J5" "USBcable" 72500 97600 -36975 4770 0 100 ""]
+(
+       Pin[0 0 6250 3000 6250 3800 "1" "1" "square,edge2"]
+       Pin[-7500 0 6250 3000 6250 3800 "2" "2" "edge2"]
+       Pin[-15000 0 6250 3000 6250 3800 "3" "3" "edge2"]
+       Pin[-22500 0 6250 3000 6250 3800 "4" "4" "edge2,thermal(0X,1X)"]
+       Pin[-31500 0 8700 3000 8700 6250 "5" "5" "edge2,thermal(1X)"]
+
        )
 Layer(1 "top")
 (
-       Line[25100 99800 28700 103400 1000 2000 "clearline"]
+       Line[56386 42000 56900 42000 1000 2000 "clearline"]
        Line[3800 78600 8900 83700 1000 2000 "clearline"]
        Line[64730 60044 80056 60044 1000 2000 "clearline"]
        Line[67193 56107 67200 56100 1000 2000 "clearline"]
        Line[64730 65949 66951 65949 1000 2000 "clearline"]
-       Line[47675 83828 47675 89425 1000 2000 "clearline"]
-       Line[65300 96043 65343 96000 1000 2000 "clearline"]
+       Line[63466 35738 63800 35404 1000 2000 "clearline"]
+       Line[48000 49500 48000 46500 1000 2000 "clearline"]
        Line[67100 49986 69786 49986 1000 2000 "clearline"]
        Line[76748 50914 76748 48837 1000 2000 "clearline"]
        Line[76748 48837 78800 46785 1000 2000 "clearline"]
@@ -1291,9 +1286,9 @@ Layer(1 "top")
        Line[62100 50200 63738 50200 1000 2000 "clearline"]
        Line[50912 75830 50912 80531 1000 2000 "clearline"]
        Line[41031 58075 39075 58075 1000 2000 "clearline"]
-       Line[48944 75830 48944 81297 1000 2000 "clearline"]
+       Line[48944 75830 48944 81097 1000 2000 "clearline"]
        Line[39075 58075 37100 56100 1000 2000 "clearline"]
-       Line[99800 86100 100900 85000 1000 2000 "clearline"]
+       Line[99800 86000 100900 85000 1000 2000 "clearline"]
        Line[40607 82500 41127 81980 1000 2000 "clearline"]
        Line[46975 75830 46975 77266 1000 2000 "clearline"]
        Line[46975 77266 44261 79980 1000 2000 "clearline"]
@@ -1346,18 +1341,18 @@ Layer(1 "top")
        Line[86552 81848 87500 80900 1000 2000 "clearline"]
        Line[81000 81848 86552 81848 1000 2000 "clearline"]
        Line[81300 69100 81300 71466 1000 2000 "clearline"]
-       Line[43100 41200 42900 41400 1000 2000 "clearline"]
+       Line[45007 52131 44931 52131 1000 2000 "clearline"]
        Line[81300 71466 81786 71952 1000 2000 "clearline"]
-       Line[42900 41400 42900 43738 1000 2000 "clearline"]
-       Line[25100 85500 25100 99800 1000 2000 "clearline"]
-       Line[81893 86026 99574 86026 1000 2000 "clearline"]
+       Line[11800 78300 5800 72300 1000 2000 "clearline"]
+       Line[25100 85500 25100 106700 1000 2000 "clearline"]
+       Line[77500 69900 64744 69900 1000 2000 "clearline"]
        Line[55800 45734 56386 45148 1000 2000 "clearline"]
        Line[54814 27200 51834 27200 1000 2000 "clearline"]
        Line[55300 30300 55300 27686 1000 2000 "clearline"]
        Line[54814 21128 54800 21114 1000 2000 "clearline"]
-       Line[60421 90679 61700 89400 1000 2000 "clearline"]
+       Line[80000 96800 87500 89800 1000 2000 "clearline"]
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@@ -1365,13 +1360,13 @@ Layer(1 "top")
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        Line[64730 63980 66980 63980 1000 2000 "clearline"]
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        Line[66951 65949 67000 65900 1000 2000 "clearline"]
-       Line[65300 98700 65300 96043 1000 2000 "clearline"]
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+       Line[43300 50500 43300 46086 1000 2000 "clearline"]
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        Line[73200 75400 72100 75400 1000 2000 "clearline"]
        Line[67074 50526 67000 50600 1000 2000 "clearline"]
@@ -1380,24 +1375,24 @@ Layer(1 "top")
        Line[9700 63500 27933 63500 1000 2000 "clearline"]
        Line[49428 37900 46248 37900 1000 2000 "clearline"]
        Line[54814 24052 54814 21128 1000 2000 "clearline"]
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-       Line[73400 82600 85800 82600 2500 2000 "clearline"]
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+       Line[12600 78300 11800 78300 1000 2000 "clearline"]
+       Line[74100 82600 85800 82600 2500 2000 "clearline"]
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@@ -1417,22 +1412,22 @@ Layer(1 "top")
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        Line[51800 84253 51375 83828 1000 2000 "clearline"]
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+       Line[65000 89686 64614 89300 1000 2000 "clearline"]
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-       Line[36800 82600 40247 82600 1000 2000 "clearline"]
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@@ -1440,15 +1435,15 @@ Layer(1 "top")
        Line[3700 78700 3700 55900 1000 2000 "clearline"]
        Line[3700 55900 6100 53500 1000 2000 "clearline"]
        Line[6100 53500 9700 53500 1000 2000 "clearline"]
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-       Line[81107 91193 80200 92100 1000 2000 "clearline"]
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+       Line[64744 69900 64730 69886 1000 2000 "clearline"]
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@@ -1457,9 +1452,9 @@ Layer(1 "top")
        Line[31221 56107 31200 56086 1000 2000 "clearline"]
        Line[99600 89800 103700 85700 1000 2000 "clearline"]
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@@ -1469,15 +1464,15 @@ Layer(1 "top")
        Line[39700 53700 39700 56100 1000 2000 "clearline"]
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        Line[46975 50725 47800 49900 1000 2000 "clearline"]
-       Line[47800 49900 47800 47786 1000 2000 "clearline"]
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@@ -1486,93 +1481,92 @@ Layer(1 "top")
        Line[63800 38552 60348 38552 1000 2000 "clearline"]
        Line[54052 37952 54000 37900 1000 2000 "clearline"]
        Line[50912 38598 50214 37900 1000 2000 "clearline"]
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-       Line[12600 78300 11800 78300 1000 2000 "clearline"]
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+       Line[32284 92000 35400 92000 1000 2000 "clearline"]
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+       Line[42700 91800 49000 91800 1000 2000 "clearline"]
+       Line[25100 106600 76800 106600 1000 2000 "clearline"]
 )
 Layer(2 "bottom")
 (
-       Line[39700 53700 42600 50800 1000 2000 "clearline"]
+       Line[45200 88800 45200 86600 1000 2000 "clearline"]
        Line[14600 71400 14400 71600 1000 2000 "clearline"]
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-       Line[65500 96157 65343 96000 1000 2000 "clearline"]
-       Line[42881 71854 42881 64981 1000 2000 "clearline"]
-       Line[51800 87800 76700 87800 1000 2000 "clearline"]
+       Line[9750 88400 1000 88400 600 2000 "clearline"]
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        Line[24300 63500 18200 63500 1000 2000 "clearline"]
-       Line[42881 64981 34400 56500 1000 2000 "clearline"]
+       Line[68300 87400 75100 87400 1000 2000 "clearline"]
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+       Line[37800 66600 37800 70800 1000 2000 "clearline"]
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+       Line[8600 75000 4600 71000 1000 2000 "clearline"]
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+       Line[59500 84300 62500 81300 1000 2000 "clearline"]
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-       Line[42600 50800 62400 50800 1000 2000 "clearline"]
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+       Line[45200 86600 47500 84300 1000 2000 "clearline"]
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+       Line[53900 49800 55800 47900 1000 2000 "clearline"]
        Line[74900 56400 74900 62700 1000 2000 "clearline"]
-       Line[55500 94900 58300 92100 1000 2000 "clearline"]
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-       Line[58300 92100 81000 92100 1000 2000 "clearline"]
-       Line[37600 75100 39635 75100 1000 2000 "clearline"]
+       Line[100250 21600 109000 21600 600 2000 "clearline"]
+       Line[64400 56500 55800 47900 1000 2000 "clearline"]
+       Line[88400 1000 88400 9750 600 2000 "clearline"]
+       Line[74900 56500 64400 56500 1000 2000 "clearline"]
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        Line[31000 67100 27900 67100 1000 2000 "clearline"]
-       Line[55800 47200 55800 50700 1000 2000 "clearline"]
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-       Line[88400 1000 88400 9750 600 2000 "clearline"]
-       Line[100250 21600 109000 21600 600 2000 "clearline"]
-       Line[21600 109000 21600 100250 600 2000 "clearline"]
-       Line[9750 88400 1000 88400 600 2000 "clearline"]
+       Line[47500 84300 59500 84300 1000 2000 "clearline"]
+       Line[57500 102900 57500 97600 1000 2000 "clearline"]
+       Line[88700 86100 77800 95200 1000 2000 "clearline"]
+       Line[77800 95200 77800 102900 1000 2000 "clearline"]
+       Line[77800 102900 57500 102900 1000 2000 "clearline"]
+       Line[62500 81300 69100 81300 1000 2000 "clearline"]
+       Line[57000 89300 66400 89300 1000 2000 "clearline"]
+       Line[66400 89300 68300 87400 1000 2000 "clearline"]
+       Line[34400 56400 40800 62800 1000 2000 "clearline"]
+       Line[40800 62800 40800 71900 1000 2000 "clearline"]
+       Line[40800 71900 37700 75000 1000 2000 "clearline"]
        Arc[100250 9750 11800 11800 600 2000 0 90 "clearline"]
        Arc[9750 100250 11800 11800 600 2000 180 90 "clearline"]
        Polygon("clearpoly")
@@ -1595,8 +1589,8 @@ Layer(3 "outline")
 )
 Layer(4 "silk")
 (
-       Text[81500 84800 3 100 "Licensed under the TAPR OHL" "auto"]
-       Text[68602 85100 3 100 "http://www.tapr.org/OHL" "auto"]
+       Text[108200 106300 3 100 "Licensed under the TAPR OHL" "auto"]
+       Text[101672 98788 3 100 "tapr.org/OHL" "auto"]
        Polygon("clearpoly")
        (
                [41300 49800] [27900 49800] [27900 1600] [41300 1600] 
@@ -1604,11 +1598,12 @@ Layer(4 "silk")
 )
 Layer(5 "silk")
 (
-       Text[108600 26100 3 100 "debug" ""]
+       Text[108600 25700 3 100 "debug" ""]
        Text[6400 1400 3 100 "(c) 2010 Bdale Garbee" ""]
        Text[33200 15700 3 100 "companion" ""]
-       Text[50900 97900 0 100 "usb" ""]
-       Text[108600 67300 3 100 "TeleDongle v0.1" ""]
+       Text[109000 66300 3 100 "TeleDongle v0.2" ""]
+       Text[54200 103600 0 100 "usb" ""]
+       Text[43300 100500 0 100 "B B  G  W  R" ""]
 )
 NetList()
 (