From: Bdale Garbee Date: Thu, 21 Apr 2011 17:12:27 +0000 (-0600) Subject: cts and rts need to be cross-connected between the cc1111 and the BTM-182 X-Git-Tag: fab-v0.1~7 X-Git-Url: https://git.gag.com/?p=hw%2Ftelebt;a=commitdiff_plain;h=8f88b4bd6a24283432bffd4b127571085174323d cts and rts need to be cross-connected between the cc1111 and the BTM-182 --- diff --git a/telebt.pcb b/telebt.pcb index ad06954..f8c6764 100644 --- a/telebt.pcb +++ b/telebt.pcb @@ -1,5 +1,5 @@ # release: pcb 20100929 -# date: Mon Apr 18 14:10:42 2011 +# date: Thu Apr 21 11:12:18 2011 # user: bdale (Bdale Garbee,KB0G) # host: rover @@ -9,7 +9,7 @@ FileVersion[20100606] PCB["" 291339 133858] Grid[100.000000 0 0 0] -Cursor[0 23858 0.000000] +Cursor[0 110000 0.000000] PolyArea[200000000.000000] Thermal[0.500000] DRC[600 1000 600 500 1500 650] @@ -831,7 +831,7 @@ Via[122900 94300 3000 2000 0 1500 "" "thermal(0S)"] Via[96400 76300 3000 2000 0 1500 "" ""] Via[91300 29300 3000 2000 0 1500 "" ""] Via[102200 40800 3000 2000 0 1500 "" ""] -Via[117300 47100 3000 2000 0 1500 "" ""] +Via[117200 52200 3000 2000 0 1500 "" ""] Via[117200 37900 3000 2000 0 1500 "" ""] Via[156600 99800 3000 2000 0 1500 "" ""] Via[165900 71200 3000 2000 0 1500 "" ""] @@ -1517,7 +1517,7 @@ Layer(1 "top") Line[96400 46600 102200 40800 1000 2000 "clearline"] Line[91300 29300 91300 29900 1000 2000 "clearline"] Line[91300 29900 102200 40800 1000 2000 "clearline"] - Line[117300 47100 117300 38000 1000 2000 "clearline"] + Line[232200 46700 233100 47600 1000 2000 "clearline"] Line[117300 38000 117200 37900 1000 2000 "clearline"] Line[200600 47800 200600 38500 1000 2000 "clearline"] Line[191900 56600 191900 35700 1000 2000 "clearline"] @@ -1557,7 +1557,7 @@ Layer(1 "top") Line[156600 89500 160800 85300 1000 2000 "clearline"] Line[160800 85300 160800 76300 1000 2000 "clearline"] Line[218100 46700 232200 46700 1000 2000 "clearline"] - Line[232200 46700 233100 47600 1000 2000 "clearline"] + Line[117200 37900 117200 52200 1000 2000 "clearline"] Arc[3937 3937 3937 3937 600 2000 270 90 "clearline,lock"] Arc[278543 12795 11811 11811 600 2000 0 90 "clearline,lock"] Arc[12795 121063 11811 11811 600 2000 180 90 "clearline,lock"] @@ -1598,7 +1598,7 @@ Layer(2 "bottom") Line[247594 65568 248526 66500 1000 2000 "clearline"] Line[248526 66500 248526 69526 1000 2000 "clearline"] Line[248526 69526 248100 69952 1000 2000 "clearline"] - Line[211956 57694 204594 57694 1000 2000 "clearline"] + Line[127500 68800 66900 68800 1000 2000 "clearline"] Line[248100 73100 253000 73100 1000 2000 "clearline"] Line[253000 73100 255200 75300 1000 2000 "clearline"] Line[226817 24117 215100 12400 1000 2000 "clearline"] @@ -1707,8 +1707,8 @@ Layer(2 "bottom") Line[239100 80800 242900 84600 1000 2000 "clearline"] Line[242900 84600 242900 91726 1000 2000 "clearline"] Line[242900 91726 242769 91857 1000 2000 "clearline"] - Line[204594 57694 193900 47000 1000 2000 "clearline"] - Line[193900 47000 117200 47000 1000 2000 "clearline"] + Line[66900 68800 61400 74300 1000 2000 "clearline"] + Line[233805 57694 236206 57694 1000 2000 "clearline"] Line[102200 34852 114152 34852 1000 2000 "clearline"] Line[114152 34852 117200 37900 1000 2000 "clearline"] Line[80900 10200 71500 19600 1000 2000 "clearline"] @@ -1730,11 +1730,11 @@ Layer(2 "bottom") Line[251674 56226 252100 55800 1000 2000 "clearline"] Line[263000 89400 253426 89400 2500 2000 "clearline"] Line[253426 89400 250969 91857 2500 2000 "clearline"] - Line[61500 32600 61500 24437 1000 2000 "clearline"] - Line[80400 51500 61500 32600 1000 2000 "clearline"] - Line[192800 51500 80400 51500 1000 2000 "clearline"] - Line[200963 59663 192800 51500 1000 2000 "clearline"] - Line[211956 59663 200963 59663 1000 2000 "clearline"] + Line[230152 47600 230100 47548 1000 2000 "clearline"] + Line[233100 47600 230152 47600 1000 2000 "clearline"] + Line[230100 44400 230100 41700 1000 2000 "clearline"] + Line[61400 74300 61400 81270 1000 2000 "clearline"] + Line[61400 81270 61324 81346 1000 2000 "clearline"] Line[171800 75000 174700 77900 1000 2000 "clearline"] Line[66300 24285 66324 24261 1000 2000 "clearline"] Line[119000 94500 122700 94500 1000 2000 "clearline"] @@ -1918,14 +1918,15 @@ Layer(2 "bottom") Line[235300 49800 233100 47600 1000 2000 "clearline"] Line[233805 55726 234874 55726 1000 2000 "clearline"] Line[234874 55726 235300 55300 1000 2000 "clearline"] - Line[230100 44400 230100 41700 1000 2000 "clearline"] - Line[233100 47600 230152 47600 1000 2000 "clearline"] - Line[230152 47600 230100 47548 1000 2000 "clearline"] - Line[233805 57694 236206 57694 1000 2000 "clearline"] - Line[127500 68800 66900 68800 1000 2000 "clearline"] - Line[66900 68800 61400 74300 1000 2000 "clearline"] - Line[61400 74300 61400 81270 1000 2000 "clearline"] - Line[61400 81270 61324 81346 1000 2000 "clearline"] + Line[61324 24261 61324 30924 1000 2000 "clearline"] + Line[61324 30924 79900 49500 1000 2000 "clearline"] + Line[79900 49500 197000 49500 1000 2000 "clearline"] + Line[197000 49500 205200 57700 1000 2000 "clearline"] + Line[205200 57700 211950 57700 1000 2000 "clearline"] + Line[211950 57700 211956 57694 1000 2000 "clearline"] + Line[211956 59663 202963 59663 1000 2000 "clearline"] + Line[202963 59663 195500 52200 1000 2000 "clearline"] + Line[195500 52200 117300 52200 1000 2000 "clearline"] ) Layer(3 "outline") ( @@ -2013,7 +2014,7 @@ NetList() Net("cts" "(unknown)") ( Connect("U3-8") - Connect("U9-7") + Connect("U9-8") ) Net("debug_clock" "(unknown)") ( @@ -2115,7 +2116,7 @@ NetList() ( Connect("R2-1") Connect("U3-11") - Connect("U9-8") + Connect("U9-7") ) Net("rx1" "(unknown)") ( diff --git a/telebt.sch b/telebt.sch index d663197..06487cf 100644 --- a/telebt.sch +++ b/telebt.sch @@ -1322,14 +1322,14 @@ N 54000 54800 51200 54800 4 T 51200 54900 5 10 1 1 0 0 1 netname=rts } -N 65800 47300 64500 47300 4 +N 65800 47700 64500 47700 4 { -T 64500 47400 5 10 1 1 0 0 1 +T 64500 47800 5 10 1 1 0 0 1 netname=rts } -N 64500 47700 65800 47700 4 +N 64500 47300 65800 47300 4 { -T 64500 47800 5 10 1 1 0 0 1 +T 64500 47400 5 10 1 1 0 0 1 netname=cts } C 51900 56700 1 90 0 resistor.sym