move Vlcd from the analog rail to 3.3V to minimize analog rail noise

[hw/megadongle] / megadongle.pcb

diff --git a/megadongle.pcb b/megadongle.pcb
index 7a91dc7d4ae4aa9b4c091bb66de689582aa3bb40..e31d409afdd0058896f8d8628ab30c47c3f2a7ad 100644 (file)
--- a/megadongle.pcb
+++ b/megadongle.pcb
@@ -6,7 +6,7 @@ FileVersion[20070407]
 PCB["MegaDongle" 112500 112500]
 
 Grid[100.0 0 0 0]
-Cursor[200 62000 0.000000]
+Cursor[1700 8800 0.000000]
 PolyArea[200000000.000000]
 Thermal[0.500000]
 DRC[600 1000 600 500 1500 650]
@@ -1698,7 +1698,6 @@ Layer(1 "top")
        Line[106400 39600 100102 39600 1000 2000 "clearline"]
        Line[100102 39600 99013 38511 1000 2000 "clearline"]
        Line[70122 43400 71148 43400 1000 2000 "clearline"]
-       Line[70144 47200 71148 47200 1000 2000 "clearline"]
        Line[71148 47200 73048 45300 1000 2000 "clearline"]
        Line[74748 43400 75248 43400 1000 2000 "clearline"]
        Line[74748 43400 72948 45200 1000 2000 "clearline"]
@@ -1837,6 +1836,7 @@ Layer(1 "top")
        Line[73400 87700 70000 91100 1000 2000 "clearline"]
        Line[80674 51500 80674 49426 1000 2000 "clearline"]
        Line[80674 49426 78448 47200 1000 2000 "clearline"]
+       Line[70144 47200 71148 47200 1000 2000 "clearline"]
        Polygon("")
        (
                [62300 16000] [87100 16000] [87100 1000] [62300 1000] 
@@ -1973,12 +1973,6 @@ Layer(4 "bottom")
        Line[28400 29500 28400 45500 1000 2000 "clearline"]
        Line[71363 36062 75038 36062 1000 2000 "clearline"]
        Line[75038 36062 75700 35400 1000 2000 "clearline"]
-       Line[79236 43936 79236 42636 1000 2000 "clearline"]
-       Line[79236 42636 77800 41200 1000 2000 "clearline"]
-       Line[77800 41200 71700 41200 1000 2000 "clearline"]
-       Line[71700 41200 69500 43400 1000 2000 "clearline"]
-       Line[69500 43400 69500 47800 1000 2000 "clearline"]
-       Line[69500 47800 72900 51200 1000 2000 "clearline"]
        Line[34100 71494 38694 71494 1000 2000 "clearline"]
        Line[38694 71494 43300 76100 1000 2000 "clearline"]
        Line[43300 76100 58800 76100 1000 2000 "clearline"]
@@ -2049,6 +2043,8 @@ Layer(4 "bottom")
        Line[38300 41000 36200 38900 1000 2000 "clearline"]
        Line[33962 47873 30773 47873 1000 2000 "clearline"]
        Line[30773 47873 28400 45500 1000 2000 "clearline"]
+       Line[79236 43936 74212 43936 1000 2000 "clearline"]
+       Line[74212 43936 72948 45200 1000 2000 "clearline"]
        Polygon("clearpoly")
        (
                [13700 16000] [87100 16000] [87100 1000] [13700 1000] 
@@ -2115,6 +2111,7 @@ NetList()
                Connect("U6-25")
                Connect("U6-27")
                Connect("U6-28")
+               Connect("U7-1")
                Connect("U7-19")
                Connect("U7-32")
                Connect("U7-48")
@@ -2416,7 +2413,6 @@ NetList()
                Connect("C601-1")
                Connect("C602-1")
                Connect("L600-2")
-               Connect("U7-1")
                Connect("U7-13")
        )
 )