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Bdale Garbee [Tue, 23 Nov 2010 06:13:56 +0000 (23:13 -0700)]
make sure all silk elements are within pcb outline
Bdale Garbee [Tue, 23 Nov 2010 05:37:17 +0000 (22:37 -0700)]
tweaking silk and attributes
Bdale Garbee [Thu, 18 Nov 2010 23:08:44 +0000 (16:08 -0700)]
new footprint for the IC with vias, DRC clean again
Bdale Garbee [Thu, 18 Nov 2010 18:33:41 +0000 (11:33 -0700)]
add explicit netlist connection for exposed ground pad on DFN, clean up
various attributes on the layout to ensure no conflict with LiPo connector
and lower impedance for various high-current nets
Bdale Garbee [Thu, 18 Nov 2010 15:31:11 +0000 (08:31 -0700)]
move vias outside the battery connector pads
Bdale Garbee [Thu, 11 Nov 2010 10:24:51 +0000 (03:24 -0700)]
add targets for automating outputs
Bdale Garbee [Thu, 11 Nov 2010 08:00:27 +0000 (01:00 -0700)]
fix layout name
Bdale Garbee [Thu, 11 Nov 2010 06:19:57 +0000 (23:19 -0700)]
fix DFM identified soldermask issues
Bdale Garbee [Thu, 11 Nov 2010 05:43:04 +0000 (22:43 -0700)]
tweaks based on freedfm.com output
Bdale Garbee [Fri, 5 Nov 2010 17:05:37 +0000 (11:05 -0600)]
ground prog2, fatten supply and output traces
Bdale Garbee [Fri, 5 Nov 2010 04:47:21 +0000 (22:47 -0600)]
enabling outline layer causes bogus drc errors, so leave it off
Bdale Garbee [Thu, 4 Nov 2010 22:47:57 +0000 (16:47 -0600)]
initial capture of LiPo charger
projects / hw / lipocharger / log