hw/lipocharger
12 years agoadd more attributes
Bdale Garbee [Tue, 26 Apr 2011 03:10:14 +0000 (21:10 -0600)]
add more attributes

13 years agoadd data sheet for the slide switch we're using fab-v0.2
Bdale Garbee [Fri, 22 Apr 2011 16:03:58 +0000 (10:03 -0600)]
add data sheet for the slide switch we're using

13 years agofix mask clearance on switch mounting holes, fix refdes on switch
Bdale Garbee [Fri, 22 Apr 2011 00:38:41 +0000 (18:38 -0600)]
fix mask clearance on switch mounting holes, fix refdes on switch

13 years agoswitch usb footprint for one without overhang so can reduce length to 1"
Bdale Garbee [Tue, 19 Apr 2011 08:02:52 +0000 (02:02 -0600)]
switch usb footprint for one without overhang so can reduce length to 1"

13 years agoshrink length to minimum required including USB overhang
Bdale Garbee [Tue, 19 Apr 2011 07:56:21 +0000 (01:56 -0600)]
shrink length to minimum required including USB overhang

13 years agoadd charge rate switch legends to schematic and pcb silk screen
Bdale Garbee [Thu, 10 Mar 2011 14:32:50 +0000 (07:32 -0700)]
add charge rate switch legends to schematic and pcb silk screen

13 years agoclearn DRC run except for known bug regarding outline pseudo-layer
Bdale Garbee [Thu, 10 Mar 2011 14:07:57 +0000 (07:07 -0700)]
clearn DRC run except for known bug regarding outline pseudo-layer

13 years agofirst draft of a second version
Bdale Garbee [Thu, 10 Mar 2011 05:32:35 +0000 (22:32 -0700)]
first draft of a second version

13 years agoneed a 10k resistor from the thermistor input to ground
Bdale Garbee [Thu, 10 Mar 2011 02:11:56 +0000 (19:11 -0700)]
need a 10k resistor from the thermistor input to ground

13 years agoswitch to 6.3V bulk caps!
Bdale Garbee [Mon, 6 Dec 2010 23:42:06 +0000 (16:42 -0700)]
switch to 6.3V bulk caps!

13 years agomake sure all silk elements are within pcb outline fab-v0.1
Bdale Garbee [Tue, 23 Nov 2010 06:13:56 +0000 (23:13 -0700)]
make sure all silk elements are within pcb outline

13 years agotweaking silk and attributes
Bdale Garbee [Tue, 23 Nov 2010 05:37:17 +0000 (22:37 -0700)]
tweaking silk and attributes

13 years agonew footprint for the IC with vias, DRC clean again origin/master
Bdale Garbee [Thu, 18 Nov 2010 23:08:44 +0000 (16:08 -0700)]
new footprint for the IC with vias, DRC clean again

13 years agoadd explicit netlist connection for exposed ground pad on DFN, clean up
Bdale Garbee [Thu, 18 Nov 2010 18:33:41 +0000 (11:33 -0700)]
add explicit netlist connection for exposed ground pad on DFN, clean up
various attributes on the layout to ensure no conflict with LiPo connector
and lower impedance for various high-current nets

13 years agomove vias outside the battery connector pads
Bdale Garbee [Thu, 18 Nov 2010 15:31:11 +0000 (08:31 -0700)]
move vias outside the battery connector pads

13 years agoadd targets for automating outputs
Bdale Garbee [Thu, 11 Nov 2010 10:24:51 +0000 (03:24 -0700)]
add targets for automating outputs

13 years agofix layout name
Bdale Garbee [Thu, 11 Nov 2010 08:00:27 +0000 (01:00 -0700)]
fix layout name

13 years agofix DFM identified soldermask issues
Bdale Garbee [Thu, 11 Nov 2010 06:19:57 +0000 (23:19 -0700)]
fix DFM identified soldermask issues

13 years agotweaks based on freedfm.com output
Bdale Garbee [Thu, 11 Nov 2010 05:43:04 +0000 (22:43 -0700)]
tweaks based on freedfm.com output

13 years agoground prog2, fatten supply and output traces
Bdale Garbee [Fri, 5 Nov 2010 17:05:37 +0000 (11:05 -0600)]
ground prog2, fatten supply and output traces

13 years agoenabling outline layer causes bogus drc errors, so leave it off
Bdale Garbee [Fri, 5 Nov 2010 04:47:21 +0000 (22:47 -0600)]
enabling outline layer causes bogus drc errors, so leave it off

13 years agoinitial capture of LiPo charger
Bdale Garbee [Thu, 4 Nov 2010 22:47:57 +0000 (16:47 -0600)]
initial capture of LiPo charger