summary |
shortlog | log |
commit |
commitdiff |
tree
first ⋅ prev ⋅ next
Keith Packard [Thu, 7 Mar 2024 05:44:04 +0000 (21:44 -0800)]
Reposition refdes to be semi-usable
Signed-off-by: Keith Packard <keithp@keithp.com>
Bdale Garbee [Thu, 7 Mar 2024 03:29:53 +0000 (20:29 -0700)]
Merge branch 'master' of ssh://git.gag.com/scm/git/hw/easytimer
Bdale Garbee [Thu, 7 Mar 2024 03:23:03 +0000 (20:23 -0700)]
restore refdes in silk for Seeed
Keith Packard [Mon, 4 Mar 2024 00:36:45 +0000 (16:36 -0800)]
Add .gitignore
Keith Packard [Sun, 3 Mar 2024 23:14:43 +0000 (15:14 -0800)]
Add test plan and firmware image
Signed-off-by: Keith Packard <keithp@keithp.com>
Keith Packard [Sun, 3 Mar 2024 04:42:31 +0000 (20:42 -0800)]
Remove 'noload' from beeper
Signed-off-by: Keith Packard <keithp@keithp.com>
Bdale Garbee [Thu, 29 Feb 2024 02:05:51 +0000 (19:05 -0700)]
adjust one trace on power plane, tweak clearances to get clean DRC report
Bdale Garbee [Tue, 13 Feb 2024 19:58:27 +0000 (12:58 -0700)]
shove copper to make laser-safe, drop 'p2' in silk, update copyright year
Bdale Garbee [Tue, 13 Feb 2024 19:35:14 +0000 (12:35 -0700)]
switch to the same LDO used on EasyMini, it's much cheaper and just as good
Bdale Garbee [Tue, 13 Feb 2024 19:33:36 +0000 (12:33 -0700)]
actually connect the gnd side of the bulk capacitor...
Bdale Garbee [Thu, 1 Feb 2024 06:29:44 +0000 (23:29 -0700)]
rationalize 22uF capacitor choice to pref parts, clean up metadata
Bdale Garbee [Thu, 16 Mar 2023 17:50:49 +0000 (11:50 -0600)]
be explicit about 5V pin on USB connector being a no-connect
Bdale Garbee [Thu, 16 Mar 2023 17:44:00 +0000 (11:44 -0600)]
declare p2 in the silk, tweak copper to improve DRC results
Keith Packard [Thu, 16 Mar 2023 16:58:12 +0000 (09:58 -0700)]
Shift SPI0 pins to correct alignment
SPI0 was wired to PA03 PA04 PA05 instead of PA04 PA05 PA06
Signed-off-by: Keith Packard <keithp@keithp.com>
Bdale Garbee [Mon, 6 Mar 2023 21:48:26 +0000 (16:48 -0500)]
route complete and drc clean-ish after reducing vias under chips
Bdale Garbee [Sun, 5 Mar 2023 04:23:16 +0000 (23:23 -0500)]
eliminate vias under chips with bottom copper
Bdale Garbee [Sat, 4 Mar 2023 23:59:24 +0000 (18:59 -0500)]
snapshot before working on under-samd21 vias
Bdale Garbee [Sat, 4 Mar 2023 04:06:28 +0000 (23:06 -0500)]
add explicit NC symbols on schematic, 'p1' in silk on board
Bdale Garbee [Fri, 3 Mar 2023 22:34:54 +0000 (17:34 -0500)]
route complete, could use copper tweaking
Bdale Garbee [Thu, 23 Feb 2023 12:16:00 +0000 (05:16 -0700)]
work in progress
Bdale Garbee [Tue, 21 Feb 2023 06:33:02 +0000 (23:33 -0700)]
working on layout .. much left to do
Bdale Garbee [Tue, 7 Feb 2023 05:01:10 +0000 (22:01 -0700)]
first cut at pulling v2 parts together
Bdale Garbee [Wed, 7 Dec 2022 19:06:35 +0000 (12:06 -0700)]
work in progress
Bdale Garbee [Mon, 7 Nov 2022 20:12:02 +0000 (13:12 -0700)]
forward annotate additional bypass caps, etc, to incomplete pcb layout
Bdale Garbee [Mon, 7 Nov 2022 20:08:26 +0000 (13:08 -0700)]
add bypass caps for 3.3V rail, and fix VDDCORE connection
Bdale Garbee [Fri, 30 Sep 2022 04:56:13 +0000 (22:56 -0600)]
work in process
Bdale Garbee [Sun, 3 Jul 2022 05:27:24 +0000 (23:27 -0600)]
use IMU parts we can actually get
Bdale Garbee [Sun, 3 Jul 2022 00:31:03 +0000 (18:31 -0600)]
add smaller logo, adjust debug connector and beeper locations
Bdale Garbee [Sun, 3 Jul 2022 00:12:27 +0000 (18:12 -0600)]
remove large logo from silk, etc
Bdale Garbee [Sat, 18 Jun 2022 19:44:52 +0000 (15:44 -0400)]
switch cpu to SAMD21 parts we have in stock
Bdale Garbee [Sat, 18 Jun 2022 19:20:10 +0000 (15:20 -0400)]
add flash part from TeleMini to schematic
Bdale Garbee [Fri, 30 Oct 2020 05:02:16 +0000 (23:02 -0600)]
fix corner of outline polygon to have lines actually intersect
Bdale Garbee [Sat, 19 Sep 2020 20:07:06 +0000 (14:07 -0600)]
bulk cap in LDO circuit is actually a 1206
Bdale Garbee [Fri, 18 Sep 2020 19:49:47 +0000 (13:49 -0600)]
rationalize screw terminal strip values in pref parts
Bdale Garbee [Thu, 28 May 2020 21:21:29 +0000 (15:21 -0600)]
forward annotate attributes cleanup
Bdale Garbee [Mon, 18 May 2020 20:53:42 +0000 (14:53 -0600)]
let attribs be automatically handled
Bdale Garbee [Mon, 4 May 2020 21:09:25 +0000 (15:09 -0600)]
mark all through-hole parts as noload
Bdale Garbee [Fri, 10 Apr 2020 17:30:20 +0000 (11:30 -0600)]
eliminate duplicate footprint attribute, which fortunately didn't kill us
Bdale Garbee [Fri, 10 Jan 2020 16:43:17 +0000 (09:43 -0700)]
update EasyTimer for 2020 copyright and add slots for USB in outline layer
Bdale Garbee [Wed, 13 Nov 2019 23:21:46 +0000 (16:21 -0700)]
circuit complete, layout passes DRC
Bdale Garbee [Wed, 13 Nov 2019 07:53:23 +0000 (00:53 -0700)]
route nearly complete, just bypass caps left to place
Bdale Garbee [Wed, 13 Nov 2019 00:45:23 +0000 (17:45 -0700)]
move to BMX160 IMU
Bdale Garbee [Thu, 31 Oct 2019 18:21:37 +0000 (12:21 -0600)]
change schematic to say 'v1' to match artwork .. single digit fits silk better
Bdale Garbee [Thu, 31 Oct 2019 18:19:03 +0000 (12:19 -0600)]
switch to the same cpu variant at TeleMetrum, a bit of layout work
Bdale Garbee [Tue, 6 Aug 2019 23:15:31 +0000 (17:15 -0600)]
move to STM32L151 to have enough flash and EEPROM so can drop flash
Bdale Garbee [Tue, 6 Aug 2019 16:52:37 +0000 (10:52 -0600)]
initial capture of a potential EasyTimer design
projects / hw / easytimer / log