add bypass caps for 3.3V rail, and fix VDDCORE connection

diff --git a/easytimer.sch b/easytimer.sch
index dd6edb4226aed6c87f7c6e62622fe42b914b5917..76003144b3b9d93d509d214d9d5f322f5975867f 100644 (file)
--- a/easytimer.sch
+++ b/easytimer.sch
@@ -755,8 +755,6 @@ N 15000 37700 15000 37200 4
 N 15000 37200 15300 37200 4
 N 15000 37700 15300 37700 4
 N 16400 37700 16200 37700 4
-N 16100 36300 16400 36300 4
-N 16400 36300 16400 35100 4
 C 24700 26000 1 180 1 conn-4.sym
 {
 T 24700 26000 5 10 0 0 180 6 1
@@ -1150,4 +1148,65 @@ T 14800 28800 5 10 1 1 0 0 1
 refdes=U8
 }
 C 16200 38900 1 0 0 3.3V-plus.sym
-C 15900 36300 1 0 0 3.3V-plus.sym
+N 16400 36300 12500 36300 4
+C 12300 36300 1 0 0 3.3V-plus.sym
+C 12700 35400 1 90 0 capacitor.sym
+{
+T 12000 35600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 11800 35600 5 10 0 0 90 0 1
+symversion=0.1
+T 12700 35400 5 10 0 0 0 0 1
+footprint=0402
+T 12400 36000 5 10 1 1 0 6 1
+refdes=C110
+T 12400 35600 5 10 1 1 0 6 1
+value=0.1uF
+}
+C 13600 35400 1 90 0 capacitor.sym
+{
+T 12900 35600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 12700 35600 5 10 0 0 90 0 1
+symversion=0.1
+T 13600 35400 5 10 0 0 0 0 1
+footprint=0402
+T 13300 36000 5 10 1 1 0 6 1
+refdes=C111
+T 13300 35600 5 10 1 1 0 6 1
+value=0.1uF
+}
+C 14500 35400 1 90 0 capacitor.sym
+{
+T 13800 35600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 13600 35600 5 10 0 0 90 0 1
+symversion=0.1
+T 14500 35400 5 10 0 0 0 0 1
+footprint=0402
+T 14200 36000 5 10 1 1 0 6 1
+refdes=C112
+T 14200 35600 5 10 1 1 0 6 1
+value=0.1uF
+}
+N 12500 35400 14700 35400 4
+C 12400 35100 1 0 0 gnd.sym
+C 15600 35200 1 0 1 capacitor.sym
+{
+T 15400 35900 5 10 0 0 0 6 1
+device=CAPACITOR
+T 15400 36100 5 10 0 0 0 6 1
+symversion=0.1
+T 15600 35200 5 10 0 1 0 6 1
+footprint=0402
+T 15700 35500 5 10 1 1 0 6 1
+refdes=C113
+T 15000 35500 5 10 1 1 0 6 1
+value=1uF
+}
+N 16400 35900 16200 35900 4
+N 16200 35100 16200 36300 4
+N 16400 35100 16200 35100 4
+N 16400 35500 15900 35500 4
+N 15600 35400 15900 35400 4
+N 15900 35400 15900 35500 4