circuit complete, layout passes DRC
authorBdale Garbee <bdale@gag.com>
Wed, 13 Nov 2019 23:21:46 +0000 (16:21 -0700)
committerBdale Garbee <bdale@gag.com>
Wed, 13 Nov 2019 23:21:46 +0000 (16:21 -0700)
commit639c3140850b74ea6dd7ff7f84045df6ee489f65
tree3587ff9e00b4b7bcefc9a8cada0c73acdadafd6a
parent141daedc73a25ba6683487f3567001ef1c8c90c8
circuit complete, layout passes DRC
easytimer.lht
easytimer.sch