From: Bdale Garbee Date: Thu, 5 Dec 2013 08:11:16 +0000 (-0700) Subject: initial checking of stripped-down TeleMega design X-Git-Tag: fab-0.1~12 X-Git-Url: https://git.gag.com/?p=hw%2Feasymega;a=commitdiff_plain;h=64af3927b971a140e4f6fbce14e97e05f3a78e50 initial checking of stripped-down TeleMega design --- 64af3927b971a140e4f6fbce14e97e05f3a78e50 diff --git a/License.pdf b/License.pdf new file mode 100644 index 0000000..01fceb2 Binary files /dev/null and b/License.pdf differ diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..3ae477a --- /dev/null +++ b/Makefile @@ -0,0 +1,65 @@ +PROJECT=easymega +AM=../altusmetrum +SCHEME=$(AM)/scheme + +# intentionally want to rebuild drc and bom on every invocation +all: drc partslist partslist.csv pcb + +drc: $(PROJECT).sch Makefile + -gnetlist -g drc2 $(PROJECT).sch -o $(PROJECT).drc + +partslist: $(PROJECT).sch Makefile + gnetlist -g bom -o $(PROJECT).unsorted $(PROJECT).sch + head -n1 $(PROJECT).unsorted > partslist + tail -n+2 $(PROJECT).unsorted | sort >> partslist + rm -f $(PROJECT).unsorted + +partslist.csv: $(PROJECT).sch Makefile + gnetlist -L $(SCHEME) -g partslistgag -o $(PROJECT).csvtmp $(PROJECT).sch + (head -n1 $(PROJECT).csvtmp; tail -n+2 $(PROJECT).csvtmp | sort -t \, -k 8) > $@ && rm -f $(PROJECT).csvtmp + + +partslist.dk: $(PROJECT).sch Makefile $(SCHEME)/gnet-partslist-bom.scm + gnetlist -L $(SCHEME) -g partslist-bom -Ovendor=digikey -o $@ $(PROJECT).sch + +partslist.mouser: $(PROJECT).sch Makefile $(SCHEME)/gnet-partslist-bom.scm + gnetlist -L $(SCHEME) -g partslist-bom -Ovendor=mouser -o $@ $(PROJECT).sch + +pcb: $(PROJECT).sch project Makefile + gsch2pcb project + +$(PROJECT).xy: $(PROJECT).pcb + pcb -x bom $(PROJECT).pcb + +$(PROJECT).bottom.gbr: $(PROJECT).pcb + pcb -x gerber $(PROJECT).pcb + +zip: $(PROJECT).bottom.gbr $(PROJECT).bottommask.gbr $(PROJECT).fab.gbr $(PROJECT).top.gbr $(PROJECT).topmask.gbr $(PROJECT).toppaste.gbr $(PROJECT).topsilk.gbr $(PROJECT).group2.gbr $(PROJECT).group3.gbr $(PROJECT).plated-drill.cnc $(PROJECT).xy Makefile # $(PROJECT).xls + zip $(PROJECT).zip $(PROJECT).*.gbr $(PROJECT).*.cnc $(PROJECT).xy # $(PROJECT).xls + +oshpark: $(PROJECT).bottom.gbr $(PROJECT).bottommask.gbr $(PROJECT).top.gbr $(PROJECT).topmask.gbr $(PROJECT).topsilk.gbr $(PROJECT).plated-drill.cnc + mv $(PROJECT).bottom.gbr bottom\ layer.ger + mv $(PROJECT).bottommask.gbr bottom\ solder\ mask.ger + mv $(PROJECT).bottomsilk.gbr bottom\ silk\ screen.ger + mv $(PROJECT).outline.gbr board\ outline.ger + mv $(PROJECT).top.gbr top\ layer.ger + mv $(PROJECT).topmask.gbr top\ solder\ mask.ger + mv $(PROJECT).topsilk.gbr top\ silk\ screen.ger + mv $(PROJECT).plated-drill.cnc drills.xln + mv $(PROJECT).group2.gbr internal\ plane\ 1.ger + mv $(PROJECT).group3.gbr internal\ plane\ 2.ger + zip $(PROJECT)-oshpark.zip *.ger *.xln + +stencil: $(PROJECT).bottom.gbr $(PROJECT).toppaste.gbr $(PROJECT).outline.gbr + zip $(PROJECT)-stencil.zip $(PROJECT).toppaste.gbr $(PROJECT).outline.gbr + +clean: + rm -f *.bom *.drc *.log *~ $(PROJECT).ps *.gbr *.cnc *bak* *- *.zip + rm -f *.net *.xy *.cmd *.png partslist partslist.csv *.ger *.xln + rm -f *.partslist *.new.pcb *.unsorted $(PROJECT).xls muffin-5267.pdf + +muffins: partslist.csv $(AM)/glabels/muffin-short-5267.glabels + glabels-3-batch $(AM)/glabels/muffin-short-5267.glabels \ + -i partslist.csv -o muffin-5267.ps >/dev/null && \ + ps2pdf muffin-5267.ps && rm muffin-5267.ps + diff --git a/attribs b/attribs new file mode 100644 index 0000000..92a91e7 --- /dev/null +++ b/attribs @@ -0,0 +1,6 @@ +value +vendor +vendor_part_number +footprint +loadstatus +device diff --git a/easymega.pcb b/easymega.pcb new file mode 100644 index 0000000..e103943 --- /dev/null +++ b/easymega.pcb @@ -0,0 +1,3882 @@ +# release: pcb 20110918 + +# To read pcb files, the pcb version (or the git source date) must be >= the file version +FileVersion[20070407] + +PCB["TeleMega" 325000 125000] + +Grid[100.0 0 0 0] +Cursor[0 9400 0.000000] +PolyArea[200000000.000000] +Thermal[0.500000] +DRC[600 1000 600 500 1500 700] +Flags("showdrc,nameonpcb,clearnew,snappin,liveroute,hidenames") +Groups("1,c:4,s:2:3:5") +Styles["Signal,1000,800,400,800:Power,2500,800,400,1000:Fat,4000,800,400,1000:Medium,1500,800,400,600"] + +Symbol[' ' 1800] +( +) +Symbol['!' 1200] +( + SymbolLine[0 4500 0 5000 800] + SymbolLine[0 1000 0 3500 800] +) +Symbol['"' 1200] +( + SymbolLine[0 1000 0 2000 800] + SymbolLine[1000 1000 1000 2000 800] +) +Symbol['#' 1200] +( + SymbolLine[0 3500 2000 3500 800] + SymbolLine[0 2500 2000 2500 800] + SymbolLine[1500 2000 1500 4000 800] + SymbolLine[500 2000 500 4000 800] +) +Symbol['$' 1200] +( + SymbolLine[1500 1500 2000 2000 800] + SymbolLine[500 1500 1500 1500 800] + SymbolLine[0 2000 500 1500 800] + SymbolLine[0 2000 0 2500 800] + SymbolLine[0 2500 500 3000 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 2000 4000 800] + SymbolLine[1500 4500 2000 4000 800] + SymbolLine[500 4500 1500 4500 800] + SymbolLine[0 4000 500 4500 800] + SymbolLine[1000 1000 1000 5000 800] +) +Symbol['%' 1200] +( + SymbolLine[0 1500 0 2000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1000 1000 800] + SymbolLine[1000 1000 1500 1500 800] + SymbolLine[1500 1500 1500 2000 800] + SymbolLine[1000 2500 1500 2000 800] + SymbolLine[500 2500 1000 2500 800] + SymbolLine[0 2000 500 2500 800] + SymbolLine[0 5000 4000 1000 800] + SymbolLine[3500 5000 4000 4500 800] + SymbolLine[4000 4000 4000 4500 800] + SymbolLine[3500 3500 4000 4000 800] + SymbolLine[3000 3500 3500 3500 800] + SymbolLine[2500 4000 3000 3500 800] + SymbolLine[2500 4000 2500 4500 800] + SymbolLine[2500 4500 3000 5000 800] + SymbolLine[3000 5000 3500 5000 800] +) +Symbol['&' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 1500 0 2500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 3500 1500 2000 800] + SymbolLine[500 5000 1000 5000 800] + SymbolLine[1000 5000 2000 4000 800] + SymbolLine[0 2500 2500 5000 800] + SymbolLine[500 1000 1000 1000 800] + SymbolLine[1000 1000 1500 1500 800] + SymbolLine[1500 1500 1500 2000 800] + SymbolLine[0 3500 0 4500 800] +) +Symbol[''' 1200] +( + SymbolLine[0 2000 1000 1000 800] +) +Symbol['(' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 1500 0 4500 800] +) +Symbol[')' 1200] +( + SymbolLine[0 1000 500 1500 800] + SymbolLine[500 1500 500 4500 800] + SymbolLine[0 5000 500 4500 800] +) +Symbol['*' 1200] +( + SymbolLine[0 2000 2000 4000 800] + SymbolLine[0 4000 2000 2000 800] + SymbolLine[0 3000 2000 3000 800] + SymbolLine[1000 2000 1000 4000 800] +) +Symbol['+' 1200] +( + SymbolLine[0 3000 2000 3000 800] + SymbolLine[1000 2000 1000 4000 800] +) +Symbol[',' 1200] +( + SymbolLine[0 6000 1000 5000 800] +) +Symbol['-' 1200] +( + SymbolLine[0 3000 2000 3000 800] +) +Symbol['.' 1200] +( + SymbolLine[0 5000 500 5000 800] +) +Symbol['/' 1200] +( + SymbolLine[0 4500 3000 1500 800] +) +Symbol['0' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4000 2000 2000 800] +) +Symbol['1' 1200] +( + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1000 1000 1000 5000 800] + SymbolLine[0 2000 1000 1000 800] +) +Symbol['2' 1200] +( + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 2000 1000 800] + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[2500 1500 2500 2500 800] + SymbolLine[0 5000 2500 2500 800] + SymbolLine[0 5000 2500 5000 800] +) +Symbol['3' 1200] +( + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 3000 2000 3000 800] +) +Symbol['4' 1200] +( + SymbolLine[0 3000 2000 1000 800] + SymbolLine[0 3000 2500 3000 800] + SymbolLine[2000 1000 2000 5000 800] +) +Symbol['5' 1200] +( + SymbolLine[0 1000 2000 1000 800] + SymbolLine[0 1000 0 3000 800] + SymbolLine[0 3000 500 2500 800] + SymbolLine[500 2500 1500 2500 800] + SymbolLine[1500 2500 2000 3000 800] + SymbolLine[2000 3000 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4500 500 5000 800] +) +Symbol['6' 1200] +( + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[0 3000 1500 3000 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[2000 3500 2000 4500 800] +) +Symbol['7' 1200] +( + SymbolLine[0 5000 2500 2500 800] + SymbolLine[2500 1000 2500 2500 800] + SymbolLine[0 1000 2500 1000 800] +) +Symbol['8' 1200] +( + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 3500 0 4500 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 2500 500 3000 800] + SymbolLine[0 1500 0 2500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 2500 800] + SymbolLine[1500 3000 2000 2500 800] +) +Symbol['9' 1200] +( + SymbolLine[0 5000 2000 3000 800] + SymbolLine[2000 1500 2000 3000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 1500 0 2500 800] + SymbolLine[0 2500 500 3000 800] + SymbolLine[500 3000 2000 3000 800] +) +Symbol[':' 1200] +( + SymbolLine[0 2500 500 2500 800] + SymbolLine[0 3500 500 3500 800] +) +Symbol[';' 1200] +( + SymbolLine[0 5000 1000 4000 800] + SymbolLine[1000 2500 1000 3000 800] +) +Symbol['<' 1200] +( + SymbolLine[0 3000 1000 2000 800] + SymbolLine[0 3000 1000 4000 800] +) +Symbol['=' 1200] +( + SymbolLine[0 2500 2000 2500 800] + SymbolLine[0 3500 2000 3500 800] +) +Symbol['>' 1200] +( + SymbolLine[0 2000 1000 3000 800] + SymbolLine[0 4000 1000 3000 800] +) +Symbol['?' 1200] +( + SymbolLine[1000 3000 1000 3500 800] + SymbolLine[1000 4500 1000 5000 800] + SymbolLine[0 1500 0 2000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 2000 800] + SymbolLine[1000 3000 2000 2000 800] +) +Symbol['@' 1200] +( + SymbolLine[0 1000 0 4000 800] + SymbolLine[0 4000 1000 5000 800] + SymbolLine[1000 5000 4000 5000 800] + SymbolLine[5000 3500 5000 1000 800] + SymbolLine[5000 1000 4000 0 800] + SymbolLine[4000 0 1000 0 800] + SymbolLine[1000 0 0 1000 800] + SymbolLine[1500 2000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 3000 3500 800] + SymbolLine[3000 3500 3500 3000 800] + SymbolLine[3500 3000 4000 3500 800] + SymbolLine[3500 3000 3500 1500 800] + SymbolLine[3500 2000 3000 1500 800] + SymbolLine[2000 1500 3000 1500 800] + SymbolLine[2000 1500 1500 2000 800] + SymbolLine[4000 3500 5000 3500 800] +) +Symbol['A' 1200] +( + SymbolLine[0 1500 0 5000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 2000 1000 800] + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[2500 1500 2500 5000 800] + SymbolLine[0 3000 2500 3000 800] +) +Symbol['B' 1200] +( + SymbolLine[0 5000 2000 5000 800] + SymbolLine[2000 5000 2500 4500 800] + SymbolLine[2500 3500 2500 4500 800] + SymbolLine[2000 3000 2500 3500 800] + SymbolLine[500 3000 2000 3000 800] + SymbolLine[500 1000 500 5000 800] + SymbolLine[0 1000 2000 1000 800] + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[2500 1500 2500 2500 800] + SymbolLine[2000 3000 2500 2500 800] +) +Symbol['C' 1200] +( + SymbolLine[500 5000 2000 5000 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 2000 1000 800] +) +Symbol['D' 1200] +( + SymbolLine[500 1000 500 5000 800] + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[2500 1500 2500 4500 800] + SymbolLine[2000 5000 2500 4500 800] + SymbolLine[0 5000 2000 5000 800] + SymbolLine[0 1000 2000 1000 800] +) +Symbol['E' 1200] +( + SymbolLine[0 3000 1500 3000 800] + SymbolLine[0 5000 2000 5000 800] + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 1000 2000 1000 800] +) +Symbol['F' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 1000 2000 1000 800] + SymbolLine[0 3000 1500 3000 800] +) +Symbol['G' 1200] +( + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[500 1000 2000 1000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 2000 5000 800] + SymbolLine[2000 5000 2500 4500 800] + SymbolLine[2500 3500 2500 4500 800] + SymbolLine[2000 3000 2500 3500 800] + SymbolLine[1000 3000 2000 3000 800] +) +Symbol['H' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[2500 1000 2500 5000 800] + SymbolLine[0 3000 2500 3000 800] +) +Symbol['I' 1200] +( + SymbolLine[0 1000 1000 1000 800] + SymbolLine[500 1000 500 5000 800] + SymbolLine[0 5000 1000 5000 800] +) +Symbol['J' 1200] +( + SymbolLine[0 1000 1500 1000 800] + SymbolLine[1500 1000 1500 4500 800] + SymbolLine[1000 5000 1500 4500 800] + SymbolLine[500 5000 1000 5000 800] + SymbolLine[0 4500 500 5000 800] +) +Symbol['K' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 3000 2000 1000 800] + SymbolLine[0 3000 2000 5000 800] +) +Symbol['L' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 5000 2000 5000 800] +) +Symbol['M' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 1000 1500 2500 800] + SymbolLine[1500 2500 3000 1000 800] + SymbolLine[3000 1000 3000 5000 800] +) +Symbol['N' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 1000 0 1500 800] + SymbolLine[0 1500 2500 4000 800] + SymbolLine[2500 1000 2500 5000 800] +) +Symbol['O' 1200] +( + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4500 500 5000 800] +) +Symbol['P' 1200] +( + SymbolLine[500 1000 500 5000 800] + SymbolLine[0 1000 2000 1000 800] + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[2500 1500 2500 2500 800] + SymbolLine[2000 3000 2500 2500 800] + SymbolLine[500 3000 2000 3000 800] +) +Symbol['Q' 1200] +( + SymbolLine[0 1500 0 4500 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1500 1000 800] + SymbolLine[1500 1000 2000 1500 800] + SymbolLine[2000 1500 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[1000 4000 2000 5000 800] +) +Symbol['R' 1200] +( + SymbolLine[0 1000 2000 1000 800] + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[2500 1500 2500 2500 800] + SymbolLine[2000 3000 2500 2500 800] + SymbolLine[500 3000 2000 3000 800] + SymbolLine[500 1000 500 5000 800] + SymbolLine[500 3000 2500 5000 800] +) +Symbol['S' 1200] +( + SymbolLine[2000 1000 2500 1500 800] + SymbolLine[500 1000 2000 1000 800] + SymbolLine[0 1500 500 1000 800] + SymbolLine[0 1500 0 2500 800] + SymbolLine[0 2500 500 3000 800] + SymbolLine[500 3000 2000 3000 800] + SymbolLine[2000 3000 2500 3500 800] + SymbolLine[2500 3500 2500 4500 800] + SymbolLine[2000 5000 2500 4500 800] + SymbolLine[500 5000 2000 5000 800] + SymbolLine[0 4500 500 5000 800] +) +Symbol['T' 1200] +( + SymbolLine[0 1000 2000 1000 800] + SymbolLine[1000 1000 1000 5000 800] +) +Symbol['U' 1200] +( + SymbolLine[0 1000 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[2000 1000 2000 4500 800] +) +Symbol['V' 1200] +( + SymbolLine[0 1000 0 4000 800] + SymbolLine[0 4000 1000 5000 800] + SymbolLine[1000 5000 2000 4000 800] + SymbolLine[2000 1000 2000 4000 800] +) +Symbol['W' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 5000 1500 3500 800] + SymbolLine[1500 3500 3000 5000 800] + SymbolLine[3000 1000 3000 5000 800] +) +Symbol['X' 1200] +( + SymbolLine[0 1000 0 1500 800] + SymbolLine[0 1500 2500 4000 800] + SymbolLine[2500 4000 2500 5000 800] + SymbolLine[0 4000 0 5000 800] + SymbolLine[0 4000 2500 1500 800] + SymbolLine[2500 1000 2500 1500 800] +) +Symbol['Y' 1200] +( + SymbolLine[0 1000 0 1500 800] + SymbolLine[0 1500 1000 2500 800] + SymbolLine[1000 2500 2000 1500 800] + SymbolLine[2000 1000 2000 1500 800] + SymbolLine[1000 2500 1000 5000 800] +) +Symbol['Z' 1200] +( + SymbolLine[0 1000 2500 1000 800] + SymbolLine[2500 1000 2500 1500 800] + SymbolLine[0 4000 2500 1500 800] + SymbolLine[0 4000 0 5000 800] + SymbolLine[0 5000 2500 5000 800] +) +Symbol['[' 1200] +( + SymbolLine[0 1000 500 1000 800] + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 5000 500 5000 800] +) +Symbol['\' 1200] +( + SymbolLine[0 1500 3000 4500 800] +) +Symbol[']' 1200] +( + SymbolLine[0 1000 500 1000 800] + SymbolLine[500 1000 500 5000 800] + SymbolLine[0 5000 500 5000 800] +) +Symbol['^' 1200] +( + SymbolLine[0 1500 500 1000 800] + SymbolLine[500 1000 1000 1500 800] +) +Symbol['_' 1200] +( + SymbolLine[0 5000 2000 5000 800] +) +Symbol['`' 1200] +( + SymbolLine[5000 0 6500 1500 800] + SymbolLine[6500 5000 5000 6500 800] + SymbolLine[5000 6500 1500 6500 800] + SymbolLine[1500 6500 0 5000 800] + SymbolLine[0 5000 0 1500 800] + SymbolLine[0 1500 1500 0 800] + SymbolLine[1500 0 5000 0 800] + SymbolLine[6500 1500 6500 5000 800] + SymbolLine[2500 2500 4000 2500 800] + SymbolLine[2000 3000 2500 2500 800] + SymbolLine[2000 3000 2000 4000 800] + SymbolLine[2000 4000 2500 4500 800] + SymbolLine[2500 4500 4000 4500 800] +) +Symbol['a' 1200] +( + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[0 3500 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[2000 3000 2000 4500 800] + SymbolLine[2000 4500 2500 5000 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] +) +Symbol['b' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[2000 3500 2000 4500 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[0 3500 500 3000 800] +) +Symbol['c' 1200] +( + SymbolLine[500 3000 2000 3000 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[0 3500 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 2000 5000 800] +) +Symbol['d' 1200] +( + SymbolLine[2000 1000 2000 5000 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 3500 0 4500 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] +) +Symbol['e' 1200] +( + SymbolLine[500 5000 2000 5000 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[0 3500 0 4500 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[0 4000 2000 4000 800] + SymbolLine[2000 4000 2000 3500 800] +) +Symbol['f' 1000] +( + SymbolLine[500 1500 500 5000 800] + SymbolLine[500 1500 1000 1000 800] + SymbolLine[1000 1000 1500 1000 800] + SymbolLine[0 3000 1000 3000 800] +) +Symbol['g' 1200] +( + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[0 3500 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[0 6000 500 6500 800] + SymbolLine[500 6500 1500 6500 800] + SymbolLine[1500 6500 2000 6000 800] + SymbolLine[2000 3000 2000 6000 800] +) +Symbol['h' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 2000 5000 800] +) +Symbol['i' 1000] +( + SymbolLine[0 2000 0 2500 800] + SymbolLine[0 3500 0 5000 800] +) +Symbol['j' 1000] +( + SymbolLine[500 2000 500 2500 800] + SymbolLine[500 3500 500 6000 800] + SymbolLine[0 6500 500 6000 800] +) +Symbol['k' 1200] +( + SymbolLine[0 1000 0 5000 800] + SymbolLine[0 3500 1500 5000 800] + SymbolLine[0 3500 1000 2500 800] +) +Symbol['l' 1000] +( + SymbolLine[0 1000 0 4500 800] + SymbolLine[0 4500 500 5000 800] +) +Symbol['m' 1200] +( + SymbolLine[500 3500 500 5000 800] + SymbolLine[500 3500 1000 3000 800] + SymbolLine[1000 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 2000 5000 800] + SymbolLine[2000 3500 2500 3000 800] + SymbolLine[2500 3000 3000 3000 800] + SymbolLine[3000 3000 3500 3500 800] + SymbolLine[3500 3500 3500 5000 800] + SymbolLine[0 3000 500 3500 800] +) +Symbol['n' 1200] +( + SymbolLine[500 3500 500 5000 800] + SymbolLine[500 3500 1000 3000 800] + SymbolLine[1000 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 2000 5000 800] + SymbolLine[0 3000 500 3500 800] +) +Symbol['o' 1200] +( + SymbolLine[0 3500 0 4500 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[2000 3500 2000 4500 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[0 4500 500 5000 800] +) +Symbol['p' 1200] +( + SymbolLine[500 3500 500 6500 800] + SymbolLine[0 3000 500 3500 800] + SymbolLine[500 3500 1000 3000 800] + SymbolLine[1000 3000 2000 3000 800] + SymbolLine[2000 3000 2500 3500 800] + SymbolLine[2500 3500 2500 4500 800] + SymbolLine[2000 5000 2500 4500 800] + SymbolLine[1000 5000 2000 5000 800] + SymbolLine[500 4500 1000 5000 800] +) +Symbol['q' 1200] +( + SymbolLine[2000 3500 2000 6500 800] + SymbolLine[1500 3000 2000 3500 800] + SymbolLine[500 3000 1500 3000 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[0 3500 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] +) +Symbol['r' 1200] +( + SymbolLine[500 3500 500 5000 800] + SymbolLine[500 3500 1000 3000 800] + SymbolLine[1000 3000 2000 3000 800] + SymbolLine[0 3000 500 3500 800] +) +Symbol['s' 1200] +( + SymbolLine[500 5000 2000 5000 800] + SymbolLine[2000 5000 2500 4500 800] + SymbolLine[2000 4000 2500 4500 800] + SymbolLine[500 4000 2000 4000 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[0 3500 500 3000 800] + SymbolLine[500 3000 2000 3000 800] + SymbolLine[2000 3000 2500 3500 800] + SymbolLine[0 4500 500 5000 800] +) +Symbol['t' 1000] +( + SymbolLine[500 1000 500 4500 800] + SymbolLine[500 4500 1000 5000 800] + SymbolLine[0 2500 1000 2500 800] +) +Symbol['u' 1200] +( + SymbolLine[0 3000 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] + SymbolLine[2000 3000 2000 4500 800] +) +Symbol['v' 1200] +( + SymbolLine[0 3000 0 4000 800] + SymbolLine[0 4000 1000 5000 800] + SymbolLine[1000 5000 2000 4000 800] + SymbolLine[2000 3000 2000 4000 800] +) +Symbol['w' 1200] +( + SymbolLine[0 3000 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[500 5000 1000 5000 800] + SymbolLine[1000 5000 1500 4500 800] + SymbolLine[1500 3000 1500 4500 800] + SymbolLine[1500 4500 2000 5000 800] + SymbolLine[2000 5000 2500 5000 800] + SymbolLine[2500 5000 3000 4500 800] + SymbolLine[3000 3000 3000 4500 800] +) +Symbol['x' 1200] +( + SymbolLine[0 3000 2000 5000 800] + SymbolLine[0 5000 2000 3000 800] +) +Symbol['y' 1200] +( + SymbolLine[0 3000 0 4500 800] + SymbolLine[0 4500 500 5000 800] + SymbolLine[2000 3000 2000 6000 800] + SymbolLine[1500 6500 2000 6000 800] + SymbolLine[500 6500 1500 6500 800] + SymbolLine[0 6000 500 6500 800] + SymbolLine[500 5000 1500 5000 800] + SymbolLine[1500 5000 2000 4500 800] +) +Symbol['z' 1200] +( + SymbolLine[0 3000 2000 3000 800] + SymbolLine[0 5000 2000 3000 800] + SymbolLine[0 5000 2000 5000 800] +) +Symbol['{' 1200] +( + SymbolLine[500 1500 1000 1000 800] + SymbolLine[500 1500 500 2500 800] + SymbolLine[0 3000 500 2500 800] + SymbolLine[0 3000 500 3500 800] + SymbolLine[500 3500 500 4500 800] + SymbolLine[500 4500 1000 5000 800] +) +Symbol['|' 1200] +( + SymbolLine[0 1000 0 5000 800] +) +Symbol['}' 1200] +( + SymbolLine[0 1000 500 1500 800] + SymbolLine[500 1500 500 2500 800] + SymbolLine[500 2500 1000 3000 800] + SymbolLine[500 3500 1000 3000 800] + SymbolLine[500 3500 500 4500 800] + SymbolLine[0 5000 500 4500 800] +) +Symbol['~' 1200] +( + SymbolLine[0 3500 500 3000 800] + SymbolLine[500 3000 1000 3000 800] + SymbolLine[1000 3000 1500 3500 800] + SymbolLine[1500 3500 2000 3500 800] + SymbolLine[2000 3500 2500 3000 800] +) +Attribute("PCB::grid::unit" "mil") +Via[76900 58200 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[76900 64200 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[106100 60000 3100 1200 0 1500 "" ""] +Via[106100 65000 3100 1200 0 1500 "" ""] +Via[114200 62600 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[54600 89600 3100 1200 0 1500 "" ""] +Via[73700 89600 3100 1200 0 1500 "" ""] +Via[103300 92000 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[108900 25100 3100 1200 0 1500 "" "thermal(1S)"] +Via[138700 5200 3100 1200 0 1500 "" "thermal(1S)"] +Via[12300 76900 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[19600 86700 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[24200 62500 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[219800 40900 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[219800 36400 3100 1200 0 1500 "" "thermal(2S)"] +Via[208400 82600 3100 1200 0 1500 "" "thermal(2S)"] +Via[156000 29600 3100 1200 0 1500 "" "thermal(2S)"] +Via[195800 97800 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[177500 97800 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[227600 118600 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[200000 109200 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[216200 98300 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[226300 64500 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[174100 37700 3100 1200 0 1500 "" ""] +Via[170200 37700 3100 1200 0 1500 "" ""] +Via[161300 37000 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[196800 55300 3100 1200 0 1500 "" ""] +Via[202300 43400 3100 1200 0 1500 "" ""] +Via[163100 40300 3100 1200 0 1500 "" ""] +Via[2900 63700 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[88100 10300 3100 1200 0 1500 "" ""] +Via[119700 21900 3100 1200 0 1500 "" ""] +Via[5900 44500 3100 1200 0 1500 "" ""] +Via[151200 34800 3100 1200 0 1500 "" ""] +Via[29200 54600 3100 1200 0 1500 "" ""] +Via[177800 50700 3100 1200 0 1500 "" ""] +Via[180900 48200 3100 1200 0 1500 "" ""] +Via[208300 78500 3100 1200 0 1500 "" ""] +Via[146900 83200 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[118400 75600 3100 1200 0 1500 "" ""] +Via[158600 64100 3100 1200 0 1500 "" ""] +Via[177100 77600 3100 1200 0 1500 "" ""] +Via[78600 41400 3100 1200 0 1500 "" ""] +Via[191300 69500 3100 1200 0 1500 "" ""] +Via[201300 83500 3100 1200 0 1500 "" ""] +Via[49300 82100 3100 1200 0 1500 "" ""] +Via[181700 64500 3100 1200 0 1500 "" ""] +Via[202700 71800 3100 1200 0 1500 "" ""] +Via[179100 88800 3100 1200 0 1500 "" "thermal(2S)"] +Via[192600 83900 3100 1200 0 1500 "" ""] +Via[196700 83500 3100 1200 0 1500 "" ""] +Via[203300 63600 3100 1200 0 1500 "" ""] +Via[180100 74600 3100 1200 0 1500 "" ""] +Via[111300 122400 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[90000 113400 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[90000 105500 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[115200 92000 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[125200 118900 3100 1200 0 1500 "" "thermal(2S)"] +Via[147400 120100 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[137600 120100 3100 1200 0 1500 "" "thermal(2S)"] +Via[129100 120100 3100 1200 0 1500 "" "thermal(1S)"] +Via[150500 99100 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[124400 101600 3100 1200 0 1500 "" ""] +Via[123900 59700 3100 1200 0 1500 "" ""] +Via[236900 45600 3100 1200 0 1500 "" "thermal(2S)"] +Via[244400 53600 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[124600 105500 3100 1200 0 1500 "" ""] +Via[124600 109500 3100 1200 0 1500 "" ""] +Via[155600 106500 3100 1200 0 1500 "" ""] +Via[155600 102600 3100 1200 0 1500 "" ""] +Via[128300 105000 3100 1200 0 1500 "" ""] +Via[127400 53600 3100 1200 0 1500 "" ""] +Via[127500 99100 3100 1200 0 1500 "" ""] +Via[121200 86800 3100 1200 0 1500 "" ""] +Via[142900 86000 3100 1200 0 1500 "" "thermal(2S)"] +Via[133400 86100 3100 1200 0 1500 "" ""] +Via[133400 120100 3100 1200 0 1500 "" ""] +Via[147600 38000 3100 1200 0 1500 "" ""] +Via[165300 37000 3100 1200 0 1500 "" ""] +Via[171800 97800 3100 1200 0 1500 "" ""] +Via[177600 64500 3100 1200 0 1500 "" ""] +Via[203800 18000 3100 1200 0 1500 "" ""] +Via[216900 31500 3100 1200 0 1500 "" ""] +Via[239400 37600 3100 1200 0 1500 "" ""] +Via[226400 46000 3100 1200 0 1500 "" ""] +Via[231000 52300 3100 1200 0 1500 "" ""] +Via[182500 86700 3100 1200 0 1500 "" ""] +Via[218800 60800 3100 1200 0 1500 "" ""] +Via[229200 48800 3100 1200 0 1500 "" ""] +Via[199600 60800 3100 1200 0 1500 "" ""] +Via[160900 60800 3100 1200 0 1500 "" ""] +Via[142000 54000 3100 1200 0 1500 "" ""] +Via[191800 48800 3100 1200 0 1500 "" ""] +Via[165200 122100 3100 1200 0 1500 "" ""] +Via[122000 120800 3100 1200 0 1500 "" ""] +Via[62400 24800 3100 1200 0 1500 "" "thermal(1S)"] +Via[56600 98000 3100 1200 0 1500 "" "thermal(1S)"] +Via[65500 100200 3100 1200 0 1500 "" "thermal(1S)"] +Via[67652 61200 3100 1200 0 1500 "" ""] +Via[61900 64500 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[67626 67700 3100 1200 0 1500 "" ""] +Via[80000 93300 3100 1200 0 1500 "" "thermal(1S)"] +Via[68500 24800 3100 1200 0 1500 "" "thermal(1S)"] +Via[93900 87100 3100 1200 0 1500 "" ""] +Via[130400 57400 3100 1200 0 1500 "" ""] +Via[138800 37100 3100 1200 0 1500 "" "thermal(2S)"] +Via[143800 46800 3100 1200 0 1500 "" ""] +Via[124500 46500 3100 1200 0 1500 "" ""] +Via[120600 46600 3100 1200 0 1500 "" "thermal(2S)"] +Via[147700 69400 3100 1200 0 1500 "" "thermal(1S)"] +Via[141900 69400 3100 1200 0 1500 "" ""] +Via[143800 42200 3100 1200 0 1500 "" ""] +Via[108700 79700 3100 1200 0 1500 "" ""] +Via[123500 53900 3100 1200 0 1500 "" ""] +Via[116400 40100 3100 1200 0 1500 "" "thermal(1S)"] +Via[116400 34200 3100 1200 0 1500 "" "thermal(1S)"] +Via[133000 32100 3100 1200 0 1500 "" "thermal(1S)"] +Via[40400 32500 3100 1200 0 1500 "" "thermal(1S)"] +Via[33800 26100 3100 1200 0 1500 "" "thermal(2S)"] +Via[39300 42000 3100 1200 0 1500 "" ""] +Via[38400 101100 3100 1200 0 1500 "" ""] +Via[38400 118000 3100 1200 0 1500 "" "thermal(1S)"] +Via[46900 98600 3100 1200 0 1500 "" ""] +Via[51800 112900 3100 1200 0 1500 "" "thermal(2S)"] +Via[49000 115500 3100 1200 0 1500 "" ""] +Via[69000 104200 3100 1200 0 1500 "" ""] +Via[66800 111900 3100 1200 0 1500 "" ""] +Via[56700 67800 3100 1200 0 1500 "" ""] +Via[59300 53200 3100 1200 0 1500 "" ""] +Via[43900 62500 3100 1200 0 1500 "" "thermal(1S)"] +Via[48500 53700 3100 1200 0 1500 "" ""] +Via[49900 71200 3100 1200 0 1500 "" ""] +Via[46200 69900 3100 1200 0 1500 "" ""] +Via[59000 115400 3100 1200 0 1500 "" ""] +Via[50800 87100 3100 1200 0 1500 "" ""] +Via[35000 110100 3100 1200 0 1500 "" ""] +Via[67800 4700 3100 1200 0 1500 "" "thermal(2S)"] +Via[52700 13000 3100 1200 0 1500 "" "thermal(1S)"] +Via[45200 15800 3100 1200 0 1500 "" "thermal(1S)"] +Via[52500 4800 3100 1200 0 1500 "" ""] +Via[55800 23000 3100 1200 0 1500 "" ""] +Via[49000 23000 3100 1200 0 1500 "" ""] +Via[94300 37600 3100 1200 0 1500 "" ""] +Via[57500 60300 3100 1200 0 1500 "" ""] +Via[52600 44100 3100 1200 0 1500 "" ""] +Via[67400 16800 3100 1200 0 1500 "" ""] +Via[74900 27400 3100 1200 0 1500 "" ""] +Via[60100 15700 3100 1200 0 1500 "" ""] +Via[45200 8400 3100 1200 0 1500 "" ""] +Via[16600 33400 3100 1600 0 1500 "" "thermal(2S)"] +Via[198800 100400 3100 1200 0 1500 "" "thermal(2S)"] +Via[78200 89500 3100 1600 0 1500 "" "thermal(2S)"] +Via[218400 84200 3100 1600 0 1500 "" "thermal(1S,3S)"] +Via[219100 102200 3100 1200 0 1500 "" ""] +Via[244700 82800 3100 1200 0 1500 "" "thermal(1S,3S)"] +Via[244700 92100 3100 1200 0 1500 "" "thermal(2S)"] +Via[237100 69900 3100 1200 0 1500 "" ""] + +Element["hidename,lock" "hole-M3" "H2" "unknown" 12500 12500 -3700 -3300 0 100 ""] +( + Pin[0 0 17500 3000 22500 12500 "1" "1" "thermal(1S,3S)"] + ElementArc [0 0 12000 12000 0 360 1000] + + ) + +Element["hidename,onsolder" "B2B-PH" "B1" "LiPo" 276 50823 668 21947 0 100 "auto"] +( + Pin[11024 7677 5118 1201 5748 2953 "-" "2" "thermal(1t,3X)"] + Pin[11024 15551 5118 1201 5748 2953 "+" "1" "square"] + ElementLine [0 0 0 23228 600] + ElementLine [0 23228 17717 23228 600] + ElementLine [17717 0 17717 23228 600] + ElementLine [0 0 17717 0 600] + + ) + +Element["hidename,lock" "hole-M3" "H1" "unknown" 12500 112500 -1551 -1100 0 100 ""] +( + Pin[0 0 17500 3000 22500 12500 "1" "1" "thermal(1S,3S)"] + ElementArc [0 0 12000 12000 0 360 1000] + + ) + +Element["hidename,lock" "hole-M3" "H3" "unknown" 312500 12500 -3900 -2600 0 100 ""] +( + Pin[0 0 17500 3000 22500 12500 "1" "1" "thermal(1S,3S)"] + ElementArc [0 0 12000 12000 0 360 1000] + + ) + +Element["hidename,lock" "hole-M3" "H4" "unknown" 312500 112500 -3200 -4207 0 100 ""] +( + Pin[0 0 17500 3000 22500 12500 "1" "1" "thermal(1S,3S)"] + ElementArc [0 0 12000 12000 0 360 1000] + + ) + +Element["hidename,onsolder" "282834-9" "J1" "Pyro" 18394 62395 0 0 0 100 "auto"] +( + Pin[5906 -12795 7087 1260 8346 4528 "9" "9" "edge2,thermal(1t,3X)"] + Pin[15906 -12795 7087 1260 8346 4528 "8" "8" "edge2,thermal(2S)"] + Pin[25906 -12795 7087 1260 8346 4528 "7" "7" "edge2"] + Pin[35906 -12795 7087 1260 8346 4528 "6" "6" "edge2"] + Pin[45906 -12795 7087 1260 8346 4528 "5" "5" "edge2,thermal(2S)"] + Pin[55906 -12795 7087 1260 8346 4528 "4" "4" "edge2"] + Pin[65906 -12795 7087 1260 8346 4528 "3" "3" "edge2,thermal(2S)"] + Pin[75906 -12795 7087 1260 8346 4528 "2" "2" "edge2"] + Pin[85906 -12795 7087 1260 8346 4528 "1" "1" "square,edge2,thermal(2S)"] + ElementLine [0 -25591 0 0 600] + ElementLine [0 -25591 91811 -25591 600] + ElementLine [91811 -25591 91811 0 600] + ElementLine [0 0 91811 0 600] + + ) + +Element["hidename,onsolder" "282834-9" "J2" "Pyro" 110106 62605 0 0 2 100 "auto"] +( + Pin[-5906 12795 7087 1260 8346 4528 "9" "9" "edge2,thermal(2S)"] + Pin[-15906 12795 7087 1260 8346 4528 "8" "8" "edge2"] + Pin[-25906 12795 7087 1260 8346 4528 "7" "7" "edge2,thermal(2S)"] + Pin[-35906 12795 7087 1260 8346 4528 "6" "6" "edge2"] + Pin[-45906 12795 7087 1260 8346 4528 "5" "5" "edge2,thermal(2S)"] + Pin[-55906 12795 7087 1260 8346 4528 "4" "4" "edge2"] + Pin[-65906 12795 7087 1260 8346 4528 "3" "3" "edge2,thermal(1t,3t)"] + Pin[-75906 12795 7087 1260 8346 4528 "2" "2" "edge2"] + Pin[-85906 12795 7087 1260 8346 4528 "1" "1" "square,edge2"] + ElementLine [0 0 0 25591 600] + ElementLine [-91811 25591 0 25591 600] + ElementLine [-91811 0 -91811 25591 600] + ElementLine [-91811 0 0 0 600] + + ) + +Element["hidename" "SOT23" "U11" "MCP130T-300" 28100 33400 -7300 1100 0 100 ""] +( + Pad[0 -300 0 300 3400 3000 4000 "RESET" "1" "square"] + Pad[-7800 -300 -7800 300 3400 3000 4000 "VCC" "2" "square"] + Pad[-3900 7900 -3900 8500 3400 3000 4000 "GND" "3" "square,edge2"] + ElementLine [2500 -2900 2500 11000 1000] + ElementLine [-10300 -2900 2500 -2900 1000] + ElementLine [-10300 -2900 -10300 11000 1000] + ElementLine [-10300 11000 2500 11000 1000] + + ) + +Element["hidename" "0402" "R28" "27k" 123026 76100 -2354 -7450 0 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R27" "100k" 113826 76000 -4902 -7350 0 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R23" "27k" 54600 93826 -7550 8050 1 100 ""] +( + Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R18" "100k" 73700 85126 -7450 6350 1 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R17" "100k" 54648 85074 -7550 6976 1 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R1" "3.3k" 75000 23800 -2950 2450 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R11" "549" 46800 93874 1950 1254 1 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R15" "100k" 101926 65000 -3550 1750 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R2" "3.3k" 49000 28774 1750 3650 1 100 ""] +( + Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C5" "4.7uF" 24200 67574 7550 -2613 3 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R20" "27k" 49000 36274 2450 -13450 3 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R13" "100k" 73900 39074 -2950 3454 1 100 ""] +( + Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R12" "549" 70574 100700 -1876 1150 0 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R5" "3.3k" 50700 93874 -2050 -24 3 100 ""] +( + Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R19" "27k" 73900 32326 3450 -13250 3 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R6" "3.3k" 75226 97000 95 1250 0 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R8" "549" 54100 26700 -3150 2250 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R7" "549" 71800 20000 3250 -2050 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C4" "4.7uF" 2900 68674 3050 -9109 3 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R22" "27k" 110326 60100 7650 -1750 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R21" "27k" 110300 65000 8424 7850 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R16" "100k" 101900 60000 -3950 -7350 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R24" "27k" 75200 93300 8198 7450 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R14" "100k" 54100 41200 -12250 -3550 0 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R50" "1k" 2900 74826 3368 1704 3 100 ""] +( + Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R401" "10k" 221200 65300 -5350 -7350 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R402" "10k" 146500 73500 -6950 -7450 0 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C36" "0.1uF" 18100 47126 2750 3872 3 100 ""] +( + Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C600" "0.1uF" 191700 98974 -750 -3150 3 105 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "L600" "bead" 204826 100200 -5503 850 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C602" "0.1uF" 211052 100200 4029 -2540 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C601" "1uF" 211100 96400 4002 -3850 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C610" "0.1uF" 179200 102200 7250 -5350 3 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C302" "0.1uF" 128600 110574 -2950 16550 1 100 ""] +( + Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C301" "0.1uF" 126600 115500 5850 -1450 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename,onsolder" "0-338068-8" "J9" "Companion" 187500 7500 0 0 2 100 "auto"] +( + Pin[0 10000 6299 1200 7299 3150 "1" "1" "square,edge2,thermal(1X,3X)"] + Pin[-5000 0 6299 1200 7299 3150 "2" "2" "edge2"] + Pin[-10000 10000 6299 1200 7299 3150 "3" "3" "edge2"] + Pin[-15000 0 6299 1200 7299 3150 "4" "4" "edge2"] + Pin[-20000 10000 6299 1200 7299 3150 "5" "5" "edge2"] + Pin[-25000 0 6299 1200 7299 3150 "6" "6" "edge2"] + Pin[-30000 10000 6299 1200 7299 3150 "7" "7" "edge2,thermal(2X)"] + Pin[-35000 0 6299 1200 7299 3150 "8" "8" "edge2"] + Pin[5511 2913 7306 1400 7906 5906 "mnt" "0" "edge2"] + ElementLine [11593 -5038 11593 15039 600] + ElementLine [-46594 15039 11593 15039 600] + ElementLine [-46594 -5038 -46594 15039 600] + ElementLine [-46594 -5038 11593 -5038 600] + + ) + +Element["hidename" "ZX62-B-5PA" "J5" "USBmicroB" 114000 20658 12861 6211 2 100 ""] +( + Pad[0 -4528 0 -787 1575 984 2362 "DATA+" "3" "square,edge2"] + Pad[2558 -4528 2558 -787 1575 984 2362 "DATA-" "2" "square,edge2"] + Pad[-2559 -4528 -2559 -787 1575 984 2362 "ID" "4" "square,edge2"] + Pad[5117 -4528 5117 -787 1575 984 2362 "VBUS" "1" "square,edge2"] + Pad[-5118 -4528 -5118 -787 1575 984 2362 "GND" "5" "square,edge2"] + Pad[-13189 -3150 -11220 -3150 6299 984 7087 "tab1" "G" "square"] + Pad[11219 -3150 13188 -3150 6299 984 7087 "tab2" "G" "square,edge2"] + Pad[-4724 -13189 -4724 -13189 7480 984 8268 "tab3" "G" "square"] + Pad[4723 -13189 4723 -13189 7480 984 8268 "tab4" "G" "square,edge2"] + Pad[-15748 -13386 -15748 -12992 7087 984 7874 "tab5" "G" "square"] + Pad[15747 -13386 15747 -12992 7087 984 7874 "tab6" "G" "square"] + + ) + +Element["hidename" "0605" "D2" "dualLED" 147026 11582 0 0 2 100 ""] +( + Pad[-1280 -2067 -1280 -1280 2559 -1771 3159 "2" "2" "square,edge2"] + Pad[-4626 -2067 -4626 -1280 2559 -1771 3159 "1" "1" "square,edge2"] + Pad[-1280 -7776 -1280 -6988 2559 -1771 3159 "4" "4" "square"] + Pad[-4626 -7776 -4626 -6988 2559 -1771 3159 "3" "3" "square"] + + ) + +Element["hidename" "0402" "R53" "1k" 142100 15400 -1650 -4250 3 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R52" "1k" 146100 15426 6950 -4150 3 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R35" "2k" 10674 85200 3554 -2450 0 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R51" "1k" 19600 91500 -2650 -4902 1 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0605" "D1" "dualLED" 10382 88474 1392 -256 0 100 ""] +( + Pad[-2067 1280 -1280 1280 2559 -1771 3159 "2" "2" "square,edge2"] + Pad[-2067 4626 -1280 4626 2559 -1771 3159 "1" "1" "square,edge2"] + Pad[-7776 1280 -6988 1280 2559 -1771 3159 "4" "4" "square"] + Pad[-7776 4626 -6988 4626 2559 -1771 3159 "3" "3" "square"] + + ) + +Element["hidename" "SOT23-5" "U2" "MCP73831" 8200 73000 7800 -7500 0 89 ""] +( + Attribute("author" "DJ Delorie") + Attribute("copyright" "2006 DJ Delorie") + Attribute("use-license" "Unlimited") + Attribute("dist-license" "GPL") + Pad[-800 0 800 0 2400 3000 3000 "VIN" "4" "square"] + Pad[-800 7800 800 7800 2400 3000 3000 "PROG" "5" "square"] + Pad[7400 7800 9000 7800 2400 3000 3000 "STAT" "1" "square,edge2"] + Pad[7400 3900 9000 3900 2400 3000 3000 "VSS" "2" "square,edge2"] + Pad[7400 0 9000 0 2400 3000 3000 "VBAT" "3" "square,edge2"] + ElementLine [-2900 -2000 11000 -2000 1000] + ElementLine [-2900 -2000 -2900 9800 1000] + ElementLine [-2900 9800 11000 9800 1000] + ElementLine [11000 -2000 11000 9800 1000] + + ) + +Element["hidename" "0402" "C33" "22pF" 227653 113847 7150 750 3 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C32" "22pF" 199953 113847 -1050 150 3 100 ""] +( + Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "ABM3B" "X2" "8mhz" 213827 113923 -2798 4950 0 100 ""] +( + Pad[6692 4724 9054 4724 4724 0 5324 "2" "2" "square,edge2"] + Pad[-9055 4724 -6693 4724 4724 0 5324 "1" "1" "square"] + Pad[-9055 -4723 -6693 -4723 4724 0 5324 "4" "4" "square"] + Pad[6692 -4723 9054 -4723 4724 0 5324 "3" "3" "square,edge2"] + ElementArc [-10000 945 500 500 270 360 1000] + + ) + +Element["hidename,onsolder" "0-215079-4" "J20" "Debug" 187500 107500 0 0 2 100 "auto"] +( + Pin[0 10000 6299 1200 7299 3150 "pin1" "1" "square,edge2,thermal(1X)"] + Pin[-5000 0 6299 1200 7299 3150 "pin2" "2" "edge2"] + Pin[-10000 10000 6299 1200 7299 3150 "pin3" "3" "edge2"] + Pin[-15000 0 6299 1200 7299 3150 "pin4" "4" "edge2"] + Pin[5511 2913 7306 1400 7906 5906 "mnt" "0" "edge2"] + ElementLine [9428 -5038 9428 15039 600] + ElementLine [-24429 15039 9428 15039 600] + ElementLine [-24429 -5038 -24429 15039 600] + ElementLine [-24429 -5038 9428 -5038 600] + + ) + +Element["hidename,onsolder" "0-215079-6" "J21" "Boot" 236500 7500 0 0 2 100 "auto"] +( + Pin[0 10000 6299 1200 7299 3150 "pin1" "1" "square,edge2,thermal(1X,3X)"] + Pin[-5000 0 6299 1200 7299 3150 "pin2" "2" "edge2"] + Pin[-10000 10000 6299 1200 7299 3150 "pin3" "3" "edge2"] + Pin[-15000 0 6299 1200 7299 3150 "pin4" "4" "edge2"] + Pin[-20000 10000 6299 1200 7299 3150 "pin5" "5" "edge2"] + Pin[-25000 0 6299 1200 7299 3150 "pin6" "6" "edge2,thermal(2X)"] + Pin[5511 2913 7306 1400 7906 5906 "mnt" "0" "edge2"] + ElementLine [9428 15039 9428 -5038 600] + ElementLine [-34429 15039 9428 15039 600] + ElementLine [-34429 15039 -34429 -5038 600] + ElementLine [-34429 -5038 9428 -5038 600] + + ) + +Element["hidename" "0402" "R104" "0" 200000 18000 -3150 -3150 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C404" "47pF" 193874 18000 -3150 -3150 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R105" "0" 195600 26000 -3150 -3150 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C405" "47pF" 187500 24326 3150 -3150 3 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R103" "0" 212600 32000 3150 3150 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C403" "47pF" 221126 32000 3150 3150 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "AN3111" "U3" "MMA6555" 109300 107500 0 0 3 100 ""] +( + Pad[0 0 0 0 15748 0 16339 "VSS" "17" "square,edge2,nopaste"] + Pad[5511 -5511 5511 -5511 3937 0 3937 "VSS" "17" "square,edge2"] + Pad[5511 0 5511 0 3937 0 3937 "VSS" "17" "square,edge2"] + Pad[5511 5512 5511 5512 3937 0 3937 "VSS" "17" "square,edge2"] + Pad[0 -5511 0 -5511 3937 0 3937 "VSS" "17" "square,edge2"] + Pad[0 0 0 0 3937 0 3937 "VSS" "17" "square,edge2"] + Pad[0 5512 0 5512 3937 0 3937 "VSS" "17" "square,edge2"] + Pad[-5512 -5511 -5512 -5511 3937 0 3937 "VSS" "17" "square"] + Pad[-5512 0 -5512 0 3937 0 3937 "VSS" "17" "square"] + Pad[-5512 5512 -5512 5512 3937 0 3937 "VSS" "17" "square"] + Pad[-10413 10413 -10413 10413 2165 0 2756 "NC" "NC" "square"] + Pad[10412 10413 10412 10413 2165 0 2756 "NC" "NC" "square,edge2"] + Pad[-10413 -10412 -10413 -10412 2165 0 2756 "NC" "NC" "square"] + Pad[10412 -10412 10412 -10412 2165 0 2756 "NC" "NC" "square,edge2"] + Pad[10629 -5905 12007 -5905 1969 0 2559 "CS" "12" "square,edge2"] + Pad[-12008 -5905 -10630 -5905 1969 0 2559 "VREGA" "1" "square"] + Pad[5905 10630 5905 12008 1969 0 2559 "MISO" "8" "square,edge2"] + Pad[5905 -12007 5905 -10629 1969 0 2559 "VSSA" "13" "square"] + Pad[10629 -1968 12007 -1968 1969 0 2559 "MOSI" "11" "square,edge2"] + Pad[-12008 -1968 -10630 -1968 1969 0 2559 "VSS" "2" "square"] + Pad[1968 10630 1968 12008 1969 0 2559 "VPP/TEST" "7" "square,edge2"] + Pad[1968 -12007 1968 -10629 1969 0 2559 "pin14" "14" "square"] + Pad[10629 1969 12007 1969 1969 0 2559 "SCLK" "10" "square,edge2"] + Pad[-12008 1969 -10630 1969 1969 0 2559 "VREG" "3" "square"] + Pad[-1969 10630 -1969 12008 1969 0 2559 "ARM" "6" "square,edge2"] + Pad[-1969 -12007 -1969 -10629 1969 0 2559 "pin15" "15" "square"] + Pad[10629 5906 12007 5906 1969 0 2559 "VCC" "9" "square,edge2"] + Pad[-12008 5906 -10630 5906 1969 0 2559 "VSS" "4" "square"] + Pad[-5906 10630 -5906 12008 1969 0 2559 "pin5" "5" "square,edge2"] + Pad[-5906 -12007 -5906 -10629 1969 0 2559 "VSSA" "16" "square"] + ElementArc [-12598 -12597 500 500 270 360 1000] + + ) + +Element["hidename" "0402" "C103" "1uF" 91600 101600 -2224 350 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C102" "1uF" 91600 109500 15476 3450 2 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "MPU6000" "U12" "MPU-6000" 142500 107500 4400 3200 2 100 ""] +( + Pad[4920 6849 4920 8897 1102 866 1654 "GND" "18" "edge2"] + Pad[4920 -8898 4920 -6850 1102 866 1654 "CLKIN" "1" ""] + Pad[-8898 4920 -6850 4920 1102 866 1654 "INT" "12" ""] + Pad[6849 4920 8897 4920 1102 866 1654 "pin19" "19" "edge2"] + Pad[2952 6849 2952 8897 1102 866 1654 "pin17" "17" "edge2"] + Pad[2952 -8898 2952 -6850 1102 866 1654 "pin2" "2" ""] + Pad[-8898 2952 -6850 2952 1102 866 1654 "FSYNC" "11" ""] + Pad[6849 2952 8897 2952 1102 866 1654 "CPOUT" "20" "edge2"] + Pad[983 6849 983 8897 1102 866 1654 "pin16" "16" "edge2"] + Pad[983 -8898 983 -6850 1102 866 1654 "pin3" "3" ""] + Pad[-8898 983 -6850 983 1102 866 1654 "REGOUT" "10" ""] + Pad[6849 983 8897 983 1102 866 1654 "pin21" "21" "edge2"] + Pad[-984 6849 -984 8897 1102 866 1654 "pin15" "15" "edge2"] + Pad[-984 -8898 -984 -6850 1102 866 1654 "pin4" "4" ""] + Pad[-8898 -984 -6850 -984 1102 866 1654 "AD0/SDO" "9" ""] + Pad[6849 -984 8897 -984 1102 866 1654 "pin22" "22" "edge2"] + Pad[-2953 6849 -2953 8897 1102 866 1654 "pin14" "14" "edge2"] + Pad[-2953 -8898 -2953 -6850 1102 866 1654 "pin5" "5" ""] + Pad[-8898 -2953 -6850 -2953 1102 866 1654 "CS" "8" ""] + Pad[6849 -2953 8897 -2953 1102 866 1654 "SCL/SCLK" "23" "edge2"] + Pad[-4921 6849 -4921 8897 1102 866 1654 "VDD" "13" "edge2"] + Pad[-4921 -8898 -4921 -6850 1102 866 1654 "AUX_DA" "6" ""] + Pad[-8898 -4921 -6850 -4921 1102 866 1654 "AUX_CL" "7" ""] + Pad[6849 -4921 8897 -4921 1102 866 1654 "SDA/SDI" "24" "edge2"] + ElementArc [9448 -9449 500 500 180 360 1000] + + ) + +Element["hidename" "0402" "C303" "10nF" 152300 120100 3498 -1050 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C101" "0.1uF" 142500 120100 -5202 -6750 0 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "SOIJ8" "U5" "W25Q64" 236900 45600 -8011 2461 1 100 ""] +( + Pad[-7499 -15845 -7499 -11712 2559 2441 3159 "VCC" "8" "square"] + Pad[-7499 11713 -7499 15846 2559 2441 3159 "CS" "1" "square,edge2"] + Pad[-2499 -15845 -2499 -11712 2559 2441 3159 "HOLD" "7" "square"] + Pad[-2499 11713 -2499 15846 2559 2441 3159 "SO" "2" "square,edge2"] + Pad[2500 -15845 2500 -11712 2559 2441 3159 "SCK" "6" "square"] + Pad[2500 11713 2500 15846 2559 2441 3159 "WP" "3" "square,edge2"] + Pad[7500 -15845 7500 -11712 2559 2441 3159 "SI" "5" "square"] + Pad[7500 11713 7500 15846 2559 2441 3159 "VSS" "4" "square,edge2"] + ElementLine [-10491 -10590 -10491 10591 1000] + ElementLine [-10491 10591 10492 10591 1000] + ElementLine [10492 -10590 10492 10591 1000] + ElementLine [-10491 -10590 10492 -10590 1000] + ElementArc [-7499 8760 500 500 0 360 1000] + + ) + +Element["hidename,onsolder" "TDK_PS12" "U8" "TDK_PS12" 135500 62542 8100 -3316 1 100 "auto"] +( + Pin[0 9842 7874 3937 8661 2756 "1" "1" "square,thermal(1X,3X)"] + Pin[0 -9843 7874 3937 8661 2756 "2" "2" ""] + ElementArc [0 0 24016 24016 90 360 1000] + + ) + +Element["hidename" "1212-8" "Q3" "Si7232DN" 64208 89494 -10161 -12011 0 100 ""] +( + Pad[-3838 -6800 -3838 -4497 1594 965 2194 "pin8" "8" "square"] + Pad[-3838 4498 -3838 6801 1594 965 2194 "pin1" "1" "square,edge2"] + Pad[-1279 -6800 -1279 -4497 1594 965 2194 "pin7" "7" "square"] + Pad[-1279 4498 -1279 6801 1594 965 2194 "pin2" "2" "square,edge2"] + Pad[1280 -6800 1280 -4497 1594 965 2194 "pin6" "6" "square"] + Pad[1280 4498 1280 6801 1594 965 2194 "pin3" "3" "square,edge2"] + Pad[3839 -6800 3839 -4497 1594 965 2194 "pin5" "5" "square"] + Pad[3839 4498 3839 6801 1594 965 2194 "pin4" "4" "square,edge2"] + Pad[-2391 -3641 -2391 -747 3898 -3011 4498 "pin8" "8" "square"] + Pad[2392 -3641 2392 -747 3898 -3011 4498 "pin5" "5" "square"] + ElementLine [-6495 -6495 -6495 6496 1000] + ElementLine [-6495 6496 6496 6496 1000] + ElementLine [6496 -6495 6496 6496 1000] + ElementLine [-6495 -6495 6496 -6495 1000] + ElementArc [-5117 9118 500 500 0 360 1000] + + ) + +Element["hidename" "1212-8" "Q2" "Si7232DN" 88600 62500 12011 -10161 3 100 ""] +( + Pad[4497 -3838 6800 -3838 1594 965 2194 "pin8" "8" "square,edge2"] + Pad[-6801 -3838 -4498 -3838 1594 965 2194 "pin1" "1" "square"] + Pad[4497 -1279 6800 -1279 1594 965 2194 "pin7" "7" "square,edge2"] + Pad[-6801 -1279 -4498 -1279 1594 965 2194 "pin2" "2" "square"] + Pad[4497 1280 6800 1280 1594 965 2194 "pin6" "6" "square,edge2"] + Pad[-6801 1280 -4498 1280 1594 965 2194 "pin3" "3" "square"] + Pad[4497 3839 6800 3839 1594 965 2194 "pin5" "5" "square,edge2"] + Pad[-6801 3839 -4498 3839 1594 965 2194 "pin4" "4" "square"] + Pad[747 -2391 3641 -2391 3898 -3011 4498 "pin8" "8" "square,edge2"] + Pad[747 2392 3641 2392 3898 -3011 4498 "pin5" "5" "square,edge2"] + ElementLine [-6496 -6495 6495 -6495 1000] + ElementLine [-6496 -6495 -6496 6496 1000] + ElementLine [-6496 6496 6495 6496 1000] + ElementLine [6495 -6495 6495 6496 1000] + ElementArc [-9118 -5117 500 500 270 360 1000] + + ) + +Element["hidename" "1212-8" "Q1" "Si7232DN" 64200 35600 10161 12011 2 100 ""] +( + Pad[3838 4497 3838 6800 1594 965 2194 "pin8" "8" "square,edge2"] + Pad[3838 -6801 3838 -4498 1594 965 2194 "pin1" "1" "square"] + Pad[1279 4497 1279 6800 1594 965 2194 "pin7" "7" "square,edge2"] + Pad[1279 -6801 1279 -4498 1594 965 2194 "pin2" "2" "square"] + Pad[-1280 4497 -1280 6800 1594 965 2194 "pin6" "6" "square,edge2"] + Pad[-1280 -6801 -1280 -4498 1594 965 2194 "pin3" "3" "square"] + Pad[-3839 4497 -3839 6800 1594 965 2194 "pin5" "5" "square,edge2"] + Pad[-3839 -6801 -3839 -4498 1594 965 2194 "pin4" "4" "square"] + Pad[2391 747 2391 3641 3898 -3011 4498 "pin8" "8" "square,edge2"] + Pad[-2392 747 -2392 3641 3898 -3011 4498 "pin5" "5" "square,edge2"] + ElementLine [6495 -6496 6495 6495 1000] + ElementLine [-6496 -6496 6495 -6496 1000] + ElementLine [-6496 -6496 -6496 6495 1000] + ElementLine [-6496 6495 6495 6495 1000] + ElementArc [5117 -9118 500 500 180 360 1000] + + ) + +Element["hidename" "0402" "R10" "549" 71826 61200 -4424 -7050 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R4" "3.3k" 63478 61200 -10698 -2950 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R3" "3.3k" 63452 67700 -9909 -2850 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R9" "549" 71826 67700 -4750 -7150 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C22" "0.1uF" 137374 32100 -3150 -3150 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C20" "0.22uF" 113900 29700 -3150 -3150 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C21" "4.7uF" 112400 35726 3150 -3150 3 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "LPCC16" "U9" "HMC5883L" 125500 38100 0 0 1 100 ""] +( + Pad[-5314 2952 -4723 2952 1181 787 1575 "pin12" "12" "square"] + Pad[4724 2952 5315 2952 1181 787 1575 "pin1" "1" "square,edge2"] + Pad[-2952 -5315 -2952 -4724 1181 787 1575 "pin8" "8" "square"] + Pad[-2952 4723 -2952 5314 1181 787 1575 "pin13" "13" "square,edge2"] + Pad[-5314 983 -4723 983 1181 787 1575 "pin11" "11" "square"] + Pad[4724 983 5315 983 1181 787 1575 "pin2" "2" "square,edge2"] + Pad[-983 -5315 -983 -4724 1181 787 1575 "pin7" "7" "square"] + Pad[-983 4723 -983 5314 1181 787 1575 "pin14" "14" "square,edge2"] + Pad[-5314 -984 -4723 -984 1181 787 1575 "pin10" "10" "square"] + Pad[4724 -984 5315 -984 1181 787 1575 "pin3" "3" "square,edge2"] + Pad[984 -5315 984 -4724 1181 787 1575 "pin6" "6" "square"] + Pad[984 4723 984 5314 1181 787 1575 "pin15" "15" "square,edge2"] + Pad[-5314 -2953 -4723 -2953 1181 787 1575 "pin9" "9" "square"] + Pad[4724 -2953 5315 -2953 1181 787 1575 "pin4" "4" "square,edge2"] + Pad[2953 -5315 2953 -4724 1181 787 1575 "pin5" "5" "square"] + Pad[2953 4723 2953 5314 1181 787 1575 "pin16" "16" "square,edge2"] + ElementArc [5906 5905 500 500 90 360 1000] + + ) + +Element["hidename" "0402" "R900" "1.8k" 122278 50600 3150 3150 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R901" "1.8k" 137226 41900 -3150 -3150 0 100 ""] +( + Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"] + Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R55" "22" 137326 27700 3150 3150 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R54" "22" 137326 23800 3150 3150 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "8ufson2x2" "U15" "LM293" 59035 107947 0 0 1 100 ""] +( + Pad[3150 2953 4921 2953 1181 2362 2362 "1" "1" "square,edge2"] + Pad[-4921 -2953 -3150 -2953 1181 2362 2362 "5" "5" "square"] + Pad[3150 984 4921 984 1181 2362 2362 "2" "2" "square,edge2"] + Pad[-4921 -984 -3150 -984 1181 2362 2362 "6" "6" "square"] + Pad[3150 -984 4921 -984 1181 2362 2362 "3" "3" "square,edge2"] + Pad[-4921 984 -3150 984 1181 2362 2362 "7" "7" "square"] + Pad[3150 -2953 4921 -2953 1181 2362 2362 "4" "4" "square,edge2"] + Pad[-4921 2953 -3150 2953 1181 2362 2362 "8" "8" "square"] + Pad[0 -2264 0 2264 1772 2362 2953 "GND" "GND" "square"] + ElementLine [-3937 -3937 -3937 3937 1000] + ElementLine [-3937 -3937 3937 -3937 1000] + ElementLine [3937 -3937 3937 3937 1000] + ElementLine [-3937 3937 3937 3937 1000] + ElementLine [3937 5118 3937 5118 1000] + + ) + +Element["hidename" "8ufson2x2" "U14" "LM293" 50500 62500 0 0 2 100 ""] +( + Pad[2953 -4921 2953 -3150 1181 2362 2362 "1" "1" "square"] + Pad[-2953 3150 -2953 4921 1181 2362 2362 "5" "5" "square,edge2"] + Pad[984 -4921 984 -3150 1181 2362 2362 "2" "2" "square"] + Pad[-984 3150 -984 4921 1181 2362 2362 "6" "6" "square,edge2"] + Pad[-984 -4921 -984 -3150 1181 2362 2362 "3" "3" "square"] + Pad[984 3150 984 4921 1181 2362 2362 "7" "7" "square,edge2"] + Pad[-2953 -4921 -2953 -3150 1181 2362 2362 "4" "4" "square"] + Pad[2953 3150 2953 4921 1181 2362 2362 "8" "8" "square,edge2"] + Pad[-2264 0 2264 0 1772 2362 2953 "GND" "GND" "square"] + ElementLine [-3937 3937 3937 3937 1000] + ElementLine [-3937 -3937 -3937 3937 1000] + ElementLine [-3937 -3937 3937 -3937 1000] + ElementLine [3937 -3937 3937 3937 1000] + ElementLine [5118 -3937 5118 -3937 1000] + + ) + +Element["hidename" "powerdi123" "D3" "DFLS130L" 30000 90560 0 0 3 100 ""] +( + Pad[0 2165 0 5315 5512 2362 6693 "cathode" "2" "square,edge2"] + Pad[-984 -6299 984 -6299 3543 2362 4724 "anode" "1" "square"] + ElementLine [3799 -5906 3799 5906 1000] + ElementLine [-3799 5906 3799 5906 1000] + ElementLine [-3799 -5906 -3799 5906 1000] + ElementLine [-3799 -5906 3799 -5906 1000] + ElementLine [3799 8009 3799 9908 1000] + ElementLine [-3799 9908 3799 9908 1000] + ElementLine [-3799 8009 -3799 9908 1000] + + ) + +Element["hidename" "0402" "R36" "10k" 38400 106900 -3150 3150 1 100 ""] +( + Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R37" "8.06k" 38400 113274 -3150 3150 1 100 ""] +( + Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R38" "10k" 37126 19300 3150 3150 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R39" "9.09k" 43674 19300 3150 3150 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "SOT23-5" "U1" "TC2185-3.3" 44300 28500 7300 4700 2 89 ""] +( + Attribute("author" "DJ Delorie") + Attribute("copyright" "2006 DJ Delorie") + Attribute("use-license" "Unlimited") + Attribute("dist-license" "GPL") + Pad[0 -800 0 800 2400 3000 3000 "BY" "4" "square"] + Pad[-7800 -800 -7800 800 2400 3000 3000 "VOUT" "5" "square"] + Pad[-7800 7400 -7800 9000 2400 3000 3000 "VIN" "1" "square,edge2"] + Pad[-3900 7400 -3900 9000 2400 3000 3000 "GND" "2" "square,edge2"] + Pad[0 7400 0 9000 2400 3000 3000 "EN" "3" "square,edge2"] + ElementLine [2000 -2900 2000 11000 1000] + ElementLine [-9800 -2900 2000 -2900 1000] + ElementLine [-9800 -2900 -9800 11000 1000] + ElementLine [-9800 11000 2000 11000 1000] + + ) + +Element["hidename" "0402" "C38" "10nF" 43674 23200 11776 2350 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C37" "1uF" 37100 23200 -1050 3150 2 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "8ufson2x2" "U13" "LM293" 60100 8800 0 0 3 100 ""] +( + Pad[-4921 -2953 -3150 -2953 1181 2362 2362 "1" "1" "square"] + Pad[3150 2953 4921 2953 1181 2362 2362 "5" "5" "square,edge2"] + Pad[-4921 -984 -3150 -984 1181 2362 2362 "2" "2" "square"] + Pad[3150 984 4921 984 1181 2362 2362 "6" "6" "square,edge2"] + Pad[-4921 984 -3150 984 1181 2362 2362 "3" "3" "square"] + Pad[3150 -984 4921 -984 1181 2362 2362 "7" "7" "square,edge2"] + Pad[-4921 2953 -3150 2953 1181 2362 2362 "4" "4" "square"] + Pad[3150 -2953 4921 -2953 1181 2362 2362 "8" "8" "square,edge2"] + Pad[0 -2264 0 2264 1772 2362 2953 "GND" "GND" "square,edge2"] + ElementLine [3937 -3937 3937 3937 1000] + ElementLine [-3937 3937 3937 3937 1000] + ElementLine [-3937 -3937 -3937 3937 1000] + ElementLine [-3937 -3937 3937 -3937 1000] + ElementLine [-3937 -5118 -3937 -5118 1000] + + ) + +Element["hidename" "lqfp100" "U7" "STM32L151VCT6" 183000 62500 -2700 -8600 0 100 ""] +( + Pad[23621 28739 23621 32282 1181 787 1811 "PA2/USART2_TX/ADC_IN2/TIM2_CH3/TIM9_CH1" "25" "square,edge2"] + Pad[23621 -32283 23621 -28740 1181 787 1811 "PB12/SPI2_NSS/I2C2_SMBA/USART3_CKI/ADC_IN18/TIM10_CH1" "51" "square"] + Pad[-32283 23621 -28740 23621 1181 787 1811 "VDD3" "100" "square"] + Pad[28739 23621 32282 23621 1181 787 1811 "PA3/USART2_RX/ADC_IN3/TIM2_CH4/TIM9_CH2" "26" "square,edge2"] + Pad[21653 28739 21653 32282 1181 787 1811 "PA1/USART2_RTS/ADC_IN1/TIM2_CH2" "24" "square,edge2"] + Pad[21653 -32283 21653 -28740 1181 787 1811 "PB13/SPI2_SCK/USART3_CTS/ADC_IN19/TIM9_CH1" "52" "square"] + Pad[-32283 21653 -28740 21653 1181 787 1811 "VSS3" "99" "square"] + Pad[28739 21653 32282 21653 1181 787 1811 "VSS4" "27" "square,edge2"] + Pad[19684 28739 19684 32282 1181 787 1811 "PA0/WKUP1/USART2_CTS/ADC_IN0/TIM2_CH1_ETR" "23" "square,edge2"] + Pad[19684 -32283 19684 -28740 1181 787 1811 "PB14/SPI2_MISO/USART3_RTS/ADC_IN20/TIM9_CH2" "53" "square"] + Pad[-32283 19684 -28740 19684 1181 787 1811 "PE1/TIM11_CH1" "98" "square"] + Pad[28739 19684 32282 19684 1181 787 1811 "VDD4" "28" "square,edge2"] + Pad[17716 28739 17716 32282 1181 787 1811 "VDDA" "22" "square,edge2"] + Pad[17716 -32283 17716 -28740 1181 787 1811 "PB15/SPI2_MOSI/ADC_IN21/TIM11_CH1/RTC_50_60HZ" "54" "square"] + Pad[-32283 17716 -28740 17716 1181 787 1811 "PE0/TIM4_ETR/TIM10_CH1" "97" "square"] + Pad[28739 17716 32282 17716 1181 787 1811 "PA4/SPI1_NSS/USART2_CK/ADC_IN4/DAC_OUT1" "29" "square,edge2"] + Pad[15747 28739 15747 32282 1181 787 1811 "VREF+" "21" "square,edge2"] + Pad[15747 -32283 15747 -28740 1181 787 1811 "PD8/USART3_TX" "55" "square"] + Pad[-32283 15747 -28740 15747 1181 787 1811 "PB9/TIM4_CH4/I2C1_SDA/TIM11_CH1" "96" "square"] + Pad[28739 15747 32282 15747 1181 787 1811 "PA5/SPI1_SCK/ADC_IN5/DAC_OUT2/TIM2_CH1_ETR" "30" "square,edge2"] + Pad[13779 28739 13779 32282 1181 787 1811 "VREF-" "20" "square,edge2"] + Pad[13779 -32283 13779 -28740 1181 787 1811 "PD9/USART3_RX" "56" "square"] + Pad[-32283 13779 -28740 13779 1181 787 1811 "PB8/TIM4_CH3/I2C1_SCL/TIM10_CH1" "95" "square"] + Pad[28739 13779 32282 13779 1181 787 1811 "PA6/SPI1_MISO_ADC_IN6/TIM3_CH1/TIM10_CH1" "31" "square,edge2"] + Pad[11810 28739 11810 32282 1181 787 1811 "VSSA" "19" "square,edge2"] + Pad[11810 -32283 11810 -28740 1181 787 1811 "PD10/USART3_CK" "57" "square"] + Pad[-32283 11810 -28740 11810 1181 787 1811 "BOOT0" "94" "square"] + Pad[28739 11810 32282 11810 1181 787 1811 "PA7/SPI1_MOSI/ADC_IN7/TIM3_CH2/TIM11_CH1" "32" "square,edge2"] + Pad[9842 28739 9842 32282 1181 787 1811 "PC3/ADC_IN13" "18" "square,edge2"] + Pad[9842 -32283 9842 -28740 1181 787 1811 "PD11/USART3_CTS" "58" "square"] + Pad[-32283 9842 -28740 9842 1181 787 1811 "PB7/I2C1_SDA/TIM4_CH2/USART1_RX/PVD_IN" "93" "square"] + Pad[28739 9842 32282 9842 1181 787 1811 "PC4/ADC_IN14" "33" "square,edge2"] + Pad[7873 28739 7873 32282 1181 787 1811 "PC2/ADC_IN12" "17" "square,edge2"] + Pad[7873 -32283 7873 -28740 1181 787 1811 "PD12/TIM4_CH1/USART3_RTS" "59" "square"] + Pad[-32283 7873 -28740 7873 1181 787 1811 "PB6/I2C1_SCL/TIM4_CH1/USART1_TX" "92" "square"] + Pad[28739 7873 32282 7873 1181 787 1811 "PC5/ADC_IN15" "34" "square,edge2"] + Pad[5905 28739 5905 32282 1181 787 1811 "PC1/ADC_IN11" "16" "square,edge2"] + Pad[5905 -32283 5905 -28740 1181 787 1811 "PD13/TIM4_CH2" "60" "square"] + Pad[-32283 5905 -28740 5905 1181 787 1811 "PB5/I2C1_SMBA/TIM3_CH2/SPI1_MOSI" "91" "square"] + Pad[28739 5905 32282 5905 1181 787 1811 "PB0/ADC_IN8/TIM3_CH3/VREF_OUT" "35" "square,edge2"] + Pad[3936 28739 3936 32282 1181 787 1811 "PC0/ADC_IN10" "15" "square,edge2"] + Pad[3936 -32283 3936 -28740 1181 787 1811 "PD14_TIM4_CH3" "61" "square"] + Pad[-32283 3936 -28740 3936 1181 787 1811 "PB4/JNTRSTSPI1_MISO/TIM3_CH1" "90" "square"] + Pad[28739 3936 32282 3936 1181 787 1811 "PB1/ADC_IN9/TIM3_CH4/VREF_OUT" "36" "square,edge2"] + Pad[1968 28739 1968 32282 1181 787 1811 "NRST" "14" "square,edge2"] + Pad[1968 -32283 1968 -28740 1181 787 1811 "PD15/TIM4_CH4" "62" "square"] + Pad[-32283 1968 -28740 1968 1181 787 1811 "PB3/JTDO/TIM2_CH2/TRACESWO/SPI1_SCK" "89" "square"] + Pad[28739 1968 32282 1968 1181 787 1811 "PB2/BOOT1" "37" "square,edge2"] + Pad[0 28739 0 32282 1181 787 1811 "PH1/OSC_OUT" "13" "square,edge2"] + Pad[0 -32283 0 -28740 1181 787 1811 "PC6/TIM3_CH1" "63" "square"] + Pad[-32283 0 -28740 0 1181 787 1811 "PD7/USART2_CK/TIM9_CH2" "88" "square"] + Pad[28739 0 32282 0 1181 787 1811 "PE7/ADC_IN22" "38" "square,edge2"] + Pad[-1969 28739 -1969 32282 1181 787 1811 "PH0/OSC_IN" "12" "square,edge2"] + Pad[-1969 -32283 -1969 -28740 1181 787 1811 "PC7/TIM3_CH2" "64" "square"] + Pad[-32283 -1969 -28740 -1969 1181 787 1811 "PD6/USART2_RX" "87" "square"] + Pad[28739 -1969 32282 -1969 1181 787 1811 "PE8/ADC_IN23" "39" "square,edge2"] + Pad[-3937 28739 -3937 32282 1181 787 1811 "VDD5" "11" "square,edge2"] + Pad[-3937 -32283 -3937 -28740 1181 787 1811 "PC8/TIM3_CH3" "65" "square"] + Pad[-32283 -3937 -28740 -3937 1181 787 1811 "PD5/USART2_TX" "86" "square"] + Pad[28739 -3937 32282 -3937 1181 787 1811 "PE9/ADC_IN24/TIM2_CH1_ETR" "40" "square,edge2"] + Pad[-5906 28739 -5906 32282 1181 787 1811 "VSS5" "10" "square,edge2"] + Pad[-5906 -32283 -5906 -28740 1181 787 1811 "PC9/TIM3_CH4" "66" "square"] + Pad[-32283 -5906 -28740 -5906 1181 787 1811 "PD4_USART2_RTS/SPI2_MOSI" "85" "square"] + Pad[28739 -5906 32282 -5906 1181 787 1811 "PE10/ADC_IN25/TIM2_CH2" "41" "square,edge2"] + Pad[-7874 28739 -7874 32282 1181 787 1811 "PC15/OSC32_OUT" "9" "square,edge2"] + Pad[-7874 -32283 -7874 -28740 1181 787 1811 "PA8/USART1_CK/MCO" "67" "square"] + Pad[-32283 -7874 -28740 -7874 1181 787 1811 "PD3/USART2_CTS/SPI2_MISO" "84" "square"] + Pad[28739 -7874 32282 -7874 1181 787 1811 "PE11/TIM2_CH3" "42" "square,edge2"] + Pad[-9843 28739 -9843 32282 1181 787 1811 "PC14/OSC32_IN" "8" "square,edge2"] + Pad[-9843 -32283 -9843 -28740 1181 787 1811 "PA9/USART1_TX" "68" "square"] + Pad[-32283 -9843 -28740 -9843 1181 787 1811 "PD2/TIM3_ETR" "83" "square"] + Pad[28739 -9843 32282 -9843 1181 787 1811 "PE12/TIM2_CH4/SPI1_NSS" "43" "square,edge2"] + Pad[-11811 28739 -11811 32282 1181 787 1811 "PC13/RTC_AF1/WKUP2" "7" "square,edge2"] + Pad[-11811 -32283 -11811 -28740 1181 787 1811 "PA10/USART1_RX" "69" "square"] + Pad[-32283 -11811 -28740 -11811 1181 787 1811 "PD1/SPI2_SCK" "82" "square"] + Pad[28739 -11811 32282 -11811 1181 787 1811 "PE13/SPI1_SCK" "44" "square,edge2"] + Pad[-13780 28739 -13780 32282 1181 787 1811 "VLCD" "6" "square,edge2"] + Pad[-13780 -32283 -13780 -28740 1181 787 1811 "PA11/USART1_CTS/USBDM/SPI1_MISO" "70" "square"] + Pad[-32283 -13780 -28740 -13780 1181 787 1811 "PD0/SPI2_NSS/TIM9_CH1" "81" "square"] + Pad[28739 -13780 32282 -13780 1181 787 1811 "PE14/SPI1_MISO" "45" "square,edge2"] + Pad[-15748 28739 -15748 32282 1181 787 1811 "PE6/TRACED3/WKUP3/TIM9_CH2" "5" "square,edge2"] + Pad[-15748 -32283 -15748 -28740 1181 787 1811 "PA12/USART1_RTS/USBDP/SPI1_MOSI" "71" "square"] + Pad[-32283 -15748 -28740 -15748 1181 787 1811 "PC12/USART3_CK" "80" "square"] + Pad[28739 -15748 32282 -15748 1181 787 1811 "PE15/SPI1_MOSI" "46" "square,edge2"] + Pad[-17717 28739 -17717 32282 1181 787 1811 "PE5/TRACED2/TIM9_CH1" "4" "square,edge2"] + Pad[-17717 -32283 -17717 -28740 1181 787 1811 "PA13/JTMS/SWDIO" "72" "square"] + Pad[-32283 -17717 -28740 -17717 1181 787 1811 "PC11/USART3_RX" "79" "square"] + Pad[28739 -17717 32282 -17717 1181 787 1811 "PB10/I2C2_SCL/USART3_TX/TIM2_CH3" "47" "square,edge2"] + Pad[-19685 28739 -19685 32282 1181 787 1811 "PE4/TRACED1/TIM3_CH2" "3" "square,edge2"] + Pad[-19685 -32283 -19685 -28740 1181 787 1811 "PH2/I2C2_SMBA" "73" "square"] + Pad[-32283 -19685 -28740 -19685 1181 787 1811 "PC10/USART3_TX" "78" "square"] + Pad[28739 -19685 32282 -19685 1181 787 1811 "PB11/I2C2_SDA/USART3_RX/TIM2_CH4" "48" "square,edge2"] + Pad[-21654 28739 -21654 32282 1181 787 1811 "PE3/TRACED0/TIM3_CH1" "2" "square,edge2"] + Pad[-21654 -32283 -21654 -28740 1181 787 1811 "VSS2" "74" "square"] + Pad[-32283 -21654 -28740 -21654 1181 787 1811 "PA15/JTDI/TIM2_CH1_ETR/SPI1_NSS" "77" "square"] + Pad[28739 -21654 32282 -21654 1181 787 1811 "VSS1" "49" "square,edge2"] + Pad[-23622 28739 -23622 32282 1181 787 1811 "PE2/TRACECK/TIM3_ETR" "1" "square,edge2"] + Pad[-23622 -32283 -23622 -28740 1181 787 1811 "VDD2" "75" "square"] + Pad[-32283 -23622 -28740 -23622 1181 787 1811 "PA14/JTCK/SWCLK" "76" "square"] + Pad[28739 -23622 32282 -23622 1181 787 1811 "VDD1" "50" "square,edge2"] + ElementLine [27558 -27559 27558 27558 1000] + ElementLine [-27559 -27559 27558 -27559 1000] + ElementLine [-27559 -27559 -27559 27558 1000] + ElementLine [-27559 27558 27558 27558 1000] + ElementArc [-28740 28739 500 500 180 360 1000] + + ) + +Element["hidename" "1206" "C39" "47uF" 38500 90300 3150 -3150 3 100 ""] +( + Pad[-1181 -5905 1181 -5905 5118 2000 5718 "1" "1" "square"] + Pad[-1181 5905 1181 5905 5118 2000 5718 "2" "2" "square"] + ElementLine [3740 -2362 3740 2362 800] + ElementLine [-3740 -2362 -3740 2362 800] + + ) + +Element["hidename" "0402" "R25" "5.6k" 241874 69900 -4850 950 0 100 ""] +( + Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"] + Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "C10" "0.1uF" 244700 87700 3350 7972 3 100 ""] +( + Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "0402" "R26" "10k" 244700 77226 3150 3472 3 100 ""] +( + Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"] + Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"] + + ) + +Element["hidename" "MS5607" "U4" "MS5607" 235900 82800 3011 11139 3 100 ""] +( + Pad[-5314 7381 -3345 7381 2362 2559 2962 "SCLK" "8" "square"] + Pad[3346 7381 5315 7381 2362 2559 2962 "VDD" "1" "square,edge2"] + Pad[-5314 2460 -3345 2460 2362 2559 2962 "SDI/SDA" "7" "square"] + Pad[3346 2460 5315 2460 2362 2559 2962 "PS" "2" "square,edge2"] + Pad[-5314 -2461 -3345 -2461 2362 2559 2962 "SDO" "6" "square"] + Pad[3346 -2461 5315 -2461 2362 2559 2962 "GND" "3" "square,edge2"] + Pad[-5314 -7382 -3345 -7382 2362 2559 2962 "CSB" "5" "square"] + Pad[3346 -7382 5315 -7382 2362 2559 2962 "CSB" "4" "square,edge2"] + ElementLine [-5905 9842 5906 9842 1000] + ElementLine [5906 -9843 5906 9842 1000] + ElementLine [-5905 -9843 5906 -9843 1000] + ElementLine [-5905 -9843 -5905 9842 1000] + ElementArc [7579 8611 500 500 90 360 1000] + + ) +Rat[230586 80339 0 215282 76279 0 ""] +Rat[230586 85260 0 215282 74310 0 ""] +Rat[230586 90181 0 215282 78247 0 ""] +Rat[230586 75418 0 215282 72342 0 ""] +Rat[243448 69507 0 215282 68405 0 ""] +Rat[214950 71750 3 237100 69900 1 ""] +Layer(1 "top") +( + Line[94200 75400 94200 65000 4000 2000 ""] + Line[34200 75400 44300 49600 4000 2000 ""] + Line[94300 59900 100226 59900 1000 2000 "clearline"] + Line[100226 59900 100326 60000 1000 2000 "clearline"] + Line[103474 60000 108652 60000 1000 2000 "clearline"] + Line[108652 60000 108752 60100 1000 2000 "clearline"] + Line[108726 65000 103500 65000 1000 2000 "clearline"] + Line[100352 65000 94300 65000 1000 2000 "clearline"] + Line[94300 65000 94200 64900 1000 2000 "clearline"] + Line[111900 60100 111900 60300 1000 2000 "clearline"] + Line[111900 60300 114200 62600 1000 2000 "clearline"] + Line[111874 65000 111874 64926 1000 2000 "clearline"] + Line[111874 64926 114200 62600 1000 2000 "clearline"] + Line[24200 41600 24200 49500 2500 2000 "clearline"] + Line[24200 49500 24300 49600 2500 2000 "clearline"] + Line[108882 18000 108882 24762 1000 2000 "clearline"] + Line[145746 13498 146100 13852 1000 2000 "clearline"] + Line[145746 9908 145746 13498 1000 2000 "clearline"] + Line[142400 13526 142100 13826 1000 2000 "clearline"] + Line[142400 9908 142400 13526 1000 2000 "clearline"] + Line[142400 4200 145746 4200 1000 2000 "clearline"] + Line[141100 5500 142400 4200 1000 2000 "clearline"] + Line[138800 5500 141100 5500 1000 2000 "clearline"] + Line[12300 76900 16400 76900 2500 2000 "clearline"] + Line[16400 73000 21800 73000 2500 2000 "clearline"] + Line[21800 73000 24200 75400 2500 2000 "clearline"] + Line[12248 85200 12248 76948 1000 2000 "clearline"] + Line[12248 76948 12200 76900 1000 2000 "clearline"] + Line[9100 85200 9100 81700 1000 2000 "clearline"] + Line[9100 81700 8200 80800 1000 2000 "clearline"] + Line[2900 73252 7948 73252 1000 2000 "clearline"] + Line[7948 73252 8200 73000 1000 2000 "clearline"] + Line[8708 93100 10900 93100 1000 2000 "clearline"] + Line[10900 93100 16400 87600 1000 2000 "clearline"] + Line[16400 87600 16400 80800 1000 2000 "clearline"] + Line[2900 76400 2900 81100 1000 2000 "clearline"] + Line[2900 81100 6600 84800 1000 2000 "clearline"] + Line[6600 84800 6600 87646 1000 2000 "clearline"] + Line[6600 87646 8708 89754 1000 2000 "clearline"] + Line[35300 76500 34200 75400 2500 2000 "clearline"] + Line[24200 69148 24200 75400 1000 2000 "clearline"] + Line[24200 66000 24200 62500 1000 2000 "clearline"] + Line[213510 40846 219446 40846 1000 2000 "clearline"] + Line[219446 40846 219500 40900 1000 2000 "clearline"] + Line[213510 38878 217422 38878 1000 2000 "clearline"] + Line[217422 38878 219500 36800 1000 2000 "clearline"] + Line[159378 31988 156000 29600 1000 2000 "clearline"] + Line[194810 93010 194810 96810 1000 2000 "clearline"] + Line[194810 96810 195800 97800 1000 2000 "clearline"] + Line[196779 93010 196779 96821 1000 2000 "clearline"] + Line[196779 96821 195800 97800 1000 2000 "clearline"] + Line[177094 93010 177094 97794 1000 2000 "clearline"] + Line[177094 97794 177100 97800 1000 2000 "clearline"] + Line[205953 118647 203179 118647 1000 2000 "clearline"] + Line[203179 118647 199953 115421 1000 2000 "clearline"] + Line[221700 109200 224580 109200 1000 2000 "clearline"] + Line[224580 109200 227653 112273 1000 2000 "clearline"] + Line[221700 118647 227553 118647 1000 2000 "clearline"] + Line[227653 115421 227653 118547 1000 2000 "clearline"] + Line[227553 118647 227653 118547 1000 2000 "clearline"] + Line[199953 112273 199953 109247 1000 2000 "clearline"] + Line[199953 109247 200000 109200 1000 2000 "clearline"] + Line[205953 109200 200000 109200 1000 2000 "clearline"] + Line[181031 93010 181031 97931 1000 2000 "clearline"] + Line[181031 97931 188200 105100 1000 2000 "clearline"] + Line[188200 105100 210400 105100 1000 2000 "clearline"] + Line[210400 105100 212000 106700 1000 2000 "clearline"] + Line[212000 106700 212000 115400 1000 2000 "clearline"] + Line[212000 115400 209800 117600 1000 2000 "clearline"] + Line[209800 117600 207000 117600 1000 2000 "clearline"] + Line[207000 117600 205953 118647 1000 2000 "clearline"] + Line[183000 93010 183000 97200 1000 2000 "clearline"] + Line[183000 97200 188900 103100 1000 2000 "clearline"] + Line[188900 103100 215600 103100 1000 2000 "clearline"] + Line[198747 93010 198747 100347 1000 2000 "clearline"] + Line[198747 100347 198800 100400 1000 2000 "clearline"] + Line[203252 100200 199000 100200 1000 2000 "clearline"] + Line[200716 93010 200716 95916 1000 2000 "clearline"] + Line[200716 95916 202100 97300 1000 2000 "clearline"] + Line[202100 97300 205700 97300 1000 2000 "clearline"] + Line[205700 97300 206300 97900 1000 2000 "clearline"] + Line[206300 97900 206300 100100 1000 2000 "clearline"] + Line[206300 100100 206400 100200 1000 2000 "clearline"] + Line[206400 100200 209478 100200 1000 2000 "clearline"] + Line[209526 96400 209526 97074 1000 2000 "clearline"] + Line[209526 97074 206400 100200 1000 2000 "clearline"] + Line[212626 100200 214300 100200 1000 2000 "clearline"] + Line[214300 100200 216200 98300 1000 2000 "clearline"] + Line[212674 96400 214300 96400 1000 2000 "clearline"] + Line[214300 96400 216200 98300 1000 2000 "clearline"] + Line[191700 97400 195400 97400 1000 2000 "clearline"] + Line[195400 97400 195800 97800 1000 2000 "clearline"] + Line[213510 64468 219620 64468 1000 2000 "clearline"] + Line[219620 64468 219652 64500 1000 2000 "clearline"] + Line[222800 64500 226300 64500 1000 2000 "clearline"] + Line[161346 31988 161300 37700 1000 2000 "clearline"] + Line[165800 27500 159600 27500 1000 2000 "clearline"] + Line[159600 27500 158700 26600 1000 2000 "clearline"] + Line[115300 26600 114000 25300 1000 2000 "clearline"] + Line[114000 25300 114000 18000 1000 2000 "clearline"] + Line[171189 31988 171189 36711 1000 2000 "clearline"] + Line[171189 36711 170200 37700 1000 2000 "clearline"] + Line[173157 31988 173157 36757 1000 2000 "clearline"] + Line[173157 36757 174100 37700 1000 2000 "clearline"] + Line[112252 75500 104300 75500 1000 2000 "clearline"] + Line[104300 75500 104200 75400 1000 2000 "clearline"] + Line[115400 75500 121452 75500 1000 2000 "clearline"] + Line[121452 75500 121552 75400 1000 2000 "clearline"] + Line[124700 75400 132484 75400 1000 2000 "clearline"] + Line[135500 72384 132484 75400 1000 2000 "clearline"] + Line[24200 49700 19100 49700 1000 2000 "clearline"] + Line[19100 49700 18100 48700 1000 2000 "clearline"] + Line[117200 24700 116600 24100 1000 2000 "clearline"] + Line[116600 24100 116600 18042 1000 2000 "clearline"] + Line[116600 18042 116558 18000 1000 2000 "clearline"] + Line[144600 22800 142100 20300 1000 2000 "clearline"] + Line[142100 20300 142100 16974 1000 2000 "clearline"] + Line[152500 13000 148500 17000 1000 2000 "clearline"] + Line[148500 17000 146100 17000 1000 2000 "clearline"] + Line[152488 54626 196126 54626 1000 2000 "clearline"] + Line[196126 54626 196800 55300 1000 2000 "clearline"] + Line[183000 31988 183000 36300 1000 2000 "clearline"] + Line[183000 36300 178200 41100 1000 2000 "clearline"] + Line[178200 41100 168000 41100 1000 2000 "clearline"] + Line[168000 41100 162900 40600 1000 2000 "clearline"] + Line[167252 31988 167252 28952 1000 2000 "clearline"] + Line[167252 28952 165800 27500 1000 2000 "clearline"] + Line[2900 73252 2900 70248 1000 2000 "clearline"] + Line[2900 67100 2900 63700 1000 2000 "clearline"] + Line[119117 18000 119117 21517 1000 2000 "clearline"] + Line[119117 21517 120000 22400 1000 2000 "clearline"] + Line[5900 44500 5900 70700 1000 2000 "clearline"] + Line[5900 70700 8200 73000 1000 2000 "clearline"] + Line[29200 54600 29200 34500 1000 2000 "clearline"] + Line[29200 34500 28100 33400 1000 2000 "clearline"] + Line[152488 50689 177789 50689 1000 2000 "clearline"] + Line[177789 50689 177800 50700 1000 2000 "clearline"] + Line[180900 47700 168400 47700 1000 2000 "clearline"] + Line[168400 47700 167300 48800 1000 2000 "clearline"] + Line[167300 48800 152568 48800 1000 2000 "clearline"] + Line[152568 48800 152488 48720 1000 2000 "clearline"] + Line[108900 24792 108876 24768 1000 2000 "clearline"] + Line[152498 74300 152488 74310 1000 2000 "clearline"] + Line[152488 68405 157195 68405 1000 2000 "clearline"] + Line[157195 68405 159100 66500 1000 2000 "clearline"] + Line[159100 66500 159100 64200 1000 2000 "clearline"] + Line[177200 77700 177100 77600 1000 2000 "clearline"] + Line[177100 77600 199400 77600 1000 2000 "clearline"] + Line[152488 42815 157915 42815 1000 2000 "clearline"] + Line[157915 42815 158500 43400 1000 2000 "clearline"] + Line[158500 43400 202300 43400 1000 2000 "clearline"] + Line[181700 64500 197900 64500 1000 2000 "clearline"] + Line[179063 93010 179063 88837 1000 2000 "clearline"] + Line[179063 88837 179100 88800 1000 2000 "clearline"] + Line[206621 93010 206621 87421 1000 2000 "clearline"] + Line[206621 87421 203600 84400 1000 2000 "clearline"] + Line[203600 84400 202200 84400 1000 2000 "clearline"] + Line[202200 84400 201200 83500 1000 2000 "clearline"] + Line[196700 83500 197500 83900 1000 2000 "clearline"] + Line[197500 83900 199800 86200 1000 2000 "clearline"] + Line[199800 86200 202600 86200 1000 2000 "clearline"] + Line[202600 86200 204700 88300 1000 2000 "clearline"] + Line[204700 88300 204700 92964 1000 2000 "clearline"] + Line[204700 92964 204653 93010 1000 2000 "clearline"] + Line[202684 93010 202684 88784 1000 2000 "clearline"] + Line[202684 88784 201900 87900 1000 2000 "clearline"] + Line[201800 87900 199000 87900 1000 2000 "clearline"] + Line[199000 87900 197900 86800 1000 2000 "clearline"] + Line[197900 86800 195500 86800 1000 2000 "clearline"] + Line[195500 86800 192600 83900 1000 2000 "clearline"] + Line[202700 69300 197900 64500 1000 2000 "clearline"] + Line[202700 72400 202700 69300 1000 2000 "clearline"] + Line[213510 62500 204300 62500 1000 2000 "clearline"] + Line[204300 62500 203600 63200 1000 2000 "clearline"] + Line[213510 86121 207921 86121 1000 2000 "clearline"] + Line[207921 86121 206200 84400 1000 2000 "clearline"] + Line[213510 80216 210316 80216 1000 2000 "clearline"] + Line[210316 80216 208300 78200 1000 2000 "clearline"] + Line[213000 82184 208816 82184 1000 2000 "clearline"] + Line[208816 82184 208400 82600 1000 2000 "clearline"] + Line[180100 74600 203700 74600 1000 2000 "clearline"] + Line[94300 49600 94300 60000 4000 2000 ""] + Line[179063 88600 170400 88600 1000 2000 "clearline"] + Line[170400 88600 169200 89800 1000 2000 "clearline"] + Line[169200 89800 169200 92991 1000 2000 "clearline"] + Line[169200 92991 169220 93011 1000 2000 "clearline"] + Line[111268 122368 111300 122400 1000 2000 "clearline"] + Line[107332 105532 109300 107500 1000 2000 "clearline"] + Line[97900 113406 103394 113406 1000 2000 "clearline"] + Line[103394 113406 103788 113012 1000 2000 "clearline"] + Line[111268 122368 111268 114980 1000 2000 "clearline"] + Line[111268 114980 109300 113012 1000 2000 "clearline"] + Line[103300 92000 103300 101501 1000 2000 "clearline"] + Line[103300 101501 103788 101989 1000 2000 "clearline"] + Line[115200 92000 115200 101600 1000 2000 "clearline"] + Line[115200 101600 114811 101989 1000 2000 "clearline"] + Line[97981 113406 90006 113406 1000 2000 "clearline"] + Line[90006 113406 90000 113400 1000 2000 "clearline"] + Line[90000 113400 90000 101626 1000 2000 "clearline"] + Line[90000 101626 90026 101600 1000 2000 "clearline"] + Line[97981 109469 93205 109469 1000 2000 "clearline"] + Line[93205 109469 93174 109500 1000 2000 "clearline"] + Line[97981 101595 93179 101595 1000 2000 "clearline"] + Line[93179 101595 93174 101600 1000 2000 "clearline"] + Line[90000 105600 101888 105600 1000 2000 "clearline"] + Line[101888 105600 103788 107500 1000 2000 "clearline"] + Line[178800 103800 182500 107500 1000 2000 "clearline"] + Line[147420 99626 147420 97580 1000 2000 "clearline"] + Line[147420 97580 147900 97100 1000 2000 "clearline"] + Line[147900 97100 148500 97100 1000 2000 "clearline"] + Line[148500 97100 150500 99100 1000 2000 "clearline"] + Line[120618 101595 124395 101595 1000 2000 "clearline"] + Line[124395 101595 124400 101600 1000 2000 "clearline"] + Line[152489 56594 142706 56594 1000 2000 "clearline"] + Line[142706 56594 139100 60200 1000 2000 "clearline"] + Line[139100 60200 124400 60200 1000 2000 "clearline"] + Line[152489 60531 141669 60531 1000 2000 "clearline"] + Line[141669 60531 139600 62600 1000 2000 "clearline"] + Line[139600 62600 122400 62600 1000 2000 "clearline"] + Line[152489 62500 142800 62500 1000 2000 "clearline"] + Line[142800 62500 140800 64500 1000 2000 "clearline"] + Line[140800 64500 118000 64500 1000 2000 "clearline"] + Line[234401 43101 236900 45600 1000 2000 "clearline"] + Line[234401 31822 234401 43101 1000 2000 "clearline"] + Line[239400 48100 229401 38101 1000 2000 "clearline"] + Line[229401 31822 229401 38101 1000 2000 "clearline"] + Line[239400 48100 239400 59380 1000 2000 "clearline"] + Line[244400 53600 244400 59380 1000 2000 "clearline"] + Line[239400 31822 239400 27800 1000 2000 "clearline"] + Line[239400 27800 238300 26700 1000 2000 "clearline"] + Line[238300 26700 216400 26700 1000 2000 "clearline"] + Line[195100 5400 184600 5400 1000 2000 "clearline"] + Line[184600 5400 182500 7500 1000 2000 "clearline"] + Line[244400 31822 244400 27600 1000 2000 "clearline"] + Line[244400 27600 241400 24600 1000 2000 "clearline"] + Line[241400 24600 217300 24600 1000 2000 "clearline"] + Line[193900 2900 179700 2900 1000 2000 "clearline"] + Line[179700 2900 177500 5100 1000 2000 "clearline"] + Line[177500 5100 177500 17500 1000 2000 "clearline"] + Line[169220 31989 169220 28520 1000 2000 "clearline"] + Line[169220 28520 166500 25800 1000 2000 "clearline"] + Line[166500 25800 160800 25800 1000 2000 "clearline"] + Line[160800 25800 159700 24700 1000 2000 "clearline"] + Line[177094 31989 177094 29194 1000 2000 "clearline"] + Line[177094 29194 175700 27800 1000 2000 "clearline"] + Line[175700 27800 171000 27800 1000 2000 "clearline"] + Line[171000 27800 167300 24100 1000 2000 "clearline"] + Line[167300 24100 161500 24100 1000 2000 "clearline"] + Line[161500 24100 160200 22800 1000 2000 "clearline"] + Line[160200 22800 144600 22800 1000 2000 "clearline"] + Line[144600 22800 144550 22750 1000 2000 "clearline"] + Line[152450 13050 159750 13050 1000 2000 "clearline"] + Line[159750 13050 162500 15800 1000 2000 "clearline"] + Line[162500 15800 162500 19800 1000 2000 "clearline"] + Line[162500 19800 164800 22100 1000 2000 "clearline"] + Line[164800 22100 167800 22100 1000 2000 "clearline"] + Line[167800 22100 171800 26100 1000 2000 "clearline"] + Line[171800 26100 177000 26100 1000 2000 "clearline"] + Line[177000 26100 179100 28200 1000 2000 "clearline"] + Line[179100 28200 179100 31952 1000 2000 "clearline"] + Line[179100 31952 179063 31989 1000 2000 "clearline"] + Line[234401 59380 234401 47901 1000 2000 "clearline"] + Line[234401 47901 226600 40100 1000 2000 "clearline"] + Line[226600 40100 226600 36700 1000 2000 "clearline"] + Line[234300 59480 234401 59380 1000 2000 "clearline"] + Line[231400 7600 231500 7500 1000 2000 "clearline"] + Line[134626 108483 129117 108483 1000 2000 "clearline"] + Line[129117 108483 128600 109000 1000 2000 "clearline"] + Line[120618 113406 122932 113406 1000 2000 "clearline"] + Line[122932 113406 125026 115500 1000 2000 "clearline"] + Line[125026 115500 125026 119474 1000 2000 "clearline"] + Line[128600 112148 128600 115074 1000 2000 "clearline"] + Line[128600 115074 128174 115500 1000 2000 "clearline"] + Line[128174 115500 128174 119674 1000 2000 "clearline"] + Line[128174 119674 128600 120100 1000 2000 "clearline"] + Line[120618 105532 124568 105532 1000 2000 "clearline"] + Line[124568 105532 124600 105500 1000 2000 "clearline"] + Line[120618 109469 124569 109469 1000 2000 "clearline"] + Line[124569 109469 124600 109500 1000 2000 "clearline"] + Line[150373 102579 155579 102579 1000 2000 "clearline"] + Line[155579 102579 155600 102600 1000 2000 "clearline"] + Line[150373 104547 153647 104547 1000 2000 "clearline"] + Line[153647 104547 155600 106500 1000 2000 "clearline"] + Line[137579 115373 137579 120079 1000 2000 "clearline"] + Line[137579 120079 137600 120100 1000 2000 "clearline"] + Line[137600 120100 140926 120100 1000 2000 "clearline"] + Line[144074 120100 150726 120100 1000 2000 "clearline"] + Line[147420 115373 147420 119920 1000 2000 "clearline"] + Line[147420 119920 147600 120100 1000 2000 "clearline"] + Line[150373 110452 152652 110452 1000 2000 "clearline"] + Line[152652 110452 153800 111600 1000 2000 "clearline"] + Line[153800 111600 153800 120026 1000 2000 "clearline"] + Line[153800 120026 153874 120100 1000 2000 "clearline"] + Line[134626 106516 129816 106516 1000 2000 "clearline"] + Line[129816 106516 128300 105000 1000 2000 "clearline"] + Line[115205 118819 115205 120905 1000 2000 "clearline"] + Line[115205 120905 115900 121600 1000 2000 "clearline"] + Line[115900 121600 120900 121600 1000 2000 "clearline"] + Line[120900 121600 121600 120900 1000 2000 "clearline"] + Line[134626 104547 133047 104547 1000 2000 "clearline"] + Line[133047 104547 127500 99100 1000 2000 "clearline"] + Line[163315 89415 162900 89000 1000 2000 "clearline"] + Line[162900 89000 125900 89000 1000 2000 "clearline"] + Line[163315 93011 163315 89415 1000 2000 "clearline"] + Line[152489 84153 147853 84153 1000 2000 "clearline"] + Line[147853 84153 146900 83200 1000 2000 "clearline"] + Line[133400 120100 135000 118500 1000 2000 "clearline"] + Line[135000 118500 135000 115600 1000 2000 "clearline"] + Line[135100 115700 132900 113500 1000 2000 "clearline"] + Line[134626 112420 132880 112420 1000 2000 "clearline"] + Line[132880 112420 132800 112500 1000 2000 "clearline"] + Line[132800 112500 132800 113400 1000 2000 "clearline"] + Line[122400 95000 150600 95000 1000 2000 "clearline"] + Line[150600 95000 154600 99000 1000 2000 "clearline"] + Line[154600 99000 165900 99000 1000 2000 "clearline"] + Line[165900 99000 167300 97600 1000 2000 "clearline"] + Line[167300 97600 167300 93059 1000 2000 "clearline"] + Line[167300 93059 167252 93011 1000 2000 "clearline"] + Line[123100 93300 151400 93300 1000 2000 "clearline"] + Line[151400 93300 155400 97300 1000 2000 "clearline"] + Line[155400 97300 163800 97300 1000 2000 "clearline"] + Line[163800 97300 165300 95800 1000 2000 "clearline"] + Line[165300 95800 165300 93028 1000 2000 "clearline"] + Line[165300 93028 165283 93011 1000 2000 "clearline"] + Line[152489 38878 148478 38878 1000 2000 "clearline"] + Line[148478 38878 147600 38000 1000 2000 "clearline"] + Line[165283 31989 165283 36983 1000 2000 "clearline"] + Line[165283 36983 165300 37000 1000 2000 "clearline"] + Line[178900 100326 178900 99200 1000 2000 "clearline"] + Line[178900 99200 177500 97800 1000 2000 "clearline"] + Line[177500 117500 177500 106300 1000 2000 "clearline"] + Line[177500 106300 171800 100600 1000 2000 "clearline"] + Line[171800 100600 171800 97800 1000 2000 "clearline"] + Line[196700 4000 217300 24600 1000 2000 "clearline"] + Line[192800 5400 195100 5400 1000 2000 "clearline"] + Line[195100 5400 216300 26700 1000 2000 "clearline"] + Line[193400 2900 195600 2900 1000 2000 "clearline"] + Line[195600 2900 196750 4050 1000 2000 "clearline"] + Line[203800 18000 214200 28400 1000 2000 "clearline"] + Line[203800 18000 201574 18000 1000 2000 "clearline"] + Line[198426 18000 195448 18000 1000 2000 "clearline"] + Line[192300 18000 188000 18000 1000 2000 "clearline"] + Line[188000 18000 187500 17500 1000 2000 "clearline"] + Line[202684 31989 202684 24584 1000 2000 "clearline"] + Line[202684 24584 198500 20400 1000 2000 "clearline"] + Line[198500 20400 198500 18074 1000 2000 "clearline"] + Line[198500 18074 198426 18000 1000 2000 "clearline"] + Line[200716 31989 200716 28016 1000 2000 "clearline"] + Line[200716 28016 198700 26000 1000 2000 "clearline"] + Line[198700 26000 197174 26000 1000 2000 "clearline"] + Line[194026 26000 187600 26000 1000 2000 "clearline"] + Line[187600 26000 187500 25900 1000 2000 "clearline"] + Line[187500 25900 182400 25900 1000 2000 "clearline"] + Line[182400 25900 177400 20900 1000 2000 "clearline"] + Line[177400 20900 177400 17600 1000 2000 "clearline"] + Line[177400 17600 177500 17500 1000 2000 "clearline"] + Line[187500 22752 187500 17500 1000 2000 "clearline"] + Line[214400 28400 224500 28400 1000 2000 "clearline"] + Line[224500 28400 226600 30500 1000 2000 "clearline"] + Line[226600 30500 226600 36900 1000 2000 "clearline"] + Line[204653 31989 204653 28647 1000 2000 "clearline"] + Line[204653 28647 205400 27900 1000 2000 "clearline"] + Line[205400 27900 210200 27900 1000 2000 "clearline"] + Line[210200 27900 210900 28600 1000 2000 "clearline"] + Line[210900 28600 210900 31874 1000 2000 "clearline"] + Line[210900 31874 211026 32000 1000 2000 "clearline"] + Line[214174 32000 219552 32000 1000 2000 "clearline"] + Line[222700 32000 222700 38000 1000 2000 "clearline"] + Line[222700 38000 219800 40900 1000 2000 "clearline"] + Line[223600 39426 221274 39426 1000 2000 "clearline"] + Line[221274 39426 219800 40900 1000 2000 "clearline"] + Line[213511 46752 219348 46752 1000 2000 "clearline"] + Line[219348 46752 220100 46000 1000 2000 "clearline"] + Line[226400 46000 220100 46000 1000 2000 "clearline"] + Line[213511 48720 219072 48720 1000 2000 "clearline"] + Line[219072 48720 220152 49800 1000 2000 "clearline"] + Line[220126 49826 220152 49800 1000 2000 "clearline"] + Line[184968 93011 184968 89168 1000 2000 "clearline"] + Line[184968 89168 182500 86700 1000 2000 "clearline"] + Line[222774 64474 222800 64500 1000 2000 "clearline"] + Line[229401 59380 229401 53899 1000 2000 "clearline"] + Line[229401 53899 231000 52300 1000 2000 "clearline"] + Line[213511 50689 217189 50689 1000 2000 "clearline"] + Line[217189 50689 218900 52400 1000 2000 "clearline"] + Line[218900 52400 218900 60700 1000 2000 "clearline"] + Line[218900 60700 218800 60800 1000 2000 "clearline"] + Line[220100 49800 228200 49800 1000 2000 "clearline"] + Line[228200 49800 229200 48800 1000 2000 "clearline"] + Line[215600 103100 221700 109200 1000 2000 "clearline"] + Line[247100 51100 239400 43400 1000 2000 "clearline"] + Line[239400 31822 239400 43400 1000 2000 "clearline"] + Line[199600 60800 160900 60800 1000 2000 "clearline"] + Line[182500 107500 182500 119200 1000 2000 "clearline"] + Line[182500 119200 179500 122200 1000 2000 "clearline"] + Line[179500 122200 165300 122200 1000 2000 "clearline"] + Line[165300 122200 165200 122100 1000 2000 "clearline"] + Line[152489 74310 159390 74310 1000 2000 "clearline"] + Line[159390 74310 169200 64500 1000 2000 "clearline"] + Line[152489 52657 145457 52657 1000 2000 "clearline"] + Line[145457 52657 139600 46800 1000 2000 "clearline"] + Line[139600 46800 132200 46800 1000 2000 "clearline"] + Line[132200 46800 127400 51600 1000 2000 "clearline"] + Line[177600 64500 169200 64500 1000 2000 "clearline"] + Line[169200 64500 168700 65000 1000 2000 "clearline"] + Line[213511 66436 206664 66436 1000 2000 "clearline"] + Line[206664 66436 205400 67700 1000 2000 "clearline"] + Line[205400 67700 205400 73000 1000 2000 "clearline"] + Line[205400 73000 203800 74600 1000 2000 "clearline"] + Line[54200 75400 54200 75400 2500 2000 "clearline"] + Line[54200 75400 61800 83000 2500 2000 "clearline"] + Line[74200 75400 74200 75400 2500 2000 "clearline"] + Line[74200 75400 66700 82900 2500 2000 "clearline"] + Line[54300 49600 61700 42200 2500 2000 "clearline"] + Line[74300 49600 66800 42100 2500 2000 "clearline"] + Line[55674 41200 60313 41200 1000 2000 "clearline"] + Line[60313 41200 60361 41248 1000 2000 "clearline"] + Line[52526 41200 49574 41200 1000 2000 "clearline"] + Line[73900 33900 73900 37500 1000 2000 "clearline"] + Line[73900 40648 68639 40648 1000 2000 "clearline"] + Line[68639 40648 68038 41248 1000 2000 "clearline"] + Line[82950 61221 73721 61221 1000 2000 "clearline"] + Line[73721 61221 73700 61200 1000 2000 "clearline"] + Line[65052 61200 70252 61200 1000 2000 "clearline"] + Line[65026 67700 70252 67700 1000 2000 "clearline"] + Line[82950 66339 79061 66339 1000 2000 "clearline"] + Line[79061 66339 77700 67700 1000 2000 "clearline"] + Line[77700 67700 73400 67700 1000 2000 "clearline"] + Line[73700 92400 73700 86700 1000 2000 "clearline"] + Line[73700 83552 68341 83552 1000 2000 "clearline"] + Line[68341 83552 68047 83846 1000 2000 "clearline"] + Line[54600 92252 54600 86696 1000 2000 "clearline"] + Line[54600 86696 54648 86648 1000 2000 "clearline"] + Line[54648 83500 60024 83500 1000 2000 "clearline"] + Line[60024 83500 60370 83846 1000 2000 "clearline"] + Line[76774 93300 80000 93300 1000 2000 "clearline"] + Line[65479 29950 65489 23289 1000 2000 "clearline"] + Line[49000 37848 49000 40800 1000 2000 "clearline"] + Line[49000 40800 49400 41200 1000 2000 "clearline"] + Line[82950 63780 77320 63780 1500 1200 "clearline"] + Line[77320 63780 76900 64200 1500 1200 "clearline"] + Line[82950 58662 77362 58662 1500 1200 "clearline"] + Line[77362 58662 76900 58200 1500 1200 "clearline"] + Line[62920 29950 62920 25320 1500 1200 "clearline"] + Line[62920 25320 62400 24800 1500 1200 "clearline"] + Line[68038 29950 68038 25262 1500 1200 "clearline"] + Line[68038 25262 68500 24800 1500 1200 "clearline"] + Line[73900 23800 69500 23800 1000 2000 "clearline"] + Line[69500 23800 68750 24550 1000 2000 "clearline"] + Line[73900 30752 73900 30200 1000 2000 "clearline"] + Line[73900 30200 68500 24800 1000 2000 "clearline"] + Line[65488 95143 65488 100188 1500 1200 "clearline"] + Line[65488 100188 65500 100200 1500 1200 "clearline"] + Line[60370 95143 60370 97430 1500 1200 "clearline"] + Line[60370 97430 59800 98000 1500 1200 "clearline"] + Line[59800 98000 56600 98000 1500 1200 "clearline"] + Line[68047 95143 68047 97447 1000 2000 "clearline"] + Line[68047 97447 69000 98400 1000 2000 "clearline"] + Line[72148 100700 72148 98504 1000 2000 "clearline"] + Line[72148 98504 73652 97000 1000 2000 "clearline"] + Line[76800 97000 76800 93326 1000 2000 "clearline"] + Line[76800 93326 76774 93300 1000 2000 "clearline"] + Line[54600 95400 50748 95400 1000 2000 "clearline"] + Line[50748 95400 50700 95448 1000 2000 "clearline"] + Line[54600 95400 54600 96000 1000 2000 "clearline"] + Line[54600 96000 56600 98000 1000 2000 "clearline"] + Line[46800 92300 50700 92300 1000 2000 "clearline"] + Line[62929 95143 62929 98571 1000 2000 "clearline"] + Line[62929 98571 60700 100800 1000 2000 "clearline"] + Line[60700 100800 50500 100800 1000 2000 "clearline"] + Line[152489 86121 143021 86121 1000 2000 "clearline"] + Line[143021 86121 142900 86000 1000 2000 "clearline"] + Line[152489 80216 145984 80216 1000 2000 "clearline"] + Line[145984 80216 143000 83200 1000 2000 "clearline"] + Line[143000 83200 136300 83200 1000 2000 "clearline"] + Line[136300 83200 133400 86100 1000 2000 "clearline"] + Line[72148 100600 84500 100600 1000 2000 "clearline"] + Line[84500 100600 95800 89300 1000 2000 "clearline"] + Line[95800 89300 116700 89300 1000 2000 "clearline"] + Line[116700 89300 122400 95000 1000 2000 "clearline"] + Line[125900 89000 121200 86700 1000 2000 "clearline"] + Line[50700 92300 50700 87200 1000 2000 "clearline"] + Line[50700 87200 50800 87100 1000 2000 "clearline"] + Line[93900 87100 117100 87100 1000 2000 "clearline"] + Line[117100 87100 123300 93300 1000 2000 "clearline"] + Line[49000 30348 49000 34700 1000 2000 "clearline"] + Line[52526 26700 49500 26700 1000 2000 "clearline"] + Line[49500 26700 49000 27200 1000 2000 "clearline"] + Line[60361 29950 60361 27261 1000 2000 "clearline"] + Line[60361 27261 59800 26700 1000 2000 "clearline"] + Line[59800 26700 55674 26700 1000 2000 "clearline"] + Line[73900 37500 76600 37500 1000 2000 "clearline"] + Line[76600 37500 78600 39500 1000 2000 "clearline"] + Line[78600 39500 78600 41400 1000 2000 "clearline"] + Line[76574 23800 99200 46300 1000 2000 "clearline"] + Line[99200 46300 99200 54100 1000 2000 "clearline"] + Line[99200 54100 99800 54700 1000 2000 "clearline"] + Line[99750 54650 111400 54700 1000 2000 "clearline"] + Line[111400 54700 117300 60600 1000 2000 "clearline"] + Line[117300 60600 117300 63800 1000 2000 "clearline"] + Line[117300 63800 118000 64500 1000 2000 "clearline"] + Line[94100 37700 100100 44300 1000 2000 "clearline"] + Line[100100 44300 108500 44300 1000 2000 "clearline"] + Line[108500 44300 110700 46500 1000 2000 "clearline"] + Line[110700 46500 110700 50900 1000 2000 "clearline"] + Line[110700 50900 122400 62600 1000 2000 "clearline"] + Line[130520 41052 134804 41052 1000 2000 "clearline"] + Line[134804 41052 135652 41900 1000 2000 "clearline"] + Line[130520 39083 136817 39083 1000 2000 "clearline"] + Line[138800 41900 138800 37100 1000 2000 "clearline"] + Line[130520 35147 136847 35147 1000 2000 "clearline"] + Line[136847 35147 138800 37100 1000 2000 "clearline"] + Line[127400 53600 127400 51600 1000 2000 "clearline"] + Line[127400 51600 127450 51550 1000 2000 "clearline"] + Line[126484 43119 126484 44516 1000 2000 "clearline"] + Line[126484 44516 124500 46500 1000 2000 "clearline"] + Line[122548 43119 122548 44452 1000 2000 "clearline"] + Line[122548 44452 120600 46400 1000 2000 "clearline"] + Line[120600 46400 120600 50496 1000 2000 "clearline"] + Line[120600 50496 120704 50600 1000 2000 "clearline"] + Line[128453 43119 128453 47547 1000 2000 "clearline"] + Line[128453 47547 125400 50600 1000 2000 "clearline"] + Line[125400 50600 123852 50600 1000 2000 "clearline"] + Line[152489 46752 143848 46752 1000 2000 "clearline"] + Line[143848 46752 143800 46800 1000 2000 "clearline"] + Line[152489 74310 148884 74310 1000 2000 "clearline"] + Line[148884 74310 148074 73500 1000 2000 "clearline"] + Line[144926 73500 144926 72174 1000 2000 "clearline"] + Line[144926 72174 147700 69400 1000 2000 "clearline"] + Line[152489 76279 142979 76279 1000 2000 "clearline"] + Line[142979 76279 141900 75200 1000 2000 "clearline"] + Line[141900 75200 141900 69400 1000 2000 "clearline"] + Line[135926 42174 135926 44026 1000 2000 "clearline"] + Line[135926 44026 136600 44700 1000 2000 "clearline"] + Line[136600 44700 141300 44700 1000 2000 "clearline"] + Line[141300 44700 143800 42200 1000 2000 "clearline"] + Line[152489 78247 128653 78247 1000 2000 "clearline"] + Line[128653 78247 127200 79700 1000 2000 "clearline"] + Line[127200 79700 108700 79700 1000 2000 "clearline"] + Line[123852 50600 123852 53548 1000 2000 "clearline"] + Line[123852 53548 123500 53900 1000 2000 "clearline"] + Line[120481 39083 117417 39083 1000 2000 "clearline"] + Line[117417 39083 116400 40100 1000 2000 "clearline"] + Line[120481 35147 116947 35147 1000 2000 "clearline"] + Line[116947 35147 116400 34600 1000 2000 "clearline"] + Line[120481 37116 112884 37116 1000 2000 "clearline"] + Line[112884 37116 112400 37600 1000 2000 "clearline"] + Line[116400 34200 112448 34200 1000 2000 "clearline"] + Line[112448 34200 112400 34152 1000 2000 "clearline"] + Line[112400 29600 109800 32200 1000 2000 "clearline"] + Line[109800 32200 109800 39600 1000 2000 "clearline"] + Line[109800 39600 113100 42900 1000 2000 "clearline"] + Line[113100 42900 117500 42900 1000 2000 "clearline"] + Line[117500 42900 119200 41200 1000 2000 "clearline"] + Line[119200 41200 120333 41200 1000 2000 "clearline"] + Line[120333 41200 120481 41052 1000 2000 "clearline"] + Line[138948 32100 138948 36952 1000 2000 "clearline"] + Line[136817 39083 138948 36952 1000 2000 "clearline"] + Line[133000 32100 135800 32100 1000 2000 "clearline"] + Line[122548 33080 122548 30848 1000 2000 "clearline"] + Line[122548 30848 121400 29700 1000 2000 "clearline"] + Line[121400 29700 115474 29700 1000 2000 "clearline"] + Line[117200 24700 134852 24700 1000 2000 "clearline"] + Line[134852 24700 135752 23800 1000 2000 "clearline"] + Line[115300 26600 134652 26600 1000 2000 "clearline"] + Line[134652 26600 135752 27700 1000 2000 "clearline"] + Line[159700 24700 139800 24700 1000 2000 "clearline"] + Line[139800 24700 138900 23800 1000 2000 "clearline"] + Line[158700 26600 140000 26600 1000 2000 "clearline"] + Line[140000 26600 138900 27700 1000 2000 "clearline"] + Line[36400 28400 36500 28500 2500 2000 "clearline"] + Line[33800 26100 36400 28400 2500 2000 "clearline"] + Line[40400 32500 40400 36700 2500 2000 "clearline"] + Line[38874 23200 42100 23200 1000 2000 "clearline"] + Line[40400 23200 40400 32500 1000 2000 "clearline"] + Line[35526 23200 35526 27526 1000 2000 "clearline"] + Line[45248 23200 45248 27552 1000 2000 "clearline"] + Line[45248 27552 44300 28500 1000 2000 "clearline"] + Line[40400 32500 49000 32500 1000 2000 "clearline"] + Line[44200 75400 44200 78500 4000 2000 "clearline"] + Line[44200 78500 38400 84300 4000 2000 "clearline"] + Line[33574 77000 33574 77226 4000 2000 "clearline"] + Line[33574 77226 30000 83900 4000 2000 "clearline"] + Line[38400 101100 38400 96110 2500 2000 "clearline"] + Line[38400 96110 29510 96110 4000 2000 "clearline"] + Line[35552 19300 35552 23174 1000 2000 ""] + Line[35552 23174 35526 23200 1000 2000 ""] + Line[38700 19300 42100 19300 1000 2000 ""] + Line[38400 101100 38400 105326 1000 2000 ""] + Line[38400 108474 38400 111700 1000 2000 ""] + Line[38400 114848 38400 118000 1000 2000 ""] + Line[61904 61200 61904 67674 1000 2000 ""] + Line[61904 67674 61878 67700 1000 2000 ""] + Line[55000 104994 47206 104994 1000 2000 ""] + Line[47206 104994 42100 110100 1000 2000 ""] + Line[42100 110100 38400 110100 1000 2000 ""] + Line[63071 104994 65406 104994 1000 2000 ""] + Line[65406 104994 66100 104300 1000 2000 ""] + Line[66100 104300 66100 100800 1000 2000 ""] + Line[66100 100800 65500 100200 1000 2000 ""] + Line[46800 95448 46800 98600 1000 2000 "clearline"] + Line[50400 100800 49000 100800 1000 2000 "clearline"] + Line[49000 100800 46800 98600 1000 2000 "clearline"] + Line[55000 110900 53800 110900 1000 1200 "clearline"] + Line[53800 110900 51800 112900 1000 1200 "clearline"] + Line[55000 108931 51369 108931 1000 1200 "clearline"] + Line[51369 108931 49000 111300 1000 1200 "clearline"] + Line[49000 111300 49000 115500 1000 1200 "clearline"] + Line[55000 106963 50537 106963 1000 1200 "clearline"] + Line[50537 106963 45800 111700 1000 1200 "clearline"] + Line[45800 111700 45800 116900 1000 1200 "clearline"] + Line[45800 116900 47300 118400 1000 1200 "clearline"] + Line[69600 113700 69600 110100 1000 1200 "clearline"] + Line[69600 110100 68400 108900 1000 1200 "clearline"] + Line[68400 108900 63102 108900 1000 1200 "clearline"] + Line[63102 108900 63071 108931 1000 1200 "clearline"] + Line[63071 106963 69063 106963 1000 1200 "clearline"] + Line[69063 106963 71700 109600 1000 1200 "clearline"] + Line[71700 109600 71700 114400 1000 1200 "clearline"] + Line[71700 114400 65500 120600 1000 1200 "clearline"] + Line[65500 120600 45900 120600 1000 1200 "clearline"] + Line[45900 120600 42300 117000 1000 1200 "clearline"] + Line[42300 117000 42300 110000 1000 1200 "clearline"] + Line[42300 110000 42250 109950 1000 1200 "clearline"] + Line[69000 98400 69000 104200 1000 1200 "clearline"] + Line[63071 110900 65800 110900 1000 1200 "clearline"] + Line[65800 110900 66800 111900 1000 1200 "clearline"] + Line[53453 58465 53453 56547 1000 1200 "clearline"] + Line[53453 56547 53900 56100 1000 1200 "clearline"] + Line[53900 56100 70400 56100 1000 1200 "clearline"] + Line[70400 56100 73200 58900 1000 1200 "clearline"] + Line[73200 58900 73200 61000 1000 1200 "clearline"] + Line[73200 61000 73400 61200 1000 1200 "clearline"] + Line[51484 66535 51484 68784 1000 1200 "clearline"] + Line[51484 68784 53300 70600 1000 1200 "clearline"] + Line[53300 70600 72400 70600 1000 1200 "clearline"] + Line[72400 70600 73300 69700 1000 1200 "clearline"] + Line[73300 69700 73300 67800 1000 1200 "clearline"] + Line[73300 67800 73400 67700 1000 1200 "clearline"] + Line[53453 68153 54100 68800 1000 1200 "clearline"] + Line[54100 68800 55700 68800 1000 1200 "clearline"] + Line[55700 68800 56700 67800 1000 1200 "clearline"] + Line[47547 58465 47547 56547 1000 1200 "clearline"] + Line[47547 56547 47100 56100 1000 1200 "clearline"] + Line[47100 56100 45800 56100 1000 1200 "clearline"] + Line[45800 56100 45200 56700 1000 1200 "clearline"] + Line[45200 56700 45200 61200 1000 1200 "clearline"] + Line[45200 61200 43900 62500 1000 1200 "clearline"] + Line[49516 58465 49516 54716 1000 1200 "clearline"] + Line[49516 54716 48500 53700 1000 1200 "clearline"] + Line[51484 58465 51484 55916 1000 1200 "clearline"] + Line[51484 55916 53000 54400 1000 1200 "clearline"] + Line[53000 54400 58100 54400 1000 1200 "clearline"] + Line[58100 54400 59300 53200 1000 1200 "clearline"] + Line[47547 66535 47547 68553 1000 1200 "clearline"] + Line[47547 68553 46200 69900 1000 1200 "clearline"] + Line[49516 66535 49516 70816 1000 1200 "clearline"] + Line[49516 70816 49900 71200 1000 1200 "clearline"] + Line[47300 118400 56000 118400 1000 1200 "clearline"] + Line[56000 118400 59000 115400 1000 1200 "clearline"] + Line[59000 115400 67900 115400 1000 1200 "clearline"] + Line[67900 115400 69600 113700 1000 1200 "clearline"] + Line[35000 110100 38400 110100 1000 1200 "clearline"] + Line[56065 11753 53647 11753 1000 1200 "clearline"] + Line[53647 11753 52500 12900 1000 1200 "clearline"] + Line[64135 5847 66653 5847 1000 1200 "clearline"] + Line[66653 5847 67800 4700 1000 1200 "clearline"] + Line[56065 9784 51416 9784 1000 1200 "clearline"] + Line[51416 9784 50000 11200 1000 1200 "clearline"] + Line[50000 11200 50000 14500 1000 1200 "clearline"] + Line[50000 14500 51200 15700 1000 1200 "clearline"] + Line[51200 15700 64400 15700 1000 1200 "clearline"] + Line[64400 15700 67000 13100 1000 1200 "clearline"] + Line[67000 13100 67000 12200 1000 1200 "clearline"] + Line[67000 12200 66500 11700 1000 1200 "clearline"] + Line[66500 11700 64189 11700 1000 1200 "clearline"] + Line[64189 11700 64135 11753 1000 1200 "clearline"] + Line[64135 9784 67284 9784 1000 1200 "clearline"] + Line[67284 9784 68600 11100 1000 1200 "clearline"] + Line[47900 14800 47900 10700 1000 1200 "clearline"] + Line[47900 10700 50800 7800 1000 1200 "clearline"] + Line[50800 7800 56048 7800 1000 1200 "clearline"] + Line[56048 7800 56065 7816 1000 1200 "clearline"] + Line[42100 19300 42100 14300 1000 1200 "clearline"] + Line[42100 14300 43500 12900 1000 1200 "clearline"] + Line[43500 12900 47900 12900 1000 1200 "clearline"] + Line[70226 20000 68779 20000 1000 1200 "clearline"] + Line[68779 20000 65479 23300 1000 1200 "clearline"] + Line[64135 7816 68016 7816 1000 1200 "clearline"] + Line[68016 7816 70400 10200 1000 1200 "clearline"] + Line[70400 10200 70400 19826 1000 1200 "clearline"] + Line[70400 19826 70226 20000 1000 1200 "clearline"] + Line[45248 19300 45248 15848 1000 1200 "clearline"] + Line[45248 15848 45200 15800 1000 1200 "clearline"] + Line[56065 5847 53547 5847 1000 1200 "clearline"] + Line[53547 5847 52500 4800 1000 1200 "clearline"] + Line[55674 26700 55674 23126 1000 1200 "clearline"] + Line[55674 23126 55800 23000 1000 1200 "clearline"] + Line[49100 27100 49100 23100 1000 1200 "clearline"] + Line[49100 23100 49000 23000 1000 1200 "clearline"] + Line[52600 41200 52600 44100 1000 1200 "clearline"] + Line[52600 44100 52500 44200 1000 1200 "clearline"] + Line[73374 20000 74800 20000 1000 1200 "clearline"] + Line[74800 20000 76600 21800 1000 1200 "clearline"] + Line[76600 21800 76600 23774 1000 1200 "clearline"] + Line[76600 23774 76574 23800 1000 1200 "clearline"] + Line[68600 11100 68600 15600 1000 1200 "clearline"] + Line[59250 53250 59450 53250 1000 1200 "clearline"] + Line[59450 53250 60600 54400 1000 1200 "clearline"] + Line[60600 54400 76800 54400 1000 1200 "clearline"] + Line[76800 54400 79300 51900 1000 1200 "clearline"] + Line[79300 51900 79300 46500 1000 1200 "clearline"] + Line[79300 46500 81500 44300 1000 1200 "clearline"] + Line[81500 44300 81500 33400 1000 1200 "clearline"] + Line[81500 33400 75200 27100 1000 1200 "clearline"] + Line[47900 14800 52000 18900 1000 1200 "clearline"] + Line[52000 18900 65300 18900 1000 1200 "clearline"] + Line[68600 15600 65300 18900 1000 1200 "clearline"] + Line[45200 8400 45100 8400 1000 1200 "clearline"] + Line[36500 36700 36500 40800 2500 2000 "clearline"] + Line[36500 40800 37700 42000 2500 2000 "clearline"] + Line[44300 36700 44300 40800 2500 2000 "clearline"] + Line[44300 40800 43100 42000 2500 2000 "clearline"] + Line[43100 42000 37700 42000 2500 2000 "clearline"] + Line[44300 49600 41400 49600 1000 1200 "clearline"] + Line[41400 49600 32400 40600 1000 1200 "clearline"] + Line[32400 40600 32400 29800 1000 1200 "clearline"] + Line[32400 29800 30400 27800 1000 1200 "clearline"] + Line[30400 27800 30400 19700 1000 1200 "clearline"] + Line[30400 19700 34100 16000 1000 1200 "clearline"] + Line[34150 15950 37650 15950 1000 1200 "clearline"] + Line[37650 15950 45200 8400 1000 1200 "clearline"] + Line[53453 66535 53453 68153 1000 1200 "clearline"] + Line[16600 33400 20300 33400 2500 2000 "clearline"] + Line[18100 45552 18100 39400 1000 1600 "clearline"] + Line[18100 39400 16500 37800 1000 1600 "clearline"] + Line[16500 37800 16500 33400 1000 1600 "clearline"] + Line[191700 100548 192648 100548 1000 1600 "clearline"] + Line[192648 100548 193200 101100 1000 1600 "clearline"] + Line[193200 101100 198100 101100 1000 1600 "clearline"] + Line[198100 101100 198800 100400 1000 1600 "clearline"] + Line[16000 73000 16000 71074 2500 2000 "clearline"] + Line[16000 71074 11300 66374 2500 2000 "clearline"] + Line[213511 84153 218400 84200 1000 2000 "clearline"] + Line[8708 93100 7000 93100 1000 1600 "clearline"] + Line[7000 93100 5900 92000 1000 1600 "clearline"] + Line[5900 92000 5900 91200 1000 1600 "clearline"] + Line[5900 91200 5100 90400 1000 1600 "clearline"] + Line[5100 90400 3646 90400 1000 1600 "clearline"] + Line[3646 90400 3000 89754 1000 1600 "clearline"] + Line[3000 93100 3000 94700 1000 1600 "clearline"] + Line[3000 94700 4300 96000 1000 1600 "clearline"] + Line[4300 96000 16674 96000 1000 1600 "clearline"] + Line[16674 96000 19600 93074 1000 1600 "clearline"] + Line[19600 89926 19600 86700 1000 1600 "clearline"] + Line[199500 77700 206300 84500 1000 2000 "clearline"] + Line[240230 80339 242239 80339 1000 2000 "clearline"] + Line[242239 80339 244700 82800 1000 2000 "clearline"] + Line[240230 85260 242240 85260 1000 2000 "clearline"] + Line[242240 85260 244700 82800 1000 2000 "clearline"] + Line[240230 90181 242781 90181 1000 2000 "clearline"] + Line[242781 90181 244700 92100 1000 2000 "clearline"] + Line[244700 89274 244700 92100 1000 2000 "clearline"] + Line[244700 92100 245474 92100 1000 2000 "clearline"] + Line[231570 75418 240230 75418 1000 2000 "clearline"] + Line[244700 78800 244700 86126 1000 2000 "clearline"] + Line[244800 82800 244750 82850 1000 2000 "clearline"] + Line[244700 71152 244700 75652 1000 2000 "clearline"] + Line[237100 69900 240300 69900 1000 2000 "clearline"] + Line[244700 71152 243400 69852 1000 2000 "clearline"] + Line[243700 69648 243448 69900 1000 2000 "clearline"] + Line[231530 85300 231570 85260 1000 1600 "clearline"] + Line[231552 75400 231570 75418 1000 1600 "clearline"] + Line[243200 69652 243448 69900 1000 1600 "clearline"] +) +Layer(2 "GND plane") +( + Line[97100 60000 100500 56600 1000 2000 "clearline"] + Line[100500 56600 125000 56600 1000 2000 "clearline"] + Line[125000 56600 132500 64100 1000 2000 "clearline"] + Line[132500 64100 159000 64100 1000 2000 "clearline"] + Line[159000 64100 159100 64200 1000 2000 "clearline"] + Line[174750 79950 117000 80000 1000 2000 "clearline"] + Line[117300 80000 106300 69000 1000 2000 "clearline"] + Line[106300 69000 106300 65200 1000 2000 "clearline"] + Line[106300 65200 106100 65000 1000 2000 "clearline"] + Line[106100 60000 106200 60000 1000 2000 "clearline"] + Line[129000 63400 131700 66100 1000 2000 "clearline"] + Line[131700 66100 156400 66100 1000 2000 "clearline"] + Line[156400 66100 156400 66200 1000 2000 "clearline"] + Line[156400 66200 159600 69400 1000 2000 "clearline"] + Line[159600 69400 186400 69400 1000 2000 "clearline"] + Line[186400 69400 201500 83800 1000 2000 "clearline"] + Line[49300 82100 95800 82100 1000 2000 "clearline"] + Line[95800 82100 99300 85600 1000 2000 "clearline"] + Line[161900 83900 192500 83900 1000 2000 "clearline"] + Line[177100 77600 174750 79950 1000 2000 "clearline"] + Line[118400 75600 118500 75600 1000 2000 "clearline"] + Line[118500 75600 120800 77900 1000 2000 "clearline"] + Line[120800 77900 172400 77900 1000 2000 "clearline"] + Line[172400 77900 175700 74600 1000 2000 "clearline"] + Line[175700 74600 180100 74600 1000 2000 "clearline"] + Line[156700 89000 161900 83900 1000 2000 "clearline"] + Line[24300 54600 24300 44700 2500 2000 ""] + Line[19100 49600 28800 49600 2500 2000 ""] + Line[7400 58500 15200 58500 2500 2000 ""] + Line[11300 55300 11300 61400 2500 2000 ""] + Line[106100 60000 107400 58700 1000 2000 "clearline"] + Line[107400 58700 118400 58700 1000 2000 "clearline"] + Line[118400 58700 123200 63500 1000 2000 "clearline"] + Line[123200 63500 129100 63500 1000 2000 "clearline"] + Line[156653 89050 156852 88852 1000 2000 "clearline"] + Line[142000 54000 186600 54000 1000 2000 "clearline"] + Line[186600 54000 191800 48800 1000 2000 "clearline"] + Line[115400 85600 115500 85600 1000 2000 "clearline"] + Line[115500 85600 119800 89900 1000 2000 "clearline"] + Line[119800 89900 155803 89900 1000 2000 "clearline"] + Line[155803 89900 156852 88852 1000 2000 "clearline"] + Line[67652 61200 95900 61200 1000 2000 "clearline"] + Line[95900 61200 98150 58950 1000 2000 "clearline"] + Line[99250 85550 115450 85550 1000 2000 "clearline"] + Line[115450 85550 116250 86350 1000 2000 "clearline"] + Line[163100 40300 152200 51200 1000 2000 "clearline"] + Line[152200 51200 136999 51200 1000 2000 "clearline"] + Line[136999 51200 135500 52699 1000 2000 "clearline"] + Line[39300 41900 39300 100200 1500 1200 "clearline"] + Line[39300 100200 38400 101100 1500 1200 "clearline"] + Line[44200 75400 47300 75400 4000 2000 ""] + Line[44100 78100 44100 73700 4000 2000 ""] + Line[44100 73700 42700 72300 4000 2000 ""] + Line[50800 87100 52000 85900 1000 1200 "clearline"] + Line[52000 85900 79000 85900 1000 1200 "clearline"] + Line[79000 85900 80200 87100 1000 1200 "clearline"] + Line[80200 87100 93900 87100 1000 1200 "clearline"] + Line[59200 82100 59200 70100 1000 1200 "clearline"] + Line[59200 70100 59600 69700 1000 1200 "clearline"] + Line[59600 69700 59600 66400 1000 1200 "clearline"] + Line[59600 66400 57500 64300 1000 1200 "clearline"] + Line[57500 64300 57500 60200 1000 1200 "clearline"] + Line[74900 27400 74900 24300 1000 1200 "clearline"] + Line[74900 24300 67400 16800 1000 1200 "clearline"] + Line[48500 53700 48500 52100 1000 1200 "clearline"] + Line[48500 52100 49200 51400 1000 1200 "clearline"] + Line[49200 51400 49200 29100 1000 1200 "clearline"] + Line[49200 29100 52500 25800 1000 1200 "clearline"] + Line[52500 25800 52500 21000 1000 1200 "clearline"] + Line[52500 21000 57800 15700 1000 1200 "clearline"] + Line[57800 15700 60100 15700 1000 1200 "clearline"] + Line[45200 8400 86200 8400 1000 1200 "clearline"] + Line[86200 8400 88100 10300 1000 1200 "clearline"] + Line[219100 102200 219100 92800 1000 1600 "clearline"] + Line[219100 92800 214800 88500 1000 1600 "clearline"] + Line[214800 88500 214800 57600 1000 1600 "clearline"] + Line[214800 57600 226400 46000 1000 1600 "clearline"] + Polygon("clearpoly,lock") + ( + [1000 1000] [88000 1000] [88000 3600] [140000 3600] [140000 1000] + [324000 1000] [324000 124000] [1000 124000] + ) +) +Layer(3 "power plane") +( + Line[11300 66374 11274 66374 1000 2000 "clearline"] + Line[152500 7500 149700 10300 1000 2000 "clearline"] + Line[149700 10300 88300 10300 1000 2000 "clearline"] + Line[181700 64500 151400 34900 1000 2000 "clearline"] + Line[166000 96000 181200 80800 1000 2000 "clearline"] + Line[132500 58800 144600 58800 1000 2000 "clearline"] + Line[144600 58800 155400 69700 1000 2000 "clearline"] + Line[155301 69600 191400 69500 1000 2000 "clearline"] + Line[181150 80850 205350 80850 1000 2000 "clearline"] + Line[205350 80850 208300 78200 1000 2000 "clearline"] + Line[174100 37700 174100 28400 1000 2000 "clearline"] + Line[174100 28400 180400 22100 1000 2000 "clearline"] + Line[180400 22100 204100 22100 1000 2000 "clearline"] + Line[204100 22100 213500 12700 1000 2000 "clearline"] + Line[213500 12700 216300 12700 1000 2000 "clearline"] + Line[216300 12700 221500 7500 1000 2000 "clearline"] + Line[170200 37700 170200 37900 1000 2000 "clearline"] + Line[177400 38900 177400 28400 1000 2000 "clearline"] + Line[177400 28400 181600 24200 1000 2000 "clearline"] + Line[181600 24200 209800 24200 1000 2000 "clearline"] + Line[209800 24200 216500 17500 1000 2000 "clearline"] + Line[124600 109500 152600 109500 1000 2000 "clearline"] + Line[152600 109500 155600 106500 1000 2000 "clearline"] + Line[124600 105500 124800 105500 1000 2000 "clearline"] + Line[124800 105500 127000 107700 1000 2000 "clearline"] + Line[127000 107700 150500 107700 1000 2000 "clearline"] + Line[150500 107700 155600 102600 1000 2000 "clearline"] + Line[196800 55300 225500 55300 1000 2000 "clearline"] + Line[225200 55300 228000 55300 1000 2000 "clearline"] + Line[228000 55300 231000 52300 1000 2000 "clearline"] + Line[199600 60800 218800 60800 1000 2000 "clearline"] + Line[191800 48800 229200 48800 1000 2000 "clearline"] + Line[216900 32000 233800 32000 1000 2000 "clearline"] + Line[233800 32000 239400 37600 1000 2000 "clearline"] + Line[11300 66374 11274 66374 1000 2000 "clearline"] + Line[203300 63600 203300 64000 1000 2000 "clearline"] + Line[170200 37700 170200 38400 1000 2000 "clearline"] + Line[170200 38400 172300 40500 1000 2000 "clearline"] + Line[172300 40500 175800 40500 1000 2000 "clearline"] + Line[175800 40500 177400 38900 1000 2000 "clearline"] + Line[154300 71500 143600 60800 1000 2000 "clearline"] + Line[143600 60800 128700 60800 1000 2000 "clearline"] + Line[128700 60800 111600 77900 1000 2000 "clearline"] + Line[203300 64000 195100 72200 1000 2000 "clearline"] + Line[195100 72200 185300 72200 1000 2000 "clearline"] + Line[185300 72200 184600 71500 1000 2000 "clearline"] + Line[184600 71500 154300 71500 1000 2000 "clearline"] + Line[203100 71400 202700 71800 1000 2000 "clearline"] + Line[111600 77900 111600 81400 1000 2000 "clearline"] + Line[111600 81400 110400 82600 1000 2000 "clearline"] + Line[110400 82600 61600 82600 1000 2000 "clearline"] + Line[61600 82600 54600 89600 1000 2000 "clearline"] + Line[73600 89600 78900 84300 1000 2000 "clearline"] + Line[78900 84300 113300 84300 1000 2000 "clearline"] + Line[113300 84300 125000 96000 1000 2000 "clearline"] + Line[124950 95950 166000 96000 1000 2000 "clearline"] + Line[133100 58800 131800 58800 1000 2000 "clearline"] + Line[131800 58800 130400 57400 1000 2000 "clearline"] + Line[46200 69900 42600 69900 1000 1200 "clearline"] + Line[42600 69900 39200 73300 1000 1200 "clearline"] + Line[39200 73300 39200 95100 1000 1200 "clearline"] + Line[39200 95100 35000 99300 1000 1200 "clearline"] + Line[35000 99300 35000 110100 1000 1200 "clearline"] + Line[55800 23000 55800 8100 1000 1200 "clearline"] + Line[55800 8100 52500 4800 1000 1200 "clearline"] + Line[202750 71750 214950 71750 1000 1600 "clearline"] + Line[189150 103100 188600 102550 1000 2000 "clearline"] + Line[155650 102550 188650 102550 1000 2000 "clearline"] + Line[200200 103100 189150 103100 1000 2000 "clearline"] + Line[200700 102600 200200 103100 1000 2000 "clearline"] + Line[219000 102600 200700 102600 1000 2000 "clearline"] + Line[233800 73200 237100 69900 1000 1600 "clearline"] + Polygon("clearpoly,lock") + ( + [29000 44000] [110000 44000] [110000 81000] [29000 81000] + ) + Polygon("clearpoly,lock") + ( + [1000 1000] [28000 1000] [28000 124000] [1000 124000] + ) + Polygon("clearpoly,lock") + ( + [1000 1000] [88000 1000] [88000 3600] [140000 3600] [140000 1000] + [324000 1000] [324000 43000] [1000 43000] + ) + Polygon("clearpoly,lock") + ( + [1000 82000] [324000 82000] [324000 124000] [1000 124000] + ) + Polygon("clearpoly,lock") + ( + [111000 3600] [140000 3600] [140000 1000] [324000 1000] [324000 124000] + [111000 124000] + ) +) +Layer(4 "bottom") +( + Line[151300 34900 151300 8700 1000 2000 "clearline"] + Line[151300 8700 152500 7500 1000 2000 "clearline"] + Line[167500 17500 177800 27800 1000 2000 "clearline"] + Line[177800 27800 177800 50700 1000 2000 "clearline"] + Line[162500 7500 164900 7500 1000 2000 "clearline"] + Line[164900 7500 172600 15200 1000 2000 "clearline"] + Line[172600 15200 172600 20000 1000 2000 "clearline"] + Line[172600 20000 180900 28300 1000 2000 "clearline"] + Line[180900 28300 180900 47700 1000 2000 "clearline"] + Line[197900 82400 197900 76100 1000 2000 "clearline"] + Line[197900 76100 191300 69500 1000 2000 "clearline"] + Line[196700 83500 197900 82400 1000 2000 "clearline"] + Line[124400 60000 124400 101600 1000 2000 "clearline"] + Line[124600 105500 125000 105500 1000 2000 "clearline"] + Line[164000 123400 116700 123500 1000 2000 "clearline"] + Line[116700 123500 111800 118600 1000 2000 "clearline"] + Line[111800 118600 44800 118450 1000 2000 "clearline"] + Line[121600 120900 121600 117700 1000 2000 "clearline"] + Line[121600 117700 128400 110900 1000 2000 "clearline"] + Line[128400 110900 128400 105100 1000 2000 "clearline"] + Line[128400 105100 128300 105000 1000 2000 "clearline"] + Line[127400 53600 127400 98900 1000 2000 "clearline"] + Line[133400 112400 133400 86100 1000 2000 "clearline"] + Line[133400 112300 134900 113800 1000 2000 "clearline"] + Line[134900 113800 134900 118600 1000 2000 "clearline"] + Line[134900 118600 133300 120200 1000 2000 "clearline"] + Line[172400 107400 172500 107500 1000 2000 "clearline"] + Line[165300 37000 165300 38500 1000 2000 "clearline"] + Line[165300 38500 166000 39200 1000 2000 "clearline"] + Line[166000 39200 166000 93800 1000 2000 "clearline"] + Line[166000 93800 170000 97800 1000 2000 "clearline"] + Line[170000 97800 171800 97800 1000 2000 "clearline"] + Line[184500 50100 184500 30400 1000 2000 "clearline"] + Line[184500 30400 191000 23900 1000 2000 "clearline"] + Line[182500 107500 182500 77100 1000 2000 "clearline"] + Line[182500 77100 185200 74400 1000 2000 "clearline"] + Line[185200 74400 185200 52200 1000 2000 "clearline"] + Line[185200 52200 186700 50700 1000 2000 "clearline"] + Line[186700 50700 186700 31100 1000 2000 "clearline"] + Line[231500 19200 231500 7500 1000 2000 "clearline"] + Line[203800 18000 203800 14100 1000 2000 "clearline"] + Line[203800 14100 192600 2900 1000 2000 "clearline"] + Line[192600 2900 177100 2900 1000 2000 "clearline"] + Line[177100 2900 172500 7500 1000 2000 "clearline"] + Line[147600 38000 155900 38000 1000 2000 "clearline"] + Line[155900 38000 163600 45700 1000 2000 "clearline"] + Line[163600 45700 163600 98600 1000 2000 "clearline"] + Line[163600 98600 172500 107500 1000 2000 "clearline"] + Line[160900 60800 160900 61400 1000 2000 "clearline"] + Line[160900 61400 161700 62200 1000 2000 "clearline"] + Line[161700 62200 161700 100400 1000 2000 "clearline"] + Line[161700 100400 155600 106500 1000 2000 "clearline"] + Line[128300 105000 130700 102600 1000 2000 "clearline"] + Line[130700 102600 130700 78400 1000 2000 "clearline"] + Line[130700 78400 129600 77300 1000 2000 "clearline"] + Line[129600 77300 129600 62500 1000 2000 "clearline"] + Line[129600 62500 132900 59200 1000 2000 "clearline"] + Line[132850 59250 136750 59250 1000 2000 "clearline"] + Line[136750 59250 142000 54000 1000 2000 "clearline"] + Line[165200 122100 165200 122200 1000 2000 "clearline"] + Line[165200 122200 164000 123400 1000 2000 "clearline"] + Line[211400 55200 211400 52500 1000 2000 "clearline"] + Line[211400 52500 202300 43400 1000 2000 "clearline"] + Line[184500 50100 182500 52100 1000 2000 "clearline"] + Line[182500 52100 182500 59600 1000 2000 "clearline"] + Line[182500 59600 177500 64600 1000 2000 "clearline"] + Line[119700 21900 119700 21800 1000 2000 "clearline"] + Line[119700 21800 117800 19900 1000 2000 "clearline"] + Line[117800 19900 32900 19900 1000 2000 "clearline"] + Line[6100 44300 5900 44500 1000 2000 "clearline"] + Line[29200 54500 29200 54600 1000 2000 "clearline"] + Line[29200 54600 39200 64600 1000 2000 "clearline"] + Line[112800 48500 105700 41400 1000 2000 "clearline"] + Line[78600 41400 105700 41400 1000 2000 "clearline"] + Line[130400 57400 130400 52600 1000 2000 "clearline"] + Line[130400 52600 128700 50900 1000 2000 "clearline"] + Line[128700 50900 115200 50900 1000 2000 "clearline"] + Line[115200 50900 112650 48350 1000 2000 "clearline"] + Line[143800 46800 124800 46800 1000 2000 "clearline"] + Line[124800 46800 124500 46500 1000 2000 "clearline"] + Line[141900 69400 147100 64200 1000 2000 "clearline"] + Line[147100 64200 147100 45500 1000 2000 "clearline"] + Line[147100 45500 143800 42200 1000 2000 "clearline"] + Line[67626 67700 74000 67700 1000 2000 "clearline"] + Line[74000 67700 79200 72900 1000 2000 "clearline"] + Line[79200 72900 79200 80400 1000 2000 "clearline"] + Line[79200 80400 82300 83500 1000 2000 "clearline"] + Line[82300 83500 117900 83500 1000 2000 "clearline"] + Line[117900 83500 121200 86800 1000 2000 "clearline"] + Line[123500 53900 118900 58500 1000 2000 "clearline"] + Line[118900 58500 118900 64400 1000 2000 "clearline"] + Line[118900 64400 109500 73800 1000 2000 "clearline"] + Line[109500 73800 109500 78900 1000 2000 "clearline"] + Line[109500 78900 108700 79700 1000 2000 "clearline"] + Line[39200 64600 39200 97100 1000 2000 "clearline"] + Line[39200 97100 41400 99300 1000 1200 "clearline"] + Line[41400 99300 41400 115050 1000 1200 "clearline"] + Line[41400 115050 44800 118450 1000 1200 "clearline"] + Line[46900 98600 46900 113400 1000 1200 "clearline"] + Line[46900 113400 49000 115500 1000 1200 "clearline"] + Line[69000 104200 69000 109700 1000 1200 "clearline"] + Line[69000 109700 66800 111900 1000 1200 "clearline"] + Line[48500 53700 48500 67600 1000 1200 "clearline"] + Line[48500 67600 46200 69900 1000 1200 "clearline"] + Line[49900 71200 51500 69600 1000 1200 "clearline"] + Line[51500 69600 51500 61000 1000 1200 "clearline"] + Line[51500 61000 59300 53200 1000 1200 "clearline"] + Line[50400 70700 50050 71050 1000 1200 "clearline"] + Line[94100 37700 63700 37700 1000 1200 "clearline"] + Line[63700 37700 49000 23000 1000 1200 "clearline"] + Line[52500 44200 66100 44200 1000 1200 "clearline"] + Line[66100 44200 69300 47400 1000 1200 "clearline"] + Line[69300 47400 69300 52400 1000 1200 "clearline"] + Line[69300 52400 61400 60300 1000 1200 "clearline"] + Line[61400 60300 57500 60300 1000 1200 "clearline"] + Line[5900 44500 12400 44500 1000 1200 "clearline"] + Line[12400 44500 28400 28500 1000 1200 "clearline"] + Line[28400 28500 28400 24400 1000 1200 "clearline"] + Line[28400 24400 32900 19900 1000 1200 "clearline"] + Line[56700 67800 57400 67800 1000 1600 "clearline"] + Line[78200 89500 78200 85900 1000 1600 "clearline"] + Line[78200 85900 75600 83300 1000 1600 "clearline"] + Line[75600 83300 73700 83300 1000 1600 "clearline"] + Line[73700 83300 69200 78800 1000 1600 "clearline"] + Line[69200 78800 69200 73000 1000 1600 "clearline"] + Line[69200 73000 66800 70600 1000 1600 "clearline"] + Line[66800 70600 59500 70600 1000 1600 "clearline"] + Line[59500 70600 56700 67800 1000 1600 "clearline"] + Line[59000 115400 59000 102500 1000 1600 "clearline"] + Line[59000 102500 61400 100100 1000 1600 "clearline"] + Line[61400 100100 61400 89800 1000 1600 "clearline"] + Line[61400 89800 49700 78100 1000 1600 "clearline"] + Line[49700 71400 49850 71250 1000 1600 "clearline"] + Line[42300 70400 42300 80500 2500 2000 ""] + Line[49900 71200 49900 71900 1000 1600 "clearline"] + Line[49900 71900 49200 72600 1000 1600 "clearline"] + Line[49200 72600 49200 77600 1000 1600 "clearline"] + Line[49200 77600 50050 78450 1000 1600 "clearline"] + Line[226500 17500 222200 21800 1000 1600 "clearline"] + Line[222200 21800 193100 21800 1000 1600 "clearline"] + Line[193100 21800 190600 24300 1000 1600 "clearline"] + Line[194200 23600 227100 23600 1000 1600 "clearline"] + Line[227100 23600 231450 19250 1000 1600 "clearline"] + Line[186700 31100 194200 23600 1000 1600 "clearline"] + Polygon("clearpoly,lock") + ( + [1000 1000] [88000 1000] [88000 3600] [140000 3600] [140000 1000] + [324000 1000] [324000 124000] [1000 124000] + ) +) +Layer(5 "outline") +( + Attribute("PCB::skip-drc" "1") + Line[0 0 89000 0 1000 2000 "lock"] + Line[89000 0 89000 2600 1000 2000 "lock"] + Line[89000 2600 139000 2600 1000 2000 "lock"] + Line[139000 2600 139000 0 1000 2000 "lock"] + Line[139000 0 325000 0 1000 2000 "lock"] + Line[325000 0 325000 125000 1000 2000 "lock"] + Line[325000 125000 0 125000 1000 2000 "lock"] + Line[0 125000 0 0 1000 2000 "lock"] +) +Layer(6 "silk") +( + Line[24400 90000 30700 96700 1000 2000 "clearline"] + Line[35200 89800 35200 96600 1000 2000 "clearline"] + Line[44400 13700 44400 16000 1000 2000 "clearline"] + Line[34400 13700 44400 13700 1000 2000 "clearline"] + Line[34400 16000 34400 13700 1000 2000 "clearline"] + Text[221200 117800 0 200 "TeleMega v1.0" "clearline,onsolder"] + Text[303248 100520 3 100 "` 2013 Bdale Garbee KB0G" "onsolder"] + Text[141500 29700 0 100 "companion" "clearline,onsolder"] + Text[39600 123800 3 150 "switch" "clearline,onsolder"] + Text[49600 112100 3 150 "gnd" "clearline,onsolder"] + Text[66000 115600 3 175 "main" "clearline,onsolder"] + Text[86200 122800 3 175 "apogee" "clearline,onsolder"] + Text[105000 98600 3 200 "D" "clearline,onsolder"] + Text[65300 34400 3 200 "A" "clearline,onsolder"] + Text[86900 34400 3 200 "B" "clearline,onsolder"] + Text[106300 34000 3 200 "C" "clearline,onsolder"] + Text[29200 34600 3 150 "gnd" "clearline,onsolder"] + Text[50300 29600 3 150 "lipo" "clearline,onsolder"] + Text[40300 35400 3 150 "pyro" "clearline,onsolder"] + Text[4200 46200 1 150 "-" "clearline,onsolder"] + Text[7200 81600 0 150 "+" "clearline,onsolder"] + Text[163800 102200 0 122 "debug" "clearline,onsolder"] + Text[202200 30200 0 122 "serial" "clearline,onsolder"] + Polygon("auto") + ( + [189574 95767] [183351 75758] [185109 73647] [189574 83028] [194039 73647] + [195797 75758] + ) + Polygon("auto") + ( + [189574 64191] [182662 73403] [171100 36229] [163136 28812] [177595 28812] + [185103 36093] [185103 64788] [189574 61825] [194044 64788] [194044 36093] + [201553 28812] [216006 28812] [208047 36229] [196486 73403] + ) + Polygon("clearpoly") + ( + [54500 22800] [136500 22800] [136500 3900] [54500 3900] + ) +) +Layer(7 "silk") +( +) +NetList() +( + Net("+3.3V" "(unknown)") + ( + Connect("C10-2") + Connect("C22-2") + Connect("C36-2") + Connect("C37-2") + Connect("C101-2") + Connect("C301-2") + Connect("C600-2") + Connect("J9-7") + Connect("J21-6") + Connect("L600-1") + Connect("R38-2") + Connect("R900-2") + Connect("R901-2") + Connect("U1-5") + Connect("U3-9") + Connect("U4-1") + Connect("U5-3") + Connect("U5-7") + Connect("U5-8") + Connect("U7-6") + Connect("U7-11") + Connect("U7-21") + Connect("U7-28") + Connect("U7-50") + Connect("U7-75") + Connect("U7-100") + Connect("U9-2") + Connect("U9-4") + Connect("U9-13") + Connect("U11-2") + Connect("U12-13") + Connect("U13-8") + Connect("U14-8") + Connect("U15-8") + ) + Net("ba_miso1" "(unknown)") + ( + Connect("U4-6") + Connect("U7-31") + ) + Net("ba_mosi1" "(unknown)") + ( + Connect("U4-7") + Connect("U7-32") + ) + Net("ba_sck1" "(unknown)") + ( + Connect("U4-8") + Connect("U7-30") + ) + Net("beeper" "(unknown)") + ( + Connect("U7-63") + Connect("U8-2") + ) + Net("boot0" "(unknown)") + ( + Connect("J21-3") + Connect("R402-1") + Connect("U7-94") + ) + Net("cmp_ldo_in" "(unknown)") + ( + Connect("R36-1") + Connect("R37-2") + Connect("U13-3") + Connect("U13-5") + Connect("U14-3") + Connect("U14-5") + Connect("U15-3") + Connect("U15-5") + ) + Net("cmp_rail" "(unknown)") + ( + Connect("R38-1") + Connect("R39-2") + Connect("U13-2") + Connect("U13-6") + Connect("U14-2") + Connect("U14-6") + Connect("U15-2") + Connect("U15-6") + ) + Net("cs_accel" "(unknown)") + ( + Connect("U3-12") + Connect("U7-85") + ) + Net("cs_companion0" "(unknown)") + ( + Connect("J9-6") + Connect("U7-81") + ) + Net("cs_companion1" "(unknown)") + ( + Connect("J9-5") + Connect("U7-82") + ) + Net("cs_flash" "(unknown)") + ( + Connect("U5-1") + Connect("U7-84") + ) + Net("cs_gyro" "(unknown)") + ( + Connect("U7-83") + Connect("U12-8") + ) + Net("cs_pres" "(unknown)") + ( + Connect("U4-4") + Connect("U4-5") + Connect("U7-33") + ) + Net("fet_a" "(unknown)") + ( + Connect("J1-6") + Connect("Q1-5") + Connect("Q1-6") + Connect("R14-1") + ) + Net("fet_b" "(unknown)") + ( + Connect("J1-4") + Connect("Q1-7") + Connect("Q1-8") + Connect("R13-1") + ) + Net("fet_c" "(unknown)") + ( + Connect("J1-2") + Connect("Q2-7") + Connect("Q2-8") + Connect("R16-1") + ) + Net("fet_d" "(unknown)") + ( + Connect("J2-8") + Connect("Q2-5") + Connect("Q2-6") + Connect("R15-1") + ) + Net("fet_e" "(unknown)") + ( + Connect("J2-6") + Connect("Q3-5") + Connect("Q3-6") + Connect("R18-1") + ) + Net("fet_f" "(unknown)") + ( + Connect("J2-4") + Connect("Q3-7") + Connect("Q3-8") + Connect("R17-1") + ) + Net("fire_a" "(unknown)") + ( + Connect("R2-2") + Connect("R8-1") + Connect("U7-87") + ) + Net("fire_b" "(unknown)") + ( + Connect("R1-2") + Connect("R7-1") + Connect("U7-88") + ) + Net("fire_c" "(unknown)") + ( + Connect("R4-2") + Connect("R10-1") + Connect("U7-91") + ) + Net("fire_d" "(unknown)") + ( + Connect("R3-2") + Connect("R9-1") + Connect("U7-3") + ) + Net("fire_e" "(unknown)") + ( + Connect("R6-2") + Connect("R12-1") + Connect("U7-5") + ) + Net("fire_f" "(unknown)") + ( + Connect("R5-2") + Connect("R11-1") + Connect("U7-4") + ) + Net("GND" "(unknown)") + ( + Connect("B1-2") + Connect("C4-1") + Connect("C5-1") + Connect("C10-1") + Connect("C21-1") + Connect("C22-1") + Connect("C32-2") + Connect("C33-2") + Connect("C36-1") + Connect("C37-1") + Connect("C38-2") + Connect("C39-1") + Connect("C101-1") + Connect("C102-1") + Connect("C103-1") + Connect("C301-1") + Connect("C302-1") + Connect("C303-1") + Connect("C403-1") + Connect("C404-1") + Connect("C405-1") + Connect("C600-1") + Connect("C601-2") + Connect("C602-2") + Connect("C610-1") + Connect("D2-3") + Connect("D2-4") + Connect("H1-1") + Connect("H2-1") + Connect("H3-1") + Connect("H4-1") + Connect("J1-9") + Connect("J2-3") + Connect("J5-5") + Connect("J9-1") + Connect("J20-1") + Connect("J21-1") + Connect("Q1-1") + Connect("Q1-3") + Connect("Q2-1") + Connect("Q2-3") + Connect("Q3-1") + Connect("Q3-3") + Connect("R1-1") + Connect("R2-1") + Connect("R3-1") + Connect("R4-1") + Connect("R5-1") + Connect("R6-1") + Connect("R19-1") + Connect("R20-1") + Connect("R21-1") + Connect("R22-1") + Connect("R23-1") + Connect("R24-1") + Connect("R26-1") + Connect("R28-1") + Connect("R35-1") + Connect("R37-1") + Connect("R39-1") + Connect("R51-1") + Connect("R401-2") + Connect("R402-2") + Connect("U1-2") + Connect("U2-2") + Connect("U3-2") + Connect("U3-4") + Connect("U3-7") + Connect("U3-13") + Connect("U3-16") + Connect("U3-17") + Connect("U4-2") + Connect("U4-3") + Connect("U5-4") + Connect("U7-10") + Connect("U7-19") + Connect("U7-20") + Connect("U7-27") + Connect("U7-49") + Connect("U7-74") + Connect("U7-99") + Connect("U8-1") + Connect("U9-9") + Connect("U9-11") + Connect("U11-3") + Connect("U12-1") + Connect("U12-18") + Connect("U13-4") + Connect("U14-4") + Connect("U15-4") + Connect("X2-2") + Connect("X2-4") + ) + Net("gyro_int" "(unknown)") + ( + Connect("U7-97") + Connect("U12-12") + ) + Net("led_green" "(unknown)") + ( + Connect("R53-2") + Connect("U7-66") + ) + Net("led_red" "(unknown)") + ( + Connect("R52-2") + Connect("U7-65") + ) + Net("mag_int" "(unknown)") + ( + Connect("U7-80") + Connect("U9-15") + ) + Net("miso1" "(unknown)") + ( + Connect("U3-8") + Connect("U7-45") + Connect("U12-9") + ) + Net("miso2" "(unknown)") + ( + Connect("J9-4") + Connect("R104-2") + Connect("U5-2") + ) + Net("mosi1" "(unknown)") + ( + Connect("U3-11") + Connect("U7-46") + Connect("U12-24") + ) + Net("mosi2" "(unknown)") + ( + Connect("C405-2") + Connect("J9-3") + Connect("R105-1") + Connect("U5-5") + ) + Net("reset_n" "(unknown)") + ( + Connect("C610-2") + Connect("J20-2") + Connect("J21-2") + Connect("U7-14") + Connect("U11-1") + ) + Net("rx1" "(unknown)") + ( + Connect("J21-5") + Connect("U7-69") + ) + Net("sck1" "(unknown)") + ( + Connect("U3-10") + Connect("U7-44") + Connect("U12-23") + ) + Net("sck2" "(unknown)") + ( + Connect("C403-2") + Connect("J9-2") + Connect("R103-1") + Connect("U5-6") + ) + Net("scl1" "(unknown)") + ( + Connect("R901-1") + Connect("U7-95") + Connect("U9-1") + ) + Net("sda1" "(unknown)") + ( + Connect("R900-1") + Connect("U7-96") + Connect("U9-16") + ) + Net("sense_a" "(unknown)") + ( + Connect("R14-2") + Connect("R20-2") + Connect("U7-23") + ) + Net("sense_b" "(unknown)") + ( + Connect("R13-2") + Connect("R19-2") + Connect("U7-24") + ) + Net("sense_c" "(unknown)") + ( + Connect("R16-2") + Connect("R22-2") + Connect("U7-25") + ) + Net("sense_d" "(unknown)") + ( + Connect("R15-2") + Connect("R21-2") + Connect("U7-26") + ) + Net("sense_e" "(unknown)") + ( + Connect("R18-2") + Connect("R24-2") + Connect("U7-29") + ) + Net("sense_f" "(unknown)") + ( + Connect("R17-2") + Connect("R23-2") + Connect("U7-38") + ) + Net("swclk" "(unknown)") + ( + Connect("J20-4") + Connect("U7-76") + ) + Net("swdio" "(unknown)") + ( + Connect("J20-3") + Connect("U7-72") + ) + Net("tx1" "(unknown)") + ( + Connect("J21-4") + Connect("U7-68") + ) + Net("unnamed_net1" "(unknown)") + ( + Connect("Q1-2") + Connect("R7-2") + Connect("U13-7") + ) + Net("unnamed_net2" "(unknown)") + ( + Connect("Q1-4") + Connect("R8-2") + Connect("U13-1") + ) + Net("unnamed_net3" "(unknown)") + ( + Connect("C38-1") + Connect("U1-4") + ) + Net("unnamed_net4" "(unknown)") + ( + Connect("D1-1") + Connect("D1-4") + Connect("U2-1") + ) + Net("unnamed_net5" "(unknown)") + ( + Connect("R35-2") + Connect("U2-5") + ) + Net("unnamed_net6" "(unknown)") + ( + Connect("Q2-4") + Connect("R9-2") + Connect("U14-7") + ) + Net("unnamed_net7" "(unknown)") + ( + Connect("Q2-2") + Connect("R10-2") + Connect("U14-1") + ) + Net("unnamed_net8" "(unknown)") + ( + Connect("Q3-4") + Connect("R12-2") + Connect("U15-1") + ) + Net("unnamed_net9" "(unknown)") + ( + Connect("Q3-2") + Connect("R11-2") + Connect("U15-7") + ) + Net("unnamed_net10" "(unknown)") + ( + Connect("C33-1") + Connect("U7-13") + Connect("X2-3") + ) + Net("unnamed_net11" "(unknown)") + ( + Connect("C32-1") + Connect("U7-12") + Connect("X2-1") + ) + Net("unnamed_net12" "(unknown)") + ( + Connect("R401-1") + Connect("U7-37") + ) + Net("unnamed_net13" "(unknown)") + ( + Connect("C404-2") + Connect("R104-1") + Connect("U7-53") + ) + Net("unnamed_net14" "(unknown)") + ( + Connect("R103-2") + Connect("U7-52") + ) + Net("unnamed_net15" "(unknown)") + ( + Connect("R105-2") + Connect("U7-54") + ) + Net("unnamed_net16" "(unknown)") + ( + Connect("C302-2") + Connect("U12-10") + ) + Net("unnamed_net17" "(unknown)") + ( + Connect("C303-2") + Connect("U12-20") + ) + Net("unnamed_net18" "(unknown)") + ( + Connect("J5-2") + Connect("R54-2") + ) + Net("unnamed_net19" "(unknown)") + ( + Connect("J5-3") + Connect("R55-2") + ) + Net("unnamed_net20" "(unknown)") + ( + Connect("D1-2") + Connect("R50-1") + ) + Net("unnamed_net21" "(unknown)") + ( + Connect("D1-3") + Connect("R51-2") + ) + Net("unnamed_net22" "(unknown)") + ( + Connect("D2-2") + Connect("R52-1") + ) + Net("unnamed_net23" "(unknown)") + ( + Connect("D2-1") + Connect("R53-1") + ) + Net("unnamed_net24" "(unknown)") + ( + Connect("C102-2") + Connect("U3-3") + ) + Net("unnamed_net25" "(unknown)") + ( + Connect("C103-2") + Connect("U3-1") + ) + Net("unnamed_net26" "(unknown)") + ( + Connect("C20-1") + Connect("U9-12") + ) + Net("unnamed_net27" "(unknown)") + ( + Connect("C20-2") + Connect("U9-8") + ) + Net("unnamed_net28" "(unknown)") + ( + Connect("C21-2") + Connect("U9-10") + ) + Net("usbdm" "(unknown)") + ( + Connect("R54-1") + Connect("U7-70") + ) + Net("usbdp" "(unknown)") + ( + Connect("R55-1") + Connect("U7-71") + ) + Net("v_batt" "(unknown)") + ( + Connect("R25-1") + Connect("R26-2") + Connect("U7-35") + ) + Net("v_charge" "(unknown)") + ( + Connect("B1-1") + Connect("C5-2") + Connect("J2-1") + Connect("U2-3") + ) + Net("v_ldo_in" "(unknown)") + ( + Connect("C39-2") + Connect("D3-2") + Connect("R36-2") + Connect("U1-1") + Connect("U1-3") + ) + Net("v_lipo" "(unknown)") + ( + Connect("D3-1") + Connect("J1-7") + Connect("J2-2") + Connect("J9-8") + Connect("R25-2") + ) + Net("v_pbatt" "(unknown)") + ( + Connect("R27-1") + Connect("R28-2") + Connect("U7-36") + ) + Net("v_pyro" "(unknown)") + ( + Connect("J1-1") + Connect("J1-3") + Connect("J1-5") + Connect("J1-8") + Connect("J2-5") + Connect("J2-7") + Connect("J2-9") + Connect("R27-2") + ) + Net("v_usb" "(unknown)") + ( + Connect("C4-2") + Connect("J5-1") + Connect("R50-2") + Connect("U2-4") + ) + Net("vdda" "(unknown)") + ( + Connect("C601-1") + Connect("C602-1") + Connect("L600-2") + Connect("U7-22") + ) +) diff --git a/easymega.sch b/easymega.sch new file mode 100644 index 0000000..2afc93b --- /dev/null +++ b/easymega.sch @@ -0,0 +1,2987 @@ +v 20130925 2 +C 40000 40000 0 0 0 title-E-bdale.sym +N 51400 61900 50600 61900 4 +{ +T 50900 62000 5 10 1 1 0 0 1 +netname=v_usb +} +N 59400 44000 56300 44000 4 +{ +T 56300 44100 5 10 1 1 0 0 1 +netname=v_usb +} +C 61700 41300 1 0 0 gnd.sym +N 61800 43200 61800 41600 4 +C 57500 42400 1 90 0 capacitor.sym +{ +T 56800 42600 5 10 0 0 90 0 1 +device=CAPACITOR +T 57100 43100 5 10 1 1 180 0 1 +refdes=C4 +T 56600 42600 5 10 0 0 90 0 1 +symversion=0.1 +T 56700 42500 5 10 1 1 0 0 1 +value=4.7uF +T 57500 42400 5 10 0 0 0 0 1 +vendor_part_number=445-5947-1-ND +T 57500 42400 5 10 0 0 0 0 1 +footprint=0402 +T 57500 42400 5 10 0 0 0 0 1 +vendor=digikey +T 57500 42400 5 10 0 1 0 0 1 +loadstatus=smt +} +N 57300 42400 57300 41600 4 +N 57300 41600 69100 41600 4 +N 63000 44000 63000 43000 4 +C 63600 43500 1 270 0 battery.sym +{ +T 64500 43200 5 10 0 1 270 0 1 +device=CONNECTOR +T 64100 43400 5 10 1 1 0 0 1 +refdes=B1 +T 64900 43200 5 10 0 0 270 0 1 +symversion=0.1 +T 64100 43000 5 10 1 1 0 0 1 +value=LiPo +T 63600 43500 5 10 0 0 0 0 1 +footprint=B2B-PH +T 63600 43500 5 10 0 0 0 0 1 +vendor_part_number=A100034-ND +T 63600 43500 5 10 0 0 0 0 1 +loadstatus=throughhole +T 63600 43500 5 10 0 0 0 0 1 +vendor=digikey +T 63600 43500 5 10 0 1 0 0 1 +device=CONNECTOR +} +N 63000 42100 63000 41600 4 +N 69100 41600 69100 43100 4 +C 50700 60000 1 0 1 gnd.sym +T 78900 41900 9 30 1 0 0 0 1 +EasyMega +N 51500 50200 53600 50200 4 +{ +T 53200 50300 5 10 1 1 0 0 1 +netname=fet_b +} +C 51500 48500 1 0 0 gnd.sym +C 45200 48500 1 0 0 gnd.sym +N 47800 49000 49200 49000 4 +{ +T 47800 49100 5 10 1 1 0 0 1 +netname=fire_b +} +N 42900 49000 41500 49000 4 +{ +T 41500 49100 5 10 1 1 0 0 1 +netname=fire_a +} +N 45200 49800 45400 49800 4 +N 52600 49800 53600 49800 4 +{ +T 52900 49900 5 10 1 1 0 0 1 +netname=sense_b +} +N 46300 49800 47300 49800 4 +{ +T 46600 49900 5 10 1 1 0 0 1 +netname=sense_a +} +T 13300 -8600 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T 13300 -8600 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +N 64500 44000 65000 44000 4 +{ +T 64500 44100 5 10 1 1 0 0 1 +netname=v_lipo +} +N 63800 43500 63800 44000 4 +N 63800 42800 63800 41600 4 +T 63300 44800 9 10 1 0 0 0 2 + external power switch +attached to pyro header +C 63900 48300 1 90 0 resistor.sym +{ +T 63500 48600 5 10 0 0 90 0 1 +device=RESISTOR +T 64400 49000 5 10 1 1 180 0 1 +refdes=R25 +T 64000 48500 5 10 1 1 0 0 1 +value=5.6k +T 63900 48300 5 10 0 1 0 0 1 +footprint=0402 +T 63900 48300 5 10 0 1 0 0 1 +vendor_part_number=P5.60KLCT-ND +T 63900 48300 5 10 0 0 0 0 1 +vendor=digikey +T 63900 48300 5 10 0 1 0 0 1 +loadstatus=smt +} +C 63900 47200 1 90 0 resistor.sym +{ +T 63500 47500 5 10 0 0 90 0 1 +device=RESISTOR +T 64400 47900 5 10 1 1 180 0 1 +refdes=R26 +T 64000 47400 5 10 1 1 0 0 1 +value=10k +T 63900 47200 5 10 0 1 0 0 1 +vendor_part_number=P10.0KLCT-ND +T 63900 47200 5 10 0 1 0 0 1 +footprint=0402 +T 63900 47200 5 10 0 0 0 0 1 +vendor=digikey +T 63900 47200 5 10 0 1 0 0 1 +loadstatus=smt +} +N 63800 48300 63800 48100 4 +N 63800 48200 65100 48200 4 +{ +T 64600 48300 5 10 1 1 0 0 1 +netname=v_batt +} +N 63800 49200 62900 49200 4 +{ +T 62900 49300 5 10 1 1 0 0 1 +netname=v_lipo +} +C 63700 46900 1 0 0 gnd.sym +T 64600 48800 9 10 1 0 0 0 2 +Tolerate up to +5V charging +N 68000 43600 67900 43600 4 +N 67900 43600 67900 44000 4 +T 82400 40400 9 10 1 0 0 0 1 +0.4 +T 80000 40400 9 10 1 0 0 0 1 +1 +T 80600 40400 9 10 1 0 0 0 1 +1 +T 77700 40400 9 10 1 0 0 0 1 +telemega.sch +T 77700 40100 9 10 1 0 0 0 1 +http://altusmetrum.com/EasyMega +N 78100 57000 77200 57000 4 +{ +T 77200 57100 5 10 1 1 0 0 1 +netname=miso2 +} +N 78100 57400 77200 57400 4 +{ +T 77200 57500 5 10 1 1 0 0 1 +netname=mosi2 +} +N 78100 57800 77200 57800 4 +{ +T 77200 57900 5 10 1 1 0 0 1 +netname=sck2 +} +C 79100 59500 1 0 0 3.3V-plus.sym +C 79200 55500 1 0 0 gnd.sym +T 13300 -8600 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T 13300 -8600 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +C 49200 48100 1 90 0 resistor.sym +{ +T 48800 48400 5 10 0 0 90 0 1 +device=RESISTOR +T 48900 48800 5 10 1 1 180 0 1 +refdes=R1 +T 49200 48095 5 10 0 1 90 0 1 +footprint=0402 +T 48600 48300 5 10 1 1 0 0 1 +value=3.3k +T 49200 48100 5 10 0 1 0 0 1 +vendor_part_number=P3.30KLCT-ND +T 49200 48100 5 10 0 0 0 0 1 +vendor=digikey +T 49200 48100 5 10 0 1 0 0 1 +loadstatus=smt +} +C 49000 47800 1 0 0 gnd.sym +C 42700 47800 1 0 0 gnd.sym +C 80300 63600 1 0 0 hole_plated.sym +{ +T 80400 65400 5 10 0 0 0 0 1 +device=HOLE_PLATED +T 79900 63800 5 10 1 1 0 0 1 +refdes=H1 +T 80300 63600 5 10 0 0 0 0 1 +footprint=hole-M3 +T 80300 63600 5 10 0 1 0 0 1 +loadstatus=noload +T 80300 63600 5 10 0 1 0 0 1 +nobom=1 +} +T 80000 64400 9 10 1 0 0 0 2 +mounting holes +for 4-40 screws +C 81400 60300 1 0 0 gnd.sym +N 80900 62800 81500 62800 4 +N 80900 63800 81500 63800 4 +N 81500 60600 81500 63800 4 +C 80300 62600 1 0 0 hole_plated.sym +{ +T 80400 64400 5 10 0 0 0 0 1 +device=HOLE_PLATED +T 79900 62800 5 10 1 1 0 0 1 +refdes=H2 +T 80300 62600 5 10 0 0 0 0 1 +footprint=hole-M3 +T 80300 62600 5 10 0 1 0 0 1 +loadstatus=noload +T 80300 62600 5 10 0 1 0 0 1 +nobom=1 +} +C 71200 44000 1 0 0 3.3V-plus.sym +C 80300 61700 1 0 0 hole_plated.sym +{ +T 80400 63500 5 10 0 0 0 0 1 +device=HOLE_PLATED +T 79900 61900 5 10 1 1 0 0 1 +refdes=H3 +T 80300 61700 5 10 0 0 0 0 1 +footprint=hole-M3 +T 80300 61700 5 10 0 1 0 0 1 +loadstatus=noload +T 80300 61700 5 10 0 1 0 0 1 +nobom=1 +} +C 80300 60700 1 0 0 hole_plated.sym +{ +T 80400 62500 5 10 0 0 0 0 1 +device=HOLE_PLATED +T 79900 60900 5 10 1 1 0 0 1 +refdes=H4 +T 80300 60700 5 10 0 0 0 0 1 +footprint=hole-M3 +T 80300 60700 5 10 0 1 0 0 1 +loadstatus=noload +T 80300 60700 5 10 0 1 0 0 1 +nobom=1 +} +N 80900 61900 81500 61900 4 +N 80900 60900 81500 60900 4 +N 45200 50200 47300 50200 4 +{ +T 46900 50300 5 10 1 1 0 0 1 +netname=fet_a +} +C 49200 48900 1 0 0 resistor.sym +{ +T 49500 49300 5 10 0 0 0 0 1 +device=RESISTOR +T 49600 49300 5 10 1 1 180 0 1 +refdes=R7 +T 50000 49300 5 10 1 1 180 0 1 +value=549 +T 49200 48900 5 10 0 0 90 0 1 +footprint=0402 +T 49200 48900 5 10 0 0 90 0 1 +vendor_part_number=P549LCT-ND +T 49200 48900 5 10 0 0 0 0 1 +vendor=digikey +T 49200 48900 5 10 0 1 0 0 1 +loadstatus=smt +} +C 42900 48900 1 0 0 resistor.sym +{ +T 43200 49300 5 10 0 0 0 0 1 +device=RESISTOR +T 43300 49300 5 10 1 1 180 0 1 +refdes=R8 +T 43700 49300 5 10 1 1 180 0 1 +value=549 +T 42900 48900 5 10 0 0 90 0 1 +footprint=0402 +T 42900 48900 5 10 0 0 90 0 1 +vendor_part_number=P549LCT-ND +T 42900 48900 5 10 0 0 0 0 1 +vendor=digikey +T 42900 48900 5 10 0 1 0 0 1 +loadstatus=smt +} +N 50100 49000 50600 49000 4 +N 43800 49000 44300 49000 4 +N 80500 56600 81300 56600 4 +{ +T 80700 56700 5 10 1 1 0 0 1 +netname=cs_flash +} +C 45400 49700 1 0 0 resistor.sym +{ +T 45700 50100 5 10 0 0 0 0 1 +device=RESISTOR +T 45600 50000 5 10 1 1 0 0 1 +refdes=R14 +T 45600 49500 5 10 1 1 0 0 1 +value=100k +T 45400 49700 5 10 0 0 0 0 1 +footprint=0402 +T 45400 49700 5 10 0 1 0 0 1 +vendor_part_number=P100KLCT-ND +T 45400 49700 5 10 0 0 0 0 1 +vendor=digikey +T 45400 49700 5 10 0 1 0 0 1 +loadstatus=smt +} +C 52800 48900 1 90 0 resistor.sym +{ +T 52400 49200 5 10 0 0 90 0 1 +device=RESISTOR +T 53200 49600 5 10 1 1 180 0 1 +refdes=R19 +T 52800 48895 5 10 0 1 90 0 1 +footprint=0402 +T 52800 48900 5 10 0 0 90 0 1 +vendor_part_number=P27.0KLCT-ND +T 52900 49100 5 10 1 1 0 0 1 +value=27k +T 52800 48900 5 10 0 0 0 0 1 +vendor=digikey +T 52800 48900 5 10 0 1 0 0 1 +loadstatus=smt +} +C 52600 48600 1 0 0 gnd.sym +C 46300 48600 1 0 0 gnd.sym +C 46500 48900 1 90 0 resistor.sym +{ +T 46100 49200 5 10 0 0 90 0 1 +device=RESISTOR +T 47000 49600 5 10 1 1 180 0 1 +refdes=R20 +T 46500 48895 5 10 0 1 90 0 1 +footprint=0402 +T 46500 48900 5 10 0 0 90 0 1 +vendor_part_number=P27.0KLCT-ND +T 46700 49100 5 10 1 1 0 0 1 +value=27k +T 46500 48900 5 10 0 0 0 0 1 +vendor=digikey +T 46500 48900 5 10 0 1 0 0 1 +loadstatus=smt +} +C 76800 63600 1 0 0 gnd.sym +N 75500 61900 77200 61900 4 +{ +T 75500 62000 5 10 1 1 0 0 1 +netname=cs_companion0 +} +N 77200 63500 75500 63500 4 +{ +T 75500 63600 5 10 1 1 0 0 1 +netname=sck2 +} +N 75500 63100 77200 63100 4 +{ +T 75500 63200 5 10 1 1 0 0 1 +netname=mosi2 +} +N 77200 62700 75500 62700 4 +{ +T 75500 62800 5 10 1 1 0 0 1 +netname=miso2 +} +N 77200 61100 75500 61100 4 +{ +T 75500 61200 5 10 1 1 0 0 1 +netname=v_lipo +} +N 76900 63900 77200 63900 4 +N 70100 44000 72700 44000 4 +C 50600 48700 1 0 0 FDS9926A.sym +{ +T 50600 49900 5 10 1 1 0 0 1 +refdes=Q1 +T 50638 48708 5 10 0 1 0 0 1 +device=MOSFET +T 50295 48670 5 10 0 1 0 0 1 +footprint=1212-8 +T 50600 48700 5 10 0 0 0 0 1 +slot=1 +T 50600 48700 5 10 0 0 0 0 1 +vendor_part_number=781-SI7232DN-GE3 +T 50600 48700 5 10 1 1 0 0 1 +value=Si7232DN +T 50600 48700 5 10 0 0 0 0 1 +vendor=mouser +T 50600 48700 5 10 0 1 0 0 1 +loadstatus=smt +} +C 44300 48700 1 0 0 FDS9926A.sym +{ +T 44300 49900 5 10 1 1 0 0 1 +refdes=Q1 +T 44338 48708 5 10 0 1 0 0 1 +device=MOSFET +T 43995 48670 5 10 0 1 0 0 1 +footprint=1212-8 +T 44300 48700 5 10 0 0 0 0 1 +slot=2 +T 44300 48700 5 10 0 1 0 0 1 +vendor_part_number=781-SI7232DN-GE3 +T 44300 48700 5 10 1 1 0 0 1 +value=Si7232DN +T 44300 48700 5 10 0 0 0 0 1 +vendor=mouser +T 44300 48700 5 10 0 1 0 0 1 +loadstatus=smt +} +N 51500 49000 51600 49000 4 +N 51600 49000 51600 48800 4 +N 45200 49000 45300 49000 4 +N 45300 49000 45300 48800 4 +N 51500 49800 51700 49800 4 +N 51600 49800 51600 50200 4 +N 45300 49800 45300 50200 4 +C 74600 61700 1 0 0 3.3V-plus.sym +N 77200 61500 74800 61500 4 +N 74800 61500 74800 61700 4 +L 64300 44600 64300 44200 3 0 0 0 -1 -1 +N 61800 44000 64000 44000 4 +{ +T 63200 44100 5 10 1 1 0 0 1 +netname=v_charge +} +C 67700 68800 1 0 1 beeper.sym +{ +T 67400 69700 5 10 0 0 0 6 1 +device=BEEPER +T 67600 69400 5 10 1 1 0 6 1 +refdes=U8 +T 67400 69900 5 10 0 0 0 6 1 +symversion=0.1 +T 67700 68800 5 10 0 1 0 6 1 +vendor_part_number=445-2525-1-ND +T 67700 68800 5 10 0 1 0 6 1 +footprint=TDK_PS12 +T 67700 68800 5 10 0 0 0 6 1 +vendor=digikey +T 67700 68800 5 10 0 1 0 6 1 +value=TDK_PS12 +T 67700 68800 5 10 0 0 0 6 1 +loadstatus=throughhole +} +C 67900 68800 1 0 1 gnd.sym +N 64300 69100 66700 69100 4 +{ +T 65600 69200 5 10 1 1 0 6 1 +netname=beeper +} +N 67700 69100 67800 69100 4 +C 70500 63100 1 0 0 3.3V-plus.sym +C 70900 62000 1 90 0 capacitor.sym +{ +T 70200 62200 5 10 0 0 90 0 1 +device=CAPACITOR +T 70400 62700 5 10 1 1 180 0 1 +refdes=C36 +T 70000 62200 5 10 0 0 90 0 1 +symversion=0.1 +T 70100 62100 5 10 1 1 0 0 1 +value=0.1uF +T 70900 62000 5 10 0 0 0 0 1 +footprint=0402 +T 70900 62000 5 10 0 0 0 0 1 +vendor_part_number=399-3027-1-ND +T 70900 62000 5 10 0 0 0 0 1 +vendor=digikey +T 70900 62000 5 10 0 1 0 0 1 +loadstatus=smt +} +C 72000 61500 1 0 0 gnd.sym +N 80500 58600 80600 58600 4 +N 79300 59300 79300 59500 4 +N 79300 59400 80600 59400 4 +N 80600 58200 80600 59400 4 +N 80600 58200 80500 58200 4 +C 71600 43100 1 90 0 capacitor.sym +{ +T 70900 43300 5 10 0 0 90 0 1 +device=CAPACITOR +T 71900 43900 5 10 1 1 180 0 1 +refdes=C37 +T 70700 43300 5 10 0 0 90 0 1 +symversion=0.1 +T 71500 43200 5 10 1 1 0 0 1 +value=1uF +T 71600 43100 5 10 0 0 0 0 1 +vendor_part_number=490-1320-1-ND +T 71600 43100 5 10 0 0 0 0 1 +footprint=0402 +T 71600 43100 5 10 0 0 0 0 1 +vendor=digikey +T 71600 43100 5 10 0 1 0 0 1 +loadstatus=smt +} +C 71300 42800 1 0 0 gnd.sym +C 70200 43600 1 270 0 capacitor.sym +{ +T 70900 43400 5 10 0 0 270 0 1 +device=CAPACITOR +T 70600 43400 5 10 1 1 0 0 1 +refdes=C38 +T 71100 43400 5 10 0 0 270 0 1 +symversion=0.1 +T 70600 42800 5 10 1 1 0 0 1 +value=10nF +T 70200 43600 5 10 0 0 270 0 1 +vendor_part_number=709-1132-1-ND +T 70200 43600 5 10 0 0 270 0 1 +footprint=0402 +T 70200 43600 5 10 0 0 270 0 1 +vendor=digikey +T 70200 43600 5 10 0 1 270 0 1 +loadstatus=smt +} +C 68000 43100 1 0 0 TC2185.sym +{ +T 68295 44295 5 10 1 1 0 0 1 +refdes=U1 +T 68595 43795 5 10 0 1 0 0 1 +device=IC +T 67995 43095 5 10 0 1 0 0 1 +footprint=SOT23-5 +T 68800 44300 5 10 1 1 0 0 1 +value=TC2185-3.3 +T 68000 43100 5 10 0 0 0 0 1 +vendor=digikey +T 68000 43100 5 10 0 0 0 0 1 +vendor_part_number=TC2185-3.3VCCT-ND +T 68000 43100 5 10 0 0 0 0 1 +loadstatus=smt +} +C 70300 42400 1 0 0 gnd.sym +N 70100 43600 70400 43600 4 +C 73100 62300 1 0 1 MCP130T.sym +{ +T 72805 63295 5 10 1 1 0 6 1 +refdes=U11 +T 72305 63295 5 10 1 1 0 6 1 +value=MCP130T-300 +T 73105 62295 5 10 0 1 0 6 1 +device=IC +T 72205 63295 5 10 0 1 0 6 1 +footprint=SOT23 +T 73100 62300 5 10 0 1 0 0 1 +vendor=digikey +T 73100 62300 5 10 0 1 0 0 1 +vendor_part_number=MCP130T-300I/TTCT-ND +T 73100 62300 5 10 0 1 0 0 1 +loadstatus=smt +} +N 70700 63100 70700 62900 4 +N 70700 63000 71100 63000 4 +N 70700 61900 72100 61900 4 +N 72100 61800 72100 62300 4 +N 70700 61900 70700 62000 4 +C 78100 55800 1 0 0 W25Q.sym +{ +T 79155 57400 5 10 0 1 0 0 1 +device=IC +T 78095 55795 5 10 0 1 0 0 1 +footprint=SOIJ8 +T 78395 59095 5 10 1 1 0 0 1 +refdes=U5 +T 78100 55800 5 10 0 0 0 0 1 +vendor=digikey +T 79500 59100 5 10 1 1 0 0 1 +value=W25Q64 +T 78100 55800 5 10 0 1 0 0 1 +loadstatus=smt +T 78100 55800 5 10 0 1 0 0 1 +vendor_part_number=W25Q64FVSSIG-ND +} +C 59400 43000 1 0 0 MCP73831.sym +{ +T 60595 44595 5 10 0 1 0 0 1 +device=IC +T 59695 44595 5 10 1 1 0 0 1 +refdes=U2 +T 59395 41095 5 10 0 1 0 0 1 +footprint=SOT23-5 +T 59400 43000 5 10 0 1 0 0 1 +loadstatus=smt +T 59400 43000 5 10 0 1 0 0 1 +vendor=digikey +T 59400 43000 5 10 0 1 0 0 1 +vendor_part_number=MCP73831T-2DCI/OTCT-ND +T 60600 44600 5 10 1 1 0 0 1 +value=MCP73831 +} +N 57300 44000 57300 43300 4 +C 62200 42500 1 90 0 resistor.sym +{ +T 61800 42800 5 10 0 0 90 0 1 +device=RESISTOR +T 62700 43200 5 10 1 1 180 0 1 +refdes=R35 +T 62300 42800 5 10 1 1 0 0 1 +value=2k +T 62200 42500 5 10 0 0 0 0 1 +vendor=digikey +T 62200 42500 5 10 0 0 0 0 1 +vendor_part_number=P2.00KLCT-ND +T 62200 42500 5 10 0 1 0 0 1 +footprint=0402 +T 62200 42500 5 10 0 1 0 0 1 +loadstatus=smt +} +N 61800 43600 62100 43600 4 +N 62100 43600 62100 43400 4 +N 62100 42500 62100 41600 4 +C 63200 42100 1 90 0 capacitor.sym +{ +T 62500 42300 5 10 0 0 90 0 1 +device=CAPACITOR +T 63300 43000 5 10 1 1 180 0 1 +refdes=C5 +T 62300 42300 5 10 0 0 90 0 1 +symversion=0.1 +T 63100 42200 5 10 1 1 0 0 1 +value=4.7uF +T 63200 42100 5 10 0 0 0 0 1 +vendor_part_number=445-5947-1-ND +T 63200 42100 5 10 0 0 0 0 1 +footprint=0402 +T 63200 42100 5 10 0 0 0 0 1 +vendor=digikey +T 63200 42100 5 10 0 1 0 0 1 +loadstatus=smt +} +C 42900 48100 1 90 0 resistor.sym +{ +T 42500 48400 5 10 0 0 90 0 1 +device=RESISTOR +T 42600 48800 5 10 1 1 180 0 1 +refdes=R2 +T 42900 48095 5 10 0 1 90 0 1 +footprint=0402 +T 42300 48300 5 10 1 1 0 0 1 +value=3.3k +T 42900 48100 5 10 0 1 0 0 1 +vendor_part_number=P3.30KLCT-ND +T 42900 48100 5 10 0 0 0 0 1 +vendor=digikey +T 42900 48100 5 10 0 1 0 0 1 +loadstatus=smt +} +C 44300 53800 1 0 0 conn-9.sym +{ +T 44655 57295 5 10 1 1 0 0 1 +refdes=J1 +T 44500 53600 5 10 1 1 0 0 1 +value=Pyro +T 44300 53800 5 10 0 0 0 0 1 +vendor=digikey +T 44300 53800 5 10 0 0 0 0 1 +vendor_part_number=282834-9-ND +T 44300 53800 5 10 0 0 0 0 1 +footprint=282834-9 +T 44300 53800 5 10 0 1 0 0 1 +device=CONNECTOR +T 44300 53800 5 10 0 1 0 0 1 +loadstatus=noload +} +C 46100 57200 1 180 0 conn-9.sym +{ +T 45645 57405 5 10 1 1 180 0 1 +refdes=J2 +T 45900 53700 5 10 1 1 180 0 1 +value=Pyro +T 46100 57200 5 10 0 1 0 0 1 +device=CONNECTOR +T 46100 57200 5 10 0 1 0 0 1 +footprint=282834-9 +T 46100 57200 5 10 0 1 0 0 1 +loadstatus=noload +T 46100 57200 5 10 0 1 0 0 1 +vendor=digikey +T 46100 57200 5 10 0 1 0 0 1 +vendor_part_number=282834-9-ND +} +N 51500 46800 53600 46800 4 +{ +T 53200 46900 5 10 1 1 0 0 1 +netname=fet_d +} +C 51500 45100 1 0 0 gnd.sym +C 45200 45100 1 0 0 gnd.sym +N 47800 45600 49200 45600 4 +{ +T 47800 45700 5 10 1 1 0 0 1 +netname=fire_d +} +N 42900 45600 41500 45600 4 +{ +T 41500 45700 5 10 1 1 0 0 1 +netname=fire_c +} +C 51700 46300 1 0 0 resistor.sym +{ +T 52000 46700 5 10 0 0 0 0 1 +device=RESISTOR +T 51900 46600 5 10 1 1 0 0 1 +refdes=R15 +T 51900 46100 5 10 1 1 0 0 1 +value=100k +T 51700 46300 5 10 0 0 0 0 1 +footprint=0402 +T 51700 46300 5 10 0 1 0 0 1 +vendor_part_number=P100KLCT-ND +T 51700 46300 5 10 0 0 0 0 1 +vendor=digikey +T 51700 46300 5 10 0 1 0 0 1 +loadstatus=smt +} +N 45200 46400 45400 46400 4 +N 52600 46400 53600 46400 4 +{ +T 52900 46500 5 10 1 1 0 0 1 +netname=sense_d +} +N 46300 46400 47300 46400 4 +{ +T 46600 46500 5 10 1 1 0 0 1 +netname=sense_c +} +C 49200 44700 1 90 0 resistor.sym +{ +T 48800 45000 5 10 0 0 90 0 1 +device=RESISTOR +T 48900 45400 5 10 1 1 180 0 1 +refdes=R3 +T 49200 44695 5 10 0 1 90 0 1 +footprint=0402 +T 48600 44900 5 10 1 1 0 0 1 +value=3.3k +T 49200 44700 5 10 0 1 0 0 1 +vendor_part_number=P3.30KLCT-ND +T 49200 44700 5 10 0 0 0 0 1 +vendor=digikey +T 49200 44700 5 10 0 1 0 0 1 +loadstatus=smt +} +C 49000 44400 1 0 0 gnd.sym +C 42700 44400 1 0 0 gnd.sym +N 45200 46800 47300 46800 4 +{ +T 46900 46900 5 10 1 1 0 0 1 +netname=fet_c +} +C 49200 45500 1 0 0 resistor.sym +{ +T 49500 45900 5 10 0 0 0 0 1 +device=RESISTOR +T 49600 45900 5 10 1 1 180 0 1 +refdes=R9 +T 50000 45900 5 10 1 1 180 0 1 +value=549 +T 49200 45500 5 10 0 0 90 0 1 +footprint=0402 +T 49200 45500 5 10 0 0 90 0 1 +vendor_part_number=P549LCT-ND +T 49200 45500 5 10 0 0 0 0 1 +vendor=digikey +T 49200 45500 5 10 0 1 0 0 1 +loadstatus=smt +} +N 50100 45600 50600 45600 4 +N 43800 45600 44300 45600 4 +C 45400 46300 1 0 0 resistor.sym +{ +T 45700 46700 5 10 0 0 0 0 1 +device=RESISTOR +T 45600 46600 5 10 1 1 0 0 1 +refdes=R16 +T 45600 46100 5 10 1 1 0 0 1 +value=100k +T 45400 46300 5 10 0 0 0 0 1 +footprint=0402 +T 45400 46300 5 10 0 1 0 0 1 +vendor_part_number=P100KLCT-ND +T 45400 46300 5 10 0 0 0 0 1 +vendor=digikey +T 45400 46300 5 10 0 1 0 0 1 +loadstatus=smt +} +C 52800 45500 1 90 0 resistor.sym +{ +T 52400 45800 5 10 0 0 90 0 1 +device=RESISTOR +T 53200 46200 5 10 1 1 180 0 1 +refdes=R21 +T 52800 45495 5 10 0 1 90 0 1 +footprint=0402 +T 52800 45500 5 10 0 0 90 0 1 +vendor_part_number=P27.0KLCT-ND +T 52900 45700 5 10 1 1 0 0 1 +value=27k +T 52800 45500 5 10 0 0 0 0 1 +vendor=digikey +T 52800 45500 5 10 0 1 0 0 1 +loadstatus=smt +} +C 52600 45200 1 0 0 gnd.sym +C 46300 45200 1 0 0 gnd.sym +C 46500 45500 1 90 0 resistor.sym +{ +T 46100 45800 5 10 0 0 90 0 1 +device=RESISTOR +T 47000 46200 5 10 1 1 180 0 1 +refdes=R22 +T 46500 45495 5 10 0 1 90 0 1 +footprint=0402 +T 46500 45500 5 10 0 0 90 0 1 +vendor_part_number=P27.0KLCT-ND +T 46700 45700 5 10 1 1 0 0 1 +value=27k +T 46500 45500 5 10 0 0 0 0 1 +vendor=digikey +T 46500 45500 5 10 0 1 0 0 1 +loadstatus=smt +} +C 50600 45300 1 0 0 FDS9926A.sym +{ +T 50600 46500 5 10 1 1 0 0 1 +refdes=Q2 +T 50638 45308 5 10 0 1 0 0 1 +device=MOSFET +T 50295 45270 5 10 0 1 0 0 1 +footprint=1212-8 +T 50600 45300 5 10 0 0 0 0 1 +slot=2 +T 50600 45300 5 10 0 0 0 0 1 +vendor_part_number=781-SI7232DN-GE3 +T 50600 45300 5 10 1 1 0 0 1 +value=Si7232DN +T 50600 45300 5 10 0 0 0 0 1 +vendor=mouser +T 50600 45300 5 10 0 1 0 0 1 +loadstatus=smt +} +C 44300 45300 1 0 0 FDS9926A.sym +{ +T 44300 46500 5 10 1 1 0 0 1 +refdes=Q2 +T 44338 45308 5 10 0 1 0 0 1 +device=MOSFET +T 43995 45270 5 10 0 1 0 0 1 +footprint=1212-8 +T 44300 45300 5 10 0 0 0 0 1 +slot=1 +T 44300 45300 5 10 0 1 0 0 1 +vendor_part_number=781-SI7232DN-GE3 +T 44300 45300 5 10 1 1 0 0 1 +value=Si7232DN +T 44300 45300 5 10 0 0 0 0 1 +vendor=mouser +T 44300 45300 5 10 0 1 0 0 1 +loadstatus=smt +} +N 51500 45600 51600 45600 4 +N 51600 45600 51600 45400 4 +N 45200 45600 45300 45600 4 +N 45300 45600 45300 45400 4 +N 51500 46400 51700 46400 4 +N 51600 46400 51600 46800 4 +N 45300 46400 45300 46800 4 +C 42900 44700 1 90 0 resistor.sym +{ +T 42500 45000 5 10 0 0 90 0 1 +device=RESISTOR +T 42600 45400 5 10 1 1 180 0 1 +refdes=R4 +T 42900 44695 5 10 0 1 90 0 1 +footprint=0402 +T 42300 44900 5 10 1 1 0 0 1 +value=3.3k +T 42900 44700 5 10 0 1 0 0 1 +vendor_part_number=P3.30KLCT-ND +T 42900 44700 5 10 0 0 0 0 1 +vendor=digikey +T 42900 44700 5 10 0 1 0 0 1 +loadstatus=smt +} +N 51500 43400 53600 43400 4 +{ +T 53200 43500 5 10 1 1 0 0 1 +netname=fet_f +} +C 51500 41700 1 0 0 gnd.sym +C 45200 41700 1 0 0 gnd.sym +N 47800 42200 49200 42200 4 +{ +T 47800 42300 5 10 1 1 0 0 1 +netname=fire_f +} +N 42900 42200 41500 42200 4 +{ +T 41500 42300 5 10 1 1 0 0 1 +netname=fire_e +} +C 51700 42900 1 0 0 resistor.sym +{ +T 52000 43300 5 10 0 0 0 0 1 +device=RESISTOR +T 51900 43200 5 10 1 1 0 0 1 +refdes=R17 +T 51900 42700 5 10 1 1 0 0 1 +value=100k +T 51700 42900 5 10 0 0 0 0 1 +footprint=0402 +T 51700 42900 5 10 0 1 0 0 1 +vendor_part_number=P100KLCT-ND +T 51700 42900 5 10 0 0 0 0 1 +vendor=digikey +T 51700 42900 5 10 0 1 0 0 1 +loadstatus=smt +} +N 45200 43000 45400 43000 4 +N 52600 43000 53600 43000 4 +{ +T 52900 43100 5 10 1 1 0 0 1 +netname=sense_f +} +N 46300 43000 47300 43000 4 +{ +T 46600 43100 5 10 1 1 0 0 1 +netname=sense_e +} +C 49200 41300 1 90 0 resistor.sym +{ +T 48800 41600 5 10 0 0 90 0 1 +device=RESISTOR +T 48900 42000 5 10 1 1 180 0 1 +refdes=R5 +T 49200 41295 5 10 0 1 90 0 1 +footprint=0402 +T 48600 41500 5 10 1 1 0 0 1 +value=3.3k +T 49200 41300 5 10 0 1 0 0 1 +vendor_part_number=P3.30KLCT-ND +T 49200 41300 5 10 0 0 0 0 1 +vendor=digikey +T 49200 41300 5 10 0 1 0 0 1 +loadstatus=smt +} +C 49000 41000 1 0 0 gnd.sym +N 45200 43400 47300 43400 4 +{ +T 46900 43500 5 10 1 1 0 0 1 +netname=fet_e +} +C 42900 42100 1 0 0 resistor.sym +{ +T 43200 42500 5 10 0 0 0 0 1 +device=RESISTOR +T 43300 42500 5 10 1 1 180 0 1 +refdes=R12 +T 43700 42500 5 10 1 1 180 0 1 +value=549 +T 42900 42100 5 10 0 0 90 0 1 +footprint=0402 +T 42900 42100 5 10 0 0 90 0 1 +vendor_part_number=P549LCT-ND +T 42900 42100 5 10 0 0 0 0 1 +vendor=digikey +T 42900 42100 5 10 0 1 0 0 1 +loadstatus=smt +} +N 50100 42200 50600 42200 4 +N 43800 42200 44300 42200 4 +C 45400 42900 1 0 0 resistor.sym +{ +T 45700 43300 5 10 0 0 0 0 1 +device=RESISTOR +T 45600 43200 5 10 1 1 0 0 1 +refdes=R18 +T 45600 42700 5 10 1 1 0 0 1 +value=100k +T 45400 42900 5 10 0 0 0 0 1 +footprint=0402 +T 45400 42900 5 10 0 1 0 0 1 +vendor_part_number=P100KLCT-ND +T 45400 42900 5 10 0 0 0 0 1 +vendor=digikey +T 45400 42900 5 10 0 1 0 0 1 +loadstatus=smt +} +C 52800 42100 1 90 0 resistor.sym +{ +T 52400 42400 5 10 0 0 90 0 1 +device=RESISTOR +T 53200 42800 5 10 1 1 180 0 1 +refdes=R23 +T 52800 42095 5 10 0 1 90 0 1 +footprint=0402 +T 52800 42100 5 10 0 0 90 0 1 +vendor_part_number=P27.0KLCT-ND +T 52900 42300 5 10 1 1 0 0 1 +value=27k +T 52800 42100 5 10 0 0 0 0 1 +vendor=digikey +T 52800 42100 5 10 0 1 0 0 1 +loadstatus=smt +} +C 52600 41800 1 0 0 gnd.sym +C 46300 41800 1 0 0 gnd.sym +C 46500 42100 1 90 0 resistor.sym +{ +T 46100 42400 5 10 0 0 90 0 1 +device=RESISTOR +T 47000 42800 5 10 1 1 180 0 1 +refdes=R24 +T 46500 42095 5 10 0 1 90 0 1 +footprint=0402 +T 46500 42100 5 10 0 0 90 0 1 +vendor_part_number=P27.0KLCT-ND +T 46700 42300 5 10 1 1 0 0 1 +value=27k +T 46500 42100 5 10 0 0 0 0 1 +vendor=digikey +T 46500 42100 5 10 0 1 0 0 1 +loadstatus=smt +} +C 50600 41900 1 0 0 FDS9926A.sym +{ +T 50600 43100 5 10 1 1 0 0 1 +refdes=Q3 +T 50638 41908 5 10 0 1 0 0 1 +device=MOSFET +T 50295 41870 5 10 0 1 0 0 1 +footprint=1212-8 +T 50600 41900 5 10 0 0 0 0 1 +slot=1 +T 50600 41900 5 10 0 0 0 0 1 +vendor_part_number=781-SI7232DN-GE3 +T 50600 41900 5 10 1 1 0 0 1 +value=Si7232DN +T 50600 41900 5 10 0 0 0 0 1 +vendor=mouser +T 50600 41900 5 10 0 1 0 0 1 +loadstatus=smt +} +C 44300 41900 1 0 0 FDS9926A.sym +{ +T 44300 43100 5 10 1 1 0 0 1 +refdes=Q3 +T 44338 41908 5 10 0 1 0 0 1 +device=MOSFET +T 43995 41870 5 10 0 1 0 0 1 +footprint=1212-8 +T 44300 41900 5 10 0 0 0 0 1 +slot=2 +T 44300 41900 5 10 0 1 0 0 1 +vendor_part_number=781-SI7232DN-GE3 +T 44300 41900 5 10 1 1 0 0 1 +value=Si7232DN +T 44300 41900 5 10 0 0 0 0 1 +vendor=mouser +T 44300 41900 5 10 0 1 0 0 1 +loadstatus=smt +} +N 51500 42200 51600 42200 4 +N 51600 42200 51600 42000 4 +N 45200 42200 45300 42200 4 +N 45300 42200 45300 42000 4 +N 51500 43000 51700 43000 4 +N 51600 43000 51600 43400 4 +N 45300 43000 45300 43400 4 +C 42900 41300 1 90 0 resistor.sym +{ +T 42500 41600 5 10 0 0 90 0 1 +device=RESISTOR +T 42600 42000 5 10 1 1 180 0 1 +refdes=R6 +T 42900 41295 5 10 0 1 90 0 1 +footprint=0402 +T 42300 41500 5 10 1 1 0 0 1 +value=3.3k +T 42900 41300 5 10 0 1 0 0 1 +vendor_part_number=P3.30KLCT-ND +T 42900 41300 5 10 0 0 0 0 1 +vendor=digikey +T 42900 41300 5 10 0 1 0 0 1 +loadstatus=smt +} +C 42700 41000 1 0 0 gnd.sym +C 46000 54400 1 0 0 gnd.sym +C 44200 53600 1 0 0 gnd.sym +T 47200 54100 9 10 1 0 0 0 1 +switch +N 44300 54700 43400 54700 4 +{ +T 43400 54800 5 10 1 1 0 0 1 +netname=v_lipo +} +N 47000 54300 46100 54300 4 +{ +T 46500 54400 5 10 1 1 0 0 1 +netname=v_lipo +} +N 47000 53900 46100 53900 4 +{ +T 46300 54000 5 10 1 1 0 0 1 +netname=v_charge +} +N 44300 54300 43400 54300 4 +{ +T 43400 54400 5 10 1 1 0 0 1 +netname=v_pyro +} +N 44300 57100 44200 57100 4 +N 44200 54300 44200 57600 4 +N 44300 56300 44200 56300 4 +N 44300 55500 44200 55500 4 +N 44200 57600 46200 57600 4 +N 46200 55500 46200 57600 4 +N 46200 57100 46100 57100 4 +N 46200 56300 46100 56300 4 +N 46200 55500 46100 55500 4 +N 44300 55100 43400 55100 4 +{ +T 43400 55200 5 10 1 1 0 0 1 +netname=fet_a +} +N 44300 55900 43400 55900 4 +{ +T 43400 56000 5 10 1 1 0 0 1 +netname=fet_b +} +N 44300 56700 43400 56700 4 +{ +T 43400 56800 5 10 1 1 0 0 1 +netname=fet_c +} +N 47000 56700 46100 56700 4 +{ +T 46600 56800 5 10 1 1 0 0 1 +netname=fet_d +} +N 47000 55900 46100 55900 4 +{ +T 46600 56000 5 10 1 1 0 0 1 +netname=fet_e +} +N 47000 55100 46100 55100 4 +{ +T 46600 55200 5 10 1 1 0 0 1 +netname=fet_f +} +C 60100 48300 1 90 0 resistor.sym +{ +T 59700 48600 5 10 0 0 90 0 1 +device=RESISTOR +T 60600 49000 5 10 1 1 180 0 1 +refdes=R27 +T 60200 48500 5 10 1 1 0 0 1 +value=100k +T 60100 48300 5 10 0 0 0 0 1 +footprint=0402 +T 60100 48300 5 10 0 0 0 0 1 +vendor_part_number=P100KLCT-ND +T 60100 48300 5 10 0 0 0 0 1 +vendor=digikey +T 60100 48300 5 10 0 1 0 0 1 +loadstatus=smt +} +C 60100 47200 1 90 0 resistor.sym +{ +T 59700 47500 5 10 0 0 90 0 1 +device=RESISTOR +T 60600 47900 5 10 1 1 180 0 1 +refdes=R28 +T 60200 47400 5 10 1 1 0 0 1 +value=27k +T 60100 47200 5 10 0 0 0 0 1 +vendor_part_number=P27.0KLCT-ND +T 60100 47200 5 10 0 0 0 0 1 +footprint=0402 +T 60100 47200 5 10 0 0 0 0 1 +vendor=digikey +T 60100 47200 5 10 0 1 0 0 1 +loadstatus=smt +} +N 60000 48300 60000 48100 4 +N 60000 48200 61300 48200 4 +{ +T 60700 48300 5 10 1 1 0 0 1 +netname=v_pbatt +} +N 60000 49200 59100 49200 4 +{ +T 59100 49300 5 10 1 1 0 0 1 +netname=v_pyro +} +C 59900 46900 1 0 0 gnd.sym +T 60800 48800 9 10 1 0 0 0 2 +Pyro Battery can +be up to 15V +C 54800 51900 1 0 0 STM32L151-100.sym +{ +T 48400 50300 5 10 0 0 0 0 1 +device=IC +T 55200 72000 5 10 1 1 0 0 1 +refdes=U7 +T 54800 51900 5 10 0 0 0 0 1 +footprint=lqfp100 +T 54800 51900 5 10 0 0 0 0 1 +vendor=mouser +T 54800 51900 5 10 0 1 0 0 1 +value=STM32L151VCT6 +T 54800 51900 5 10 0 0 0 0 1 +vendor_part_number=511-STM32L151VCT6 +T 54800 51900 5 10 0 1 0 0 1 +loadstatus=smt +} +C 58200 73300 1 0 0 3.3V-plus.sym +N 58400 72300 58400 73300 4 +N 58400 72400 60400 72400 4 +N 60000 72400 60000 72300 4 +N 59200 72400 59200 72300 4 +N 58800 72400 58800 72300 4 +C 59500 51400 1 0 0 gnd.sym +N 58600 51900 58600 51800 4 +N 58600 51800 60600 51800 4 +N 59600 51700 59600 51800 4 +N 60600 51800 60600 51900 4 +N 60200 51900 60200 51800 4 +N 59800 51900 59800 51800 4 +N 59400 51900 59400 51800 4 +N 59000 51900 59000 51800 4 +C 53200 69900 1 270 0 capacitor.sym +{ +T 53900 69700 5 10 0 0 270 0 1 +device=CAPACITOR +T 53600 69600 5 10 1 1 0 0 1 +refdes=C33 +T 54100 69700 5 10 0 0 270 0 1 +symversion=0.1 +T 53600 69100 5 10 1 1 0 0 1 +value=22pF +T 53200 69900 5 10 0 0 0 0 1 +vendor_part_number=311-1018-1-ND +T 53200 69900 5 10 0 0 0 0 1 +footprint=0402 +T 53200 69900 5 10 0 0 0 0 1 +vendor=digikey +T 53200 69900 5 10 0 1 0 0 1 +loadstatus=smt +} +C 51900 69900 1 270 0 capacitor.sym +{ +T 52600 69700 5 10 0 0 270 0 1 +device=CAPACITOR +T 51600 69600 5 10 1 1 0 0 1 +refdes=C32 +T 52800 69700 5 10 0 0 270 0 1 +symversion=0.1 +T 51500 69100 5 10 1 1 0 0 1 +value=22pF +T 51900 69900 5 10 0 0 0 0 1 +vendor_part_number=311-1018-1-ND +T 51900 69900 5 10 0 0 0 0 1 +footprint=0402 +T 51900 69900 5 10 0 0 0 0 1 +vendor=digikey +T 51900 69900 5 10 0 1 0 0 1 +loadstatus=smt +} +C 53300 68700 1 0 0 gnd.sym +C 52000 68700 1 0 0 gnd.sym +C 52400 69500 1 0 0 ABM8.sym +{ +T 52600 70000 5 10 0 0 0 0 1 +device=CRYSTAL +T 52300 70100 5 10 1 1 0 0 1 +refdes=X2 +T 52600 70200 5 10 0 0 0 0 1 +symversion=0.1 +T 52800 70100 5 10 1 1 0 0 1 +value=8mhz +T 52400 69500 5 10 0 0 0 0 1 +vendor_part_number=535-9721-1-ND +T 52400 69500 5 10 0 0 0 0 1 +footprint=ABM3B +T 52400 69500 5 10 0 0 0 0 1 +vendor=digikey +T 52400 69500 5 10 0 1 0 0 1 +loadstatus=smt +} +C 53000 69200 1 0 0 gnd.sym +C 52300 69200 1 0 0 gnd.sym +N 52400 69900 52100 69900 4 +N 52100 69900 52100 70300 4 +C 42600 70100 1 0 0 MPU6000.sym +{ +T 43895 72295 5 10 0 1 0 0 1 +device=IC +T 42895 73495 5 10 1 1 0 0 1 +refdes=U12 +T 44095 73495 5 10 1 1 0 0 1 +value=MPU-6000 +T 42600 70100 5 10 0 1 0 0 1 +footprint=MPU6000 +T 42600 70100 5 10 0 1 0 0 1 +loadstatus=smt +T 42600 70100 5 10 0 1 0 0 1 +vendor=cdiweb +T 42600 70100 5 10 0 1 0 0 1 +vendor_part_number=MPU-6000 +} +N 45300 70700 46400 70700 4 +{ +T 46000 70800 5 10 1 1 0 0 1 +netname=sck1 +} +N 45300 70300 46400 70300 4 +{ +T 45900 70400 5 10 1 1 0 0 1 +netname=mosi1 +} +C 40500 73100 1 0 0 3.3V-plus.sym +N 40700 73100 42600 73100 4 +C 40900 72200 1 90 0 capacitor.sym +{ +T 40200 72400 5 10 0 0 90 0 1 +device=CAPACITOR +T 40600 72900 5 10 1 1 180 0 1 +refdes=C301 +T 40000 72400 5 10 0 0 90 0 1 +symversion=0.1 +T 40200 72400 5 10 1 1 0 0 1 +value=0.1uF +T 40900 72200 5 10 0 1 0 0 1 +footprint=0402 +T 40900 72200 5 10 0 1 0 0 1 +loadstatus=smt +T 40900 72200 5 10 0 1 0 0 1 +vendor=digikey +T 40900 72200 5 10 0 1 0 0 1 +vendor_part_number=399-3027-1-ND +} +C 42300 71400 1 90 0 capacitor.sym +{ +T 41600 71600 5 10 0 0 90 0 1 +device=CAPACITOR +T 42000 72100 5 10 1 1 180 0 1 +refdes=C303 +T 41400 71600 5 10 0 0 90 0 1 +symversion=0.1 +T 41600 71600 5 10 1 1 0 0 1 +value=10nF +T 42300 71400 5 10 0 1 0 0 1 +footprint=0402 +T 42300 71400 5 10 0 1 0 0 1 +loadstatus=smt +T 42300 71400 5 10 0 1 0 0 1 +vendor=digikey +T 42300 71400 5 10 0 1 0 0 1 +vendor_part_number=709-1132-1-ND +} +C 41600 71800 1 90 0 capacitor.sym +{ +T 40900 72000 5 10 0 0 90 0 1 +device=CAPACITOR +T 41300 72500 5 10 1 1 180 0 1 +refdes=C302 +T 40700 72000 5 10 0 0 90 0 1 +symversion=0.1 +T 40900 72000 5 10 1 1 0 0 1 +value=0.1uF +T 41600 71800 5 10 0 1 0 0 1 +footprint=0402 +T 41600 71800 5 10 0 1 0 0 1 +loadstatus=smt +T 41600 71800 5 10 0 1 0 0 1 +vendor=digikey +T 41600 71800 5 10 0 1 0 0 1 +vendor_part_number=399-3027-1-ND +} +N 40700 70300 42600 70300 4 +N 40700 70300 40700 72200 4 +C 42000 70000 1 0 0 gnd.sym +N 45300 72300 46400 72300 4 +{ +T 45800 72400 5 10 1 1 0 0 1 +netname=gyro_int +} +N 54800 67100 52800 67100 4 +{ +T 53500 67200 5 10 1 1 0 0 1 +netname=reset_n +} +C 50600 59900 1 0 1 USBmicroB.sym +{ +T 49605 62300 5 10 1 1 0 6 1 +refdes=J5 +T 50245 60295 5 10 0 1 0 6 1 +footprint=ZX62-B-5PA +T 50600 59900 5 10 0 0 0 0 1 +vendor=digikey +T 50600 59900 5 10 0 0 0 0 1 +vendor_part_number=H11634CT-ND +T 50600 59900 5 10 0 0 0 0 1 +loadstatus=smt +T 50600 59900 5 10 0 0 0 0 1 +device=CONNECTOR +T 50600 59900 5 10 0 0 0 0 1 +value=USBmicroB +} +N 54800 61500 52900 61500 4 +{ +T 53500 61600 5 10 1 1 0 0 1 +netname=usbdm +} +N 54800 61100 52900 61100 4 +{ +T 53500 61200 5 10 1 1 0 0 1 +netname=usbdp +} +C 53400 58800 1 180 0 resistor.sym +{ +T 53100 58400 5 10 0 0 180 0 1 +device=RESISTOR +T 52550 58875 5 10 1 1 0 0 1 +refdes=R401 +T 53300 59000 5 10 1 1 180 0 1 +value=10k +T 53400 58800 5 10 0 0 90 0 1 +footprint=0402 +T 53400 58800 5 10 0 0 90 0 1 +vendor_part_number=P10.0KLCT-ND +T 53400 58800 5 10 0 0 90 0 1 +vendor=digikey +T 53400 58800 5 10 0 1 90 0 1 +loadstatus=smt +} +C 52400 58400 1 0 0 gnd.sym +N 54800 58700 53400 58700 4 +N 52100 70300 54500 70300 4 +N 54500 70300 54500 69900 4 +N 54500 69900 54800 69900 4 +N 53100 69900 54100 69900 4 +N 54100 69900 54100 69500 4 +N 54100 69500 54800 69500 4 +C 53400 68000 1 180 0 resistor.sym +{ +T 53100 67600 5 10 0 0 180 0 1 +device=RESISTOR +T 52950 68225 5 10 1 1 180 0 1 +refdes=R402 +T 53000 68100 5 10 1 1 0 0 1 +value=10k +T 53400 68000 5 10 0 0 90 0 1 +footprint=0402 +T 53400 68000 5 10 0 0 90 0 1 +vendor_part_number=P10.0KLCT-ND +T 53400 68000 5 10 0 0 90 0 1 +vendor=digikey +T 53400 68000 5 10 0 1 90 0 1 +loadstatus=smt +} +C 52400 67600 1 0 0 gnd.sym +N 53400 67900 54800 67900 4 +{ +T 53500 68000 5 10 1 1 0 0 1 +netname=boot0 +} +N 54800 62300 53500 62300 4 +{ +T 53500 62400 5 10 1 1 0 0 1 +netname=tx1 +} +N 54800 61900 53500 61900 4 +{ +T 53500 62000 5 10 1 1 0 0 1 +netname=rx1 +} +C 71200 58900 1 0 0 gnd.sym +N 71300 58800 72400 58800 4 +{ +T 71800 58900 5 10 1 1 0 0 1 +netname=reset_n +} +N 71300 58400 72400 58400 4 +{ +T 71900 58500 5 10 1 1 0 0 1 +netname=boot0 +} +N 71300 58000 72400 58000 4 +{ +T 72100 58100 5 10 1 1 0 0 1 +netname=tx1 +} +N 71300 57600 72400 57600 4 +{ +T 72100 57700 5 10 1 1 0 0 1 +netname=rx1 +} +N 77200 62300 75500 62300 4 +{ +T 75500 62400 5 10 1 1 0 0 1 +netname=cs_companion1 +} +C 77200 61000 1 0 0 conn-8.sym +{ +T 77555 64095 5 10 1 1 0 0 1 +refdes=J9 +T 77100 60800 5 10 1 1 0 0 1 +value=Companion +T 77200 61000 5 10 0 0 0 0 1 +loadstatus=noload +T 77200 61000 5 10 0 0 0 0 1 +vendor=mouser +T 77200 61000 5 10 0 0 0 0 1 +vendor_part_number=571-338068-8 +T 77200 61000 5 10 0 0 0 0 1 +footprint=0-338068-8 +T 77200 61000 5 10 0 1 0 0 1 +device=CONNECTOR +} +T 70400 57800 9 10 1 0 90 0 2 +bootloader + support +N 54800 60700 53500 60700 4 +{ +T 53500 60800 5 10 1 1 0 0 1 +netname=swdio +} +N 54800 60300 53500 60300 4 +{ +T 53500 60400 5 10 1 1 0 0 1 +netname=swclk +} +N 53900 53500 53300 53500 4 +{ +T 53800 53600 5 10 1 1 0 6 1 +netname=mosi2 +} +N 52600 54300 52100 54300 4 +{ +T 52500 54400 5 10 1 1 0 6 1 +netname=sck2 +} +N 51400 53900 50900 53900 4 +{ +T 51400 54000 5 10 1 1 0 6 1 +netname=miso2 +} +C 53300 70900 1 0 0 capacitor.sym +{ +T 53500 71600 5 10 0 0 0 0 1 +device=CAPACITOR +T 53200 71200 5 10 1 1 0 0 1 +refdes=C600 +T 53500 71800 5 10 0 0 0 0 1 +symversion=0.1 +T 53900 71200 5 10 1 1 0 0 1 +value=0.1uF +T 53300 70900 5 10 0 1 0 0 1 +footprint=0402 +T 53300 70900 5 10 0 1 0 0 1 +loadstatus=smt +T 53300 70900 5 10 0 1 0 0 1 +vendor=digikey +T 53300 70900 5 10 0 1 0 0 1 +vendor_part_number=399-3027-1-ND +} +C 54500 71200 1 0 0 3.3V-plus.sym +C 53200 70400 1 0 0 gnd.sym +N 54700 71100 54700 71200 4 +N 53300 70700 53300 71100 4 +N 54800 70700 53300 70700 4 +N 54800 71100 54200 71100 4 +C 61000 73100 1 0 0 capacitor.sym +{ +T 61200 73800 5 10 0 0 0 0 1 +device=CAPACITOR +T 60900 73400 5 10 1 1 0 0 1 +refdes=C601 +T 61200 74000 5 10 0 0 0 0 1 +symversion=0.1 +T 61600 73400 5 10 1 1 0 0 1 +value=1uF +T 61000 73100 5 10 0 1 0 0 1 +footprint=0402 +T 61000 73100 5 10 0 1 0 0 1 +loadstatus=smt +T 61000 73100 5 10 0 1 0 0 1 +vendor=digikey +T 61000 73100 5 10 0 1 0 0 1 +vendor_part_number=490-1320-1-ND +} +C 61000 72600 1 0 0 capacitor.sym +{ +T 61200 73300 5 10 0 0 0 0 1 +device=CAPACITOR +T 60900 72900 5 10 1 1 0 0 1 +refdes=C602 +T 61200 73500 5 10 0 0 0 0 1 +symversion=0.1 +T 61600 72900 5 10 1 1 0 0 1 +value=0.1uF +T 61000 72600 5 10 0 1 0 0 1 +footprint=0402 +T 61000 72600 5 10 0 1 0 0 1 +loadstatus=smt +T 61000 72600 5 10 0 1 0 0 1 +vendor=digikey +T 61000 72600 5 10 0 1 0 0 1 +vendor_part_number=399-3027-1-ND +} +C 58900 73200 1 0 0 inductor.sym +{ +T 59100 73700 5 10 0 0 0 0 1 +device=INDUCTOR +T 59100 73500 5 10 1 1 0 0 1 +refdes=L600 +T 59100 73900 5 10 0 0 0 0 1 +symversion=0.1 +T 59100 73100 5 10 1 1 0 0 1 +value=bead +T 58900 73200 5 10 0 1 0 0 1 +footprint=0402 +T 58900 73200 5 10 0 1 0 0 1 +vendor=digikey +T 58900 73200 5 10 0 1 0 0 1 +vendor_part_number=240-2554-1-ND +T 58900 73200 5 10 0 1 0 0 1 +loadstatus=smt +} +N 59600 72300 59600 72400 4 +N 58900 73300 58400 73300 4 +N 59800 73300 61000 73300 4 +{ +T 59900 73400 5 10 1 1 0 0 1 +netname=vdda +} +N 60800 73300 60800 72300 4 +N 61000 72800 60800 72800 4 +C 62100 72500 1 0 0 gnd.sym +N 62200 73300 62200 72800 4 +N 62200 72800 61900 72800 4 +N 62200 73300 61900 73300 4 +C 53000 66200 1 90 0 capacitor.sym +{ +T 52300 66400 5 10 0 0 90 0 1 +device=CAPACITOR +T 52700 66900 5 10 1 1 180 0 1 +refdes=C610 +T 52100 66400 5 10 0 0 90 0 1 +symversion=0.1 +T 52200 66400 5 10 1 1 0 0 1 +value=0.1uF +T 53000 66200 5 10 0 1 0 0 1 +footprint=0402 +T 53000 66200 5 10 0 1 0 0 1 +loadstatus=smt +T 53000 66200 5 10 0 1 0 0 1 +vendor=digikey +T 53000 66200 5 10 0 1 0 0 1 +vendor_part_number=399-3027-1-ND +} +C 52700 65900 1 0 0 gnd.sym +N 54800 65900 53500 65900 4 +{ +T 53500 66000 5 10 1 1 0 0 1 +netname=sense_a +} +N 54800 65500 53500 65500 4 +{ +T 53500 65600 5 10 1 1 0 0 1 +netname=sense_b +} +N 54800 65100 53500 65100 4 +{ +T 53500 65200 5 10 1 1 0 0 1 +netname=sense_c +} +N 54800 64700 53500 64700 4 +{ +T 53500 64800 5 10 1 1 0 0 1 +netname=sense_d +} +N 54800 64300 53500 64300 4 +{ +T 53500 64400 5 10 1 1 0 0 1 +netname=sense_e +} +N 65600 55900 64300 55900 4 +{ +T 64900 56000 5 10 1 1 0 0 1 +netname=sense_f +} +N 64300 62700 65600 62700 4 +{ +T 65100 62800 5 10 1 1 0 0 1 +netname=fire_a +} +N 64300 62300 65600 62300 4 +{ +T 65100 62400 5 10 1 1 0 0 1 +netname=fire_b +} +N 54800 57500 53500 57500 4 +{ +T 54000 57600 5 10 1 1 0 6 1 +netname=fire_c +} +N 64300 57100 65600 57100 4 +{ +T 65100 57200 5 10 1 1 0 0 1 +netname=fire_d +} +N 64300 56300 65600 56300 4 +{ +T 65100 56400 5 10 1 1 0 0 1 +netname=fire_e +} +N 64300 56700 65600 56700 4 +{ +T 65100 56800 5 10 1 1 0 0 1 +netname=fire_f +} +C 58300 43000 1 180 1 led2.sym +{ +T 58150 42400 5 10 1 1 180 6 1 +refdes=D1 +T 58200 42400 5 10 0 0 180 6 1 +device=LED +T 58250 43000 5 10 0 1 180 6 1 +footprint=0605 +T 58300 43000 5 10 0 0 0 0 1 +vendor=digikey +T 58300 43000 5 10 0 0 0 0 1 +vendor_part_number=160-1452-1-ND +T 58300 43000 5 10 0 0 0 0 1 +value=dualLED +T 58300 43000 5 10 0 0 0 0 1 +loadstatus=smt +} +C 57900 43100 1 90 0 resistor.sym +{ +T 57500 43400 5 10 0 0 90 0 1 +device=RESISTOR +T 58300 43800 5 10 1 1 180 0 1 +refdes=R50 +T 58200 43500 5 10 1 1 180 0 1 +value=1k +T 57900 43100 5 10 0 0 90 0 1 +footprint=0402 +T 57900 43100 5 10 0 0 90 0 1 +vendor=digikey +T 57900 43100 5 10 0 0 90 0 1 +vendor_part_number=P1.00KLCT-ND +T 57900 43100 5 10 0 0 90 0 1 +loadstatus=smt +} +C 59100 41600 1 90 0 resistor.sym +{ +T 58700 41900 5 10 0 0 90 0 1 +device=RESISTOR +T 59500 42300 5 10 1 1 180 0 1 +refdes=R51 +T 59400 42000 5 10 1 1 180 0 1 +value=1k +T 59100 41600 5 10 0 0 90 0 1 +footprint=0402 +T 59100 41600 5 10 0 0 90 0 1 +vendor=digikey +T 59100 41600 5 10 0 0 90 0 1 +vendor_part_number=P1.00KLCT-ND +T 59100 41600 5 10 0 0 90 0 1 +loadstatus=smt +} +C 67200 68400 1 180 0 resistor.sym +{ +T 66900 68000 5 10 0 0 180 0 1 +device=RESISTOR +T 66800 68500 5 10 1 1 0 0 1 +refdes=R52 +T 66400 68500 5 10 1 1 0 0 1 +value=1k +T 67200 68400 5 10 0 0 180 0 1 +footprint=0402 +T 67200 68400 5 10 0 0 180 0 1 +vendor=digikey +T 67200 68400 5 10 0 0 180 0 1 +vendor_part_number=P1.00KLCT-ND +T 67200 68400 5 10 0 0 180 0 1 +loadstatus=smt +} +C 67200 68000 1 180 0 resistor.sym +{ +T 66900 67600 5 10 0 0 180 0 1 +device=RESISTOR +T 66800 67500 5 10 1 1 0 0 1 +refdes=R53 +T 66400 67500 5 10 1 1 0 0 1 +value=1k +T 67200 68000 5 10 0 0 180 0 1 +footprint=0402 +T 67200 68000 5 10 0 0 180 0 1 +vendor=digikey +T 67200 68000 5 10 0 0 180 0 1 +vendor_part_number=P1.00KLCT-ND +T 67200 68000 5 10 0 0 180 0 1 +loadstatus=smt +} +N 58100 43200 59400 43200 4 +N 59000 43200 59000 42900 4 +N 59000 42900 58700 42900 4 +N 58100 43200 58100 42500 4 +N 58300 42900 57800 42900 4 +N 57800 42900 57800 43100 4 +N 59000 42500 58700 42500 4 +N 58300 42500 58100 42500 4 +C 67900 67600 1 0 1 gnd.sym +N 66300 68300 64300 68300 4 +{ +T 65600 68600 5 10 1 1 180 0 1 +netname=led_red +} +N 66300 67900 64300 67900 4 +{ +T 65600 68150 5 10 1 1 180 0 1 +netname=led_green +} +N 67600 68300 67800 68300 4 +N 67600 67900 67800 67900 4 +C 67200 68400 1 180 1 led2.sym +{ +T 67350 68600 5 10 1 1 180 6 1 +refdes=D2 +T 67100 67800 5 10 0 0 180 6 1 +device=LED +T 67150 68400 5 10 0 1 180 6 1 +footprint=0605 +T 67200 68400 5 10 0 0 0 0 1 +vendor=digikey +T 67200 68400 5 10 0 0 0 0 1 +vendor_part_number=160-1452-1-ND +T 67200 68400 5 10 0 0 0 0 1 +value=dualLED +T 67200 68400 5 10 0 0 0 0 1 +loadstatus=smt +} +N 64300 64700 65600 64700 4 +{ +T 64400 64800 5 10 1 1 0 0 1 +netname=cs_companion1 +} +N 64300 65100 65600 65100 4 +{ +T 64400 65200 5 10 1 1 0 0 1 +netname=cs_companion0 +} +N 64300 63900 65600 63900 4 +{ +T 64900 64000 5 10 1 1 0 0 1 +netname=cs_flash +} +N 64300 58700 65600 58700 4 +{ +T 65000 58800 5 10 1 1 0 0 1 +netname=gyro_int +} +C 71400 57200 1 0 0 3.3V-plus.sym +N 71600 57200 71300 57200 4 +N 73100 63000 74000 63000 4 +{ +T 73400 63100 5 10 1 1 0 0 1 +netname=reset_n +} +N 60400 72400 60400 72300 4 +N 64300 69900 65600 69900 4 +{ +T 64900 70000 5 10 1 1 0 0 1 +netname=cs_pres +} +N 67800 68300 67800 67900 4 +N 54800 59500 53500 59500 4 +{ +T 53500 59600 5 10 1 1 0 0 1 +netname=v_batt +} +N 54800 59100 53500 59100 4 +{ +T 53500 59200 5 10 1 1 0 0 1 +netname=v_pbatt +} +N 42600 72300 42100 72300 4 +N 42100 71400 42100 70300 4 +N 42600 72700 41400 72700 4 +N 41400 71800 41400 70300 4 +C 45400 72800 1 0 0 gnd.sym +N 45300 73100 45500 73100 4 +C 51700 49700 1 0 0 resistor.sym +{ +T 52000 50100 5 10 0 0 0 0 1 +device=RESISTOR +T 51900 50000 5 10 1 1 0 0 1 +refdes=R13 +T 51900 49500 5 10 1 1 0 0 1 +value=100k +T 51700 49700 5 10 0 0 0 0 1 +footprint=0402 +T 51700 49700 5 10 0 1 0 0 1 +vendor_part_number=P100KLCT-ND +T 51700 49700 5 10 0 0 0 0 1 +vendor=digikey +T 51700 49700 5 10 0 1 0 0 1 +loadstatus=smt +} +N 45300 71500 46400 71500 4 +{ +T 45800 71600 5 10 1 1 0 0 1 +netname=cs_gyro +} +N 64300 64300 65600 64300 4 +{ +T 64900 64400 5 10 1 1 0 0 1 +netname=cs_gyro +} +N 45300 71100 46400 71100 4 +{ +T 45900 71200 5 10 1 1 0 0 1 +netname=miso1 +} +T -30400 -57400 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -30400 -57400 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -30400 -57400 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -30400 -57400 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -80000 -109400 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -80000 -109400 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -80000 -109400 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -80000 -109400 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -71200 -97500 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -71200 -97500 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -71200 -97500 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -71200 -97500 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -71200 -97500 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -71200 -97500 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -71200 -97500 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -71200 -97500 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -71200 -97500 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -71200 -97500 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -120500 -148600 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -120500 -148600 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -120500 -148600 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -120500 -148600 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -96200 -124600 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -96200 -124600 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -96200 -124600 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -96200 -124600 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -55100 -54600 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -55100 -54600 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -55100 -54600 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -55100 -54600 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -55100 -54600 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -55100 -54600 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -55100 -54600 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -55100 -54600 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -55100 -54600 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -55100 -54600 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -104400 -105700 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -104400 -105700 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -104400 -105700 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -104400 -105700 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +C 74300 57600 1 0 1 conn-4.sym +{ +T 73900 59200 5 10 1 1 0 6 1 +refdes=J20 +T 74100 57400 5 10 1 1 0 6 1 +value=Debug +T 74300 57600 5 10 0 0 0 6 1 +footprint=0-215079-4 +T 74300 57600 5 10 0 0 0 6 1 +vendor_part_number=571-215079-4 +T 74300 57600 5 10 0 0 0 6 1 +vendor=mouser +T 74300 57600 5 10 0 0 0 6 1 +loadstatus=noload +T 74300 57600 5 10 0 0 0 6 1 +device=CONNECTOR +} +C 74700 58600 1 0 1 gnd.sym +N 74600 58900 74300 58900 4 +N 74300 58500 75600 58500 4 +{ +T 75600 58600 5 10 1 1 0 6 1 +netname=reset_n +} +N 74300 58100 75600 58100 4 +{ +T 75600 58200 5 10 1 1 0 6 1 +netname=swdio +} +N 74300 57700 75600 57700 4 +{ +T 75600 57800 5 10 1 1 0 6 1 +netname=swclk +} +C 71300 57100 1 0 1 conn-6.sym +{ +T 70945 59395 5 10 1 1 0 6 1 +refdes=J21 +T 71300 57100 5 10 0 1 0 0 1 +device=CONNECTOR +T 71300 57100 5 10 0 1 0 0 1 +footprint=0-215079-6 +T 70600 56900 5 10 1 1 0 0 1 +value=Boot +T 71300 57100 5 10 0 1 0 0 1 +loadstatus=noload +} +C 46800 66000 1 0 0 3.3V-plus.sym +C 47200 65100 1 90 0 capacitor.sym +{ +T 46500 65300 5 10 0 0 90 0 1 +device=CAPACITOR +T 46800 65900 5 10 1 1 180 0 1 +refdes=C10 +T 46300 65300 5 10 0 0 90 0 1 +symversion=0.1 +T 46400 65200 5 10 1 1 0 0 1 +value=0.1uF +T 47200 65100 5 10 0 1 0 0 1 +vendor_part_number=399-3027-1-ND +T 47200 65100 5 10 0 0 0 0 1 +footprint=0402 +T 47200 65100 5 10 0 0 0 0 1 +vendor=digikey +T 47200 65100 5 10 0 1 0 0 1 +loadstatus=smt +} +T -28200 -66400 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -28200 -66400 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -28200 -66400 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -28200 -66400 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +C 47400 64200 1 0 0 MS5607.sym +{ +T 48695 66395 5 10 0 1 0 0 1 +device=IC +T 47695 66395 5 10 1 1 0 0 1 +refdes=U4 +T 47395 60995 5 10 0 1 0 0 1 +footprint=MS5607 +T 47400 64200 5 10 0 1 0 0 1 +loadstatus=smt +T 48700 66400 5 10 1 1 0 0 1 +value=MS5607 +T 47400 64200 5 10 0 1 0 0 1 +vendor=measspec +T 47400 64200 5 10 0 1 0 0 1 +vendor_part_number=MS5607 +} +N 47400 66000 47000 66000 4 +N 47400 65200 47400 64400 4 +N 47000 65100 47000 64400 4 +N 47000 64400 47400 64400 4 +C 46900 64100 1 0 0 gnd.sym +N 50600 64400 49700 64400 4 +{ +T 49900 64500 5 10 1 1 0 0 1 +netname=ba_miso1 +} +N 50600 64800 49700 64800 4 +{ +T 49900 64900 5 10 1 1 0 0 1 +netname=ba_mosi1 +} +N 50600 65200 49700 65200 4 +{ +T 50000 65300 5 10 1 1 0 0 1 +netname=ba_sck1 +} +N 50600 65600 49700 65600 4 +{ +T 50000 65700 5 10 1 1 0 0 1 +netname=cs_pres +} +N 49700 66000 49800 66000 4 +N 49800 66000 49800 65600 4 +C 53500 54700 1 0 1 capacitor.sym +{ +T 53300 55400 5 10 0 0 0 6 1 +device=CAPACITOR +T 52900 55100 5 10 1 1 180 2 1 +refdes=C403 +T 53300 55600 5 10 0 0 0 6 1 +symversion=0.1 +T 53200 55200 5 10 1 1 0 2 1 +value=47pF +T 53500 54700 5 10 0 1 0 0 1 +footprint=0402 +T 53500 54700 5 10 0 1 0 0 1 +loadstatus=noload +T 53500 54700 5 10 0 1 0 0 1 +vendor=digikey +T 53500 54700 5 10 0 1 0 0 1 +vendor_part_number=399-1019-1-ND +} +C 52600 54200 1 0 0 resistor.sym +{ +T 52900 54600 5 10 0 0 0 0 1 +device=RESISTOR +T 52700 54500 5 10 1 1 0 0 1 +refdes=R103 +T 53200 54500 5 10 1 1 0 0 1 +value=0 +T 52600 54200 5 10 0 1 0 0 1 +footprint=0402 +T 52600 54200 5 10 0 1 0 0 1 +loadstatus=smt +T 52600 54200 5 10 0 1 0 0 1 +vendor=digikey +T 52600 54200 5 10 0 1 0 0 1 +vendor_part_number=P0.0JCT-ND +} +C 53800 54800 1 90 0 gnd.sym +N 53500 54300 54800 54300 4 +C 54100 52600 1 90 0 capacitor.sym +{ +T 53400 52800 5 10 0 0 90 0 1 +device=CAPACITOR +T 53700 53300 5 10 1 1 180 0 1 +refdes=C405 +T 53200 52800 5 10 0 0 90 0 1 +symversion=0.1 +T 53400 52800 5 10 1 1 0 0 1 +value=47pF +T 54100 52600 5 10 0 1 0 0 1 +footprint=0402 +T 54100 52600 5 10 0 1 0 0 1 +loadstatus=noload +T 54100 52600 5 10 0 1 0 0 1 +vendor=digikey +T 54100 52600 5 10 0 1 0 0 1 +vendor_part_number=399-1019-1-ND +} +C 53900 53400 1 0 0 resistor.sym +{ +T 54200 53800 5 10 0 0 0 0 1 +device=RESISTOR +T 54000 53700 5 10 1 1 0 0 1 +refdes=R105 +T 54500 53700 5 10 1 1 0 0 1 +value=0 +T 53900 53400 5 10 0 1 0 0 1 +footprint=0402 +T 53900 53400 5 10 0 1 0 0 1 +loadstatus=smt +T 53900 53400 5 10 0 1 0 0 1 +vendor=digikey +T 53900 53400 5 10 0 1 0 0 1 +vendor_part_number=P0.0JCT-ND +} +C 53800 52300 1 0 0 gnd.sym +C 52100 53000 1 270 1 capacitor.sym +{ +T 52800 53200 5 10 0 0 90 2 1 +device=CAPACITOR +T 52500 53700 5 10 1 1 180 6 1 +refdes=C404 +T 53000 53200 5 10 0 0 90 2 1 +symversion=0.1 +T 52800 53200 5 10 1 1 0 6 1 +value=47pF +T 52100 53000 5 10 0 1 0 0 1 +footprint=0402 +T 52100 53000 5 10 0 1 0 0 1 +loadstatus=noload +T 52100 53000 5 10 0 1 0 0 1 +vendor=digikey +T 52100 53000 5 10 0 1 0 0 1 +vendor_part_number=399-1019-1-ND +} +C 52300 53800 1 0 1 resistor.sym +{ +T 52000 54200 5 10 0 0 0 6 1 +device=RESISTOR +T 51700 53600 5 10 1 1 0 6 1 +refdes=R104 +T 52200 53600 5 10 1 1 0 6 1 +value=0 +T 52300 53800 5 10 0 1 0 0 1 +footprint=0402 +T 52300 53800 5 10 0 1 0 0 1 +loadstatus=smt +T 52300 53800 5 10 0 1 0 0 1 +vendor=digikey +T 52300 53800 5 10 0 1 0 0 1 +vendor_part_number=P0.0JCT-ND +} +C 52400 52700 1 0 1 gnd.sym +N 52600 54900 52600 54300 4 +N 52300 53900 54800 53900 4 +N 64300 52700 65600 52700 4 +{ +T 65100 52800 5 10 1 1 0 0 1 +netname=mosi1 +} +N 64300 53500 65600 53500 4 +{ +T 65200 53600 5 10 1 1 0 0 1 +netname=sck1 +} +N 64300 53100 65600 53100 4 +{ +T 65100 53200 5 10 1 1 0 0 1 +netname=miso1 +} +N 54800 63100 53500 63100 4 +{ +T 54300 63200 5 10 1 1 0 6 1 +netname=ba_mosi1 +} +N 54800 63900 53500 63900 4 +{ +T 54200 64000 5 10 1 1 0 6 1 +netname=ba_sck1 +} +N 54800 63500 53500 63500 4 +{ +T 54300 63600 5 10 1 1 0 6 1 +netname=ba_miso1 +} +C 40900 67400 1 90 0 capacitor.sym +{ +T 40200 67600 5 10 0 0 90 0 1 +device=CAPACITOR +T 40500 68200 5 10 1 1 180 0 1 +refdes=C101 +T 40000 67600 5 10 0 0 90 0 1 +symversion=0.1 +T 40100 67500 5 10 1 1 0 0 1 +value=0.1uF +T 40900 67400 5 10 0 0 0 0 1 +footprint=0402 +T 40900 67400 5 10 0 0 0 0 1 +vendor_part_number=399-3027-1-ND +T 40900 67400 5 10 0 0 0 0 1 +vendor=digikey +T 40900 67400 5 10 0 1 0 0 1 +loadstatus=smt +} +C 42600 64500 1 0 0 MMA6556.sym +{ +T 43795 68695 5 10 0 1 0 0 1 +device=IC +T 42895 68695 5 10 1 1 0 0 1 +refdes=U3 +T 42595 63695 5 10 0 1 0 0 1 +footprint=AN3111 +T 42600 64500 5 10 0 0 0 0 1 +vendor=mouser +T 42600 64500 5 10 0 0 0 0 1 +vendor_part_number=841-MMA6555KW +T 42600 64500 5 10 0 1 0 0 1 +loadstatus=smt +T 43800 68700 5 10 1 1 0 0 1 +value=MMA6555 +} +N 42600 66700 42500 66700 4 +N 42500 66700 42500 64600 4 +N 42600 64700 42500 64700 4 +N 42600 65500 42500 65500 4 +N 42600 65900 42500 65900 4 +C 40500 68300 1 0 0 3.3V-plus.sym +N 42600 68300 40700 68300 4 +N 40700 67400 40700 64700 4 +N 40700 64700 42500 64700 4 +C 41400 67000 1 90 0 capacitor.sym +{ +T 40700 67200 5 10 0 0 90 0 1 +device=CAPACITOR +T 41700 67800 5 10 1 1 180 0 1 +refdes=C102 +T 40500 67200 5 10 0 0 90 0 1 +symversion=0.1 +T 41300 67100 5 10 1 1 0 0 1 +value=1uF +T 41400 67000 5 10 0 0 0 0 1 +vendor_part_number=490-1320-1-ND +T 41400 67000 5 10 0 0 0 0 1 +footprint=0402 +T 41400 67000 5 10 0 0 0 0 1 +vendor=digikey +T 41400 67000 5 10 0 1 0 0 1 +loadstatus=smt +} +C 42100 66600 1 90 0 capacitor.sym +{ +T 41400 66800 5 10 0 0 90 0 1 +device=CAPACITOR +T 42400 67400 5 10 1 1 180 0 1 +refdes=C103 +T 41200 66800 5 10 0 0 90 0 1 +symversion=0.1 +T 42000 66700 5 10 1 1 0 0 1 +value=1uF +T 42100 66600 5 10 0 0 0 0 1 +vendor_part_number=490-1320-1-ND +T 42100 66600 5 10 0 0 0 0 1 +footprint=0402 +T 42100 66600 5 10 0 0 0 0 1 +vendor=digikey +T 42100 66600 5 10 0 1 0 0 1 +loadstatus=smt +} +N 42600 67900 41200 67900 4 +N 41900 67500 42600 67500 4 +N 41900 66600 41900 64700 4 +N 41200 67000 41200 64700 4 +N 42600 66300 42500 66300 4 +N 46000 67100 44900 67100 4 +{ +T 45550 67200 5 10 1 1 0 0 1 +netname=miso1 +} +N 46000 67500 44900 67500 4 +{ +T 45550 67600 5 10 1 1 0 0 1 +netname=mosi1 +} +N 46000 67900 44900 67900 4 +{ +T 45650 68000 5 10 1 1 0 0 1 +netname=sck1 +} +N 46000 68300 44900 68300 4 +{ +T 45300 68400 5 10 1 1 0 0 1 +netname=cs_accel +} +C 42400 64300 1 0 0 gnd.sym +N 42600 65100 42500 65100 4 +N 64300 63500 65600 63500 4 +{ +T 64900 63600 5 10 1 1 0 0 1 +netname=cs_accel +} +T -72100 -78700 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -72100 -78700 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -72100 -78700 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -72100 -78700 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -29500 -72800 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -29500 -72800 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +T -29500 -72800 8 10 0 1 0 0 1 +vendor_part_number=MMA7260QT-ND +T -29500 -72800 8 10 0 1 0 0 1 +vendor_part_number=MCP9700-E/TO-ND +C 43500 63200 1 0 0 3.3V-plus.sym +N 44900 62000 45100 62000 4 +N 45100 62000 45100 63200 4 +N 44900 62400 45100 62400 4 +C 42500 61000 1 90 0 capacitor.sym +{ +T 41800 61200 5 10 0 0 90 0 1 +device=CAPACITOR +T 42200 61800 5 10 1 1 180 0 1 +refdes=C20 +T 41600 61200 5 10 0 0 90 0 1 +symversion=0.1 +T 41600 61100 5 10 1 1 0 0 1 +value=0.22uF +T 42500 61000 5 10 0 1 0 0 1 +footprint=0402 +T 42500 61000 5 10 0 1 0 0 1 +loadstatus=smt +T 42500 61000 5 10 0 1 0 0 1 +vendor=digikey +T 42500 61000 5 10 0 1 0 0 1 +vendor_part_number=587-1228-1-ND +} +C 45800 62000 1 90 0 capacitor.sym +{ +T 45100 62200 5 10 0 0 90 0 1 +device=CAPACITOR +T 46000 62800 5 10 1 1 180 0 1 +refdes=C22 +T 44900 62200 5 10 0 0 90 0 1 +symversion=0.1 +T 45800 62100 5 10 1 1 0 0 1 +value=0.1uF +T 45800 62000 5 10 0 1 0 0 1 +footprint=0402 +T 45800 62000 5 10 0 1 0 0 1 +loadstatus=smt +T 45800 62000 5 10 0 1 0 0 1 +vendor=digikey +T 45800 62000 5 10 0 1 0 0 1 +vendor_part_number=399-3027-1-ND +} +C 42500 59500 1 90 0 capacitor.sym +{ +T 41800 59700 5 10 0 0 90 0 1 +device=CAPACITOR +T 42200 60300 5 10 1 1 180 0 1 +refdes=C21 +T 41600 59700 5 10 0 0 90 0 1 +symversion=0.1 +T 41700 59600 5 10 1 1 0 0 1 +value=4.7uF +T 42500 59500 5 10 0 1 0 0 1 +footprint=0402 +T 42500 59500 5 10 0 1 0 0 1 +loadstatus=smt +T 42500 59500 5 10 0 1 0 0 1 +vendor=digikey +T 42500 59500 5 10 0 1 0 0 1 +vendor_part_number=445-5947-1-ND +} +C 42500 59500 1 0 0 HMC5883L.sym +{ +T 43255 62700 5 10 0 1 0 0 1 +device=IC +T 42805 62945 5 10 1 1 0 0 1 +refdes=U9 +T 42500 59500 5 10 0 0 0 0 1 +footprint=LPCC16 +T 43700 62950 5 10 1 1 0 0 1 +value=HMC5883L +T 42500 59500 5 10 0 1 0 0 1 +loadstatus=smt +T 42500 59500 5 10 0 1 0 0 1 +vendor=digikey +T 42500 59500 5 10 0 1 0 0 1 +vendor_part_number=342-1082-1-ND +} +N 42500 62000 42300 62000 4 +N 42300 62000 42300 61900 4 +N 42300 61000 42300 60800 4 +N 42300 60800 42500 60800 4 +N 42300 60400 42500 60400 4 +C 42200 59200 1 0 0 gnd.sym +C 43200 59200 1 0 0 gnd.sym +C 43900 59200 1 0 0 gnd.sym +C 45500 61700 1 0 0 gnd.sym +N 44900 61200 46500 61200 4 +{ +T 45400 61300 5 10 1 1 0 0 1 +netname=sda1 +} +N 44900 60800 47300 60800 4 +{ +T 45500 60900 5 10 1 1 0 0 1 +netname=scl1 +} +N 42300 63200 45100 63200 4 +N 42500 62400 42300 62400 4 +N 42300 62400 42300 63200 4 +N 45600 62900 45100 62900 4 +N 44900 60400 45800 60400 4 +{ +T 45200 60500 5 10 1 1 0 0 1 +netname=mag_int +} +C 46600 61200 1 90 0 resistor.sym +{ +T 46200 61500 5 10 0 0 90 0 1 +device=RESISTOR +T 46700 61700 5 10 1 1 0 0 1 +refdes=R900 +T 46700 61400 5 10 1 1 0 0 1 +value=1.8k +T 46600 61200 5 10 0 1 0 0 1 +footprint=0402 +T 46600 61200 5 10 0 1 0 0 1 +loadstatus=smt +T 46600 61200 5 10 0 1 0 0 1 +vendor=digikey +T 46600 61200 5 10 0 1 0 0 1 +vendor_part_number=P1.80KLCT-ND +} +C 47400 60800 1 90 0 resistor.sym +{ +T 47000 61100 5 10 0 0 90 0 1 +device=RESISTOR +T 47500 61300 5 10 1 1 0 0 1 +refdes=R901 +T 47500 61000 5 10 1 1 0 0 1 +value=1.8k +T 47400 60800 5 10 0 1 0 0 1 +footprint=0402 +T 47400 60800 5 10 0 1 0 0 1 +loadstatus=smt +T 47400 60800 5 10 0 1 0 0 1 +vendor=digikey +T 47400 60800 5 10 0 1 0 0 1 +vendor_part_number=P1.80KLCT-ND +} +C 46300 62100 1 0 0 3.3V-plus.sym +C 47100 61700 1 0 0 3.3V-plus.sym +N 64300 66700 65600 66700 4 +{ +T 65000 66800 5 10 1 1 0 0 1 +netname=mag_int +} +N 54800 55900 53500 55900 4 +{ +T 53900 56000 5 10 1 1 0 6 1 +netname=sda1 +} +N 54800 56300 53500 56300 4 +{ +T 53850 56400 5 10 1 1 0 6 1 +netname=scl1 +} +C 52900 61400 1 0 1 resistor.sym +{ +T 52600 61800 5 10 0 0 0 6 1 +device=RESISTOR +T 52400 61700 5 10 1 1 0 6 1 +refdes=R54 +T 52800 61700 5 10 1 1 0 6 1 +value=22 +T 52900 61400 5 10 0 1 0 0 1 +footprint=0402 +T 52900 61400 5 10 0 1 0 0 1 +loadstatus=smt +T 52900 61400 5 10 0 1 0 0 1 +vendor=digikey +T 52900 61400 5 10 0 1 0 0 1 +vendor_part_number=P22.0LCT-ND +} +C 52900 61000 1 0 1 resistor.sym +{ +T 52600 61400 5 10 0 0 0 6 1 +device=RESISTOR +T 52400 60800 5 10 1 1 0 6 1 +refdes=R55 +T 52800 60800 5 10 1 1 0 6 1 +value=22 +T 52900 61000 5 10 0 1 0 0 1 +footprint=0402 +T 52900 61000 5 10 0 1 0 0 1 +loadstatus=smt +T 52900 61000 5 10 0 1 0 0 1 +vendor=digikey +T 52900 61000 5 10 0 1 0 0 1 +vendor_part_number=P22.0LCT-ND +} +N 52000 61500 50600 61500 4 +N 50600 61100 52000 61100 4 +C 72800 42200 1 90 0 resistor.sym +{ +T 72400 42500 5 10 0 0 90 0 1 +device=RESISTOR +T 72800 42195 5 10 0 1 90 0 1 +footprint=0402 +T 72800 42200 5 10 0 0 0 0 1 +vendor=digikey +T 72800 42200 5 10 0 1 0 0 1 +loadstatus=smt +T 72500 42900 5 10 1 1 180 0 1 +refdes=R39 +T 72100 42400 5 10 1 1 0 0 1 +value=9.09k +T 72800 42200 5 10 0 1 0 0 1 +vendor_part_number=P9.09KLCT-ND +} +C 72800 43100 1 90 0 resistor.sym +{ +T 72400 43400 5 10 0 0 90 0 1 +device=RESISTOR +T 72800 43095 5 10 0 1 90 0 1 +footprint=0402 +T 72800 43100 5 10 0 0 0 0 1 +vendor=digikey +T 72800 43100 5 10 0 1 0 0 1 +loadstatus=smt +T 72500 43800 5 10 1 1 180 0 1 +refdes=R38 +T 72200 43300 5 10 1 1 0 0 1 +value=10k +T 72800 43100 5 10 0 1 0 0 1 +vendor_part_number=P10.0KLCT-ND +} +C 67600 41600 1 90 0 resistor.sym +{ +T 67200 41900 5 10 0 0 90 0 1 +device=RESISTOR +T 67600 41595 5 10 0 1 90 0 1 +footprint=0402 +T 67600 41600 5 10 0 0 0 0 1 +vendor=digikey +T 67600 41600 5 10 0 1 0 0 1 +loadstatus=smt +T 67300 42300 5 10 1 1 180 0 1 +refdes=R37 +T 66900 41800 5 10 1 1 0 0 1 +value=8.06k +T 67600 41600 5 10 0 1 0 0 1 +vendor_part_number=P8.06KLCT-ND +} +C 67600 42500 1 90 0 resistor.sym +{ +T 67200 42800 5 10 0 0 90 0 1 +device=RESISTOR +T 67600 42495 5 10 0 1 90 0 1 +footprint=0402 +T 67600 42500 5 10 0 0 0 0 1 +vendor=digikey +T 67600 42500 5 10 0 1 0 0 1 +loadstatus=smt +T 67300 43200 5 10 1 1 180 0 1 +refdes=R36 +T 67000 42700 5 10 1 1 0 0 1 +value=10k +T 67600 42500 5 10 0 1 0 0 1 +vendor_part_number=P10.0KLCT-ND +} +C 72600 41900 1 0 0 gnd.sym +N 72700 43100 73800 43100 4 +{ +T 73100 43200 5 10 1 1 0 0 1 +netname=cmp_rail +} +N 67500 43400 67500 44000 4 +N 67500 42500 68700 42500 4 +{ +T 67800 42600 5 10 1 1 0 0 1 +netname=cmp_ldo_in +} +C 66800 43000 1 90 0 capacitor.sym +{ +T 66100 43200 5 10 0 0 90 0 1 +device=CAPACITOR +T 65900 43200 5 10 0 0 90 0 1 +symversion=0.1 +T 66800 43000 5 10 0 0 90 0 1 +footprint=1206 +T 66800 43000 5 10 0 0 90 0 1 +vendor_part_number=587-1780-1-ND +T 66800 43000 5 10 0 0 0 0 1 +vendor=digikey +T 66800 43000 5 10 0 1 0 0 1 +loadstatus=smt +T 66550 43750 5 10 1 1 180 0 1 +refdes=C39 +T 66500 43300 5 10 1 1 180 0 1 +value=47uF +} +C 65000 43800 1 0 0 diode.sym +{ +T 65400 44400 5 10 0 0 0 0 1 +device=DIODE +T 65300 44300 5 10 1 1 0 0 1 +refdes=D3 +T 65000 43800 5 10 0 0 0 0 1 +vendor=digikey +T 65000 43800 5 10 0 0 0 0 1 +vendor_part_number=DFLS130LDICT-ND +T 65000 43800 5 10 0 0 0 0 1 +footprint=powerdi123 +T 65000 43800 5 10 0 0 0 0 1 +loadstatus=smt +T 65000 43500 5 10 1 1 0 0 1 +value=DFLS130L +} +N 65900 44000 68000 44000 4 +{ +T 66700 44100 5 10 1 1 0 0 1 +netname=v_ldo_in +} +N 66600 43900 66600 44000 4 +N 66600 43000 66600 41600 4 +C 49200 50600 1 0 0 3.3V-plus.sym +N 47800 50000 48900 50000 4 +{ +T 47800 50100 5 10 1 1 0 0 1 +netname=cmp_rail +} +N 47800 50400 48900 50400 4 +{ +T 47800 50500 5 10 1 1 0 0 1 +netname=cmp_ldo_in +} +C 48900 49800 1 0 0 opamp-dual.sym +{ +T 50000 51100 5 10 0 0 0 0 1 +device=IC +T 50000 51700 5 10 0 0 0 0 1 +symversion=0.1 +T 48900 49800 5 10 0 1 0 0 1 +slot=2 +T 48900 49800 5 10 0 1 0 0 1 +loadstatus=smt +T 48900 49800 5 10 0 1 0 0 1 +vendor=digikey +T 48900 49800 5 10 0 1 0 0 1 +vendor_part_number=497-11133-1-ND +T 48900 49800 5 10 0 1 0 0 1 +footprint=8ufson2x2 +T 49700 50500 5 10 1 1 0 0 1 +refdes=U13 +T 49700 49800 5 10 1 1 0 0 1 +value=LM293 +} +C 49300 49500 1 0 0 gnd.sym +N 49900 50200 50400 50200 4 +N 50400 50200 50400 49000 4 +C 42900 50600 1 0 0 3.3V-plus.sym +N 41500 50000 42600 50000 4 +{ +T 41500 50100 5 10 1 1 0 0 1 +netname=cmp_rail +} +N 41500 50400 42600 50400 4 +{ +T 41500 50500 5 10 1 1 0 0 1 +netname=cmp_ldo_in +} +C 42600 49800 1 0 0 opamp-dual.sym +{ +T 43700 51100 5 10 0 0 0 0 1 +device=IC +T 43700 51700 5 10 0 0 0 0 1 +symversion=0.1 +T 42600 49800 5 10 0 1 0 0 1 +slot=1 +T 42600 49800 5 10 0 1 0 0 1 +loadstatus=smt +T 42600 49800 5 10 0 1 0 0 1 +vendor=digikey +T 42600 49800 5 10 0 1 0 0 1 +vendor_part_number=497-11133-1-ND +T 42600 49800 5 10 0 1 0 0 1 +footprint=8ufson2x2 +T 43400 50500 5 10 1 1 0 0 1 +refdes=U13 +T 43400 49800 5 10 1 1 0 0 1 +value=LM293 +} +C 43000 49500 1 0 0 gnd.sym +N 43600 50200 44100 50200 4 +N 44100 50200 44100 49000 4 +C 49200 47200 1 0 0 3.3V-plus.sym +N 47800 46600 48900 46600 4 +{ +T 47800 46700 5 10 1 1 0 0 1 +netname=cmp_rail +} +N 47800 47000 48900 47000 4 +{ +T 47800 47100 5 10 1 1 0 0 1 +netname=cmp_ldo_in +} +C 48900 46400 1 0 0 opamp-dual.sym +{ +T 50000 47700 5 10 0 0 0 0 1 +device=IC +T 50000 48300 5 10 0 0 0 0 1 +symversion=0.1 +T 48900 46400 5 10 0 1 0 0 1 +slot=2 +T 48900 46400 5 10 0 1 0 0 1 +loadstatus=smt +T 48900 46400 5 10 0 1 0 0 1 +vendor=digikey +T 48900 46400 5 10 0 1 0 0 1 +vendor_part_number=497-11133-1-ND +T 48900 46400 5 10 0 1 0 0 1 +footprint=8ufson2x2 +T 49700 47100 5 10 1 1 0 0 1 +refdes=U14 +T 49700 46400 5 10 1 1 0 0 1 +value=LM293 +} +C 49300 46100 1 0 0 gnd.sym +N 49900 46800 50400 46800 4 +N 50400 46800 50400 45600 4 +C 42900 47200 1 0 0 3.3V-plus.sym +N 41500 46600 42600 46600 4 +{ +T 41500 46700 5 10 1 1 0 0 1 +netname=cmp_rail +} +N 41500 47000 42600 47000 4 +{ +T 41500 47100 5 10 1 1 0 0 1 +netname=cmp_ldo_in +} +C 42600 46400 1 0 0 opamp-dual.sym +{ +T 43700 47700 5 10 0 0 0 0 1 +device=IC +T 43700 48300 5 10 0 0 0 0 1 +symversion=0.1 +T 42600 46400 5 10 0 1 0 0 1 +slot=1 +T 42600 46400 5 10 0 1 0 0 1 +loadstatus=smt +T 42600 46400 5 10 0 1 0 0 1 +vendor=digikey +T 42600 46400 5 10 0 1 0 0 1 +vendor_part_number=497-11133-1-ND +T 42600 46400 5 10 0 1 0 0 1 +footprint=8ufson2x2 +T 43400 47100 5 10 1 1 0 0 1 +refdes=U14 +T 43400 46400 5 10 1 1 0 0 1 +value=LM293 +} +C 43000 46100 1 0 0 gnd.sym +N 43600 46800 44100 46800 4 +N 44100 46800 44100 45600 4 +C 42900 43800 1 0 0 3.3V-plus.sym +N 41500 43200 42600 43200 4 +{ +T 41500 43300 5 10 1 1 0 0 1 +netname=cmp_rail +} +N 41500 43600 42600 43600 4 +{ +T 41500 43700 5 10 1 1 0 0 1 +netname=cmp_ldo_in +} +C 42600 43000 1 0 0 opamp-dual.sym +{ +T 43700 44300 5 10 0 0 0 0 1 +device=IC +T 43700 44900 5 10 0 0 0 0 1 +symversion=0.1 +T 42600 43000 5 10 0 1 0 0 1 +slot=1 +T 42600 43000 5 10 0 1 0 0 1 +loadstatus=smt +T 42600 43000 5 10 0 1 0 0 1 +vendor=digikey +T 42600 43000 5 10 0 1 0 0 1 +vendor_part_number=497-11133-1-ND +T 42600 43000 5 10 0 1 0 0 1 +footprint=8ufson2x2 +T 43400 43700 5 10 1 1 0 0 1 +refdes=U15 +T 43400 43000 5 10 1 1 0 0 1 +value=LM293 +} +C 43000 42700 1 0 0 gnd.sym +N 43600 43400 44100 43400 4 +N 44100 43400 44100 42200 4 +C 49200 43800 1 0 0 3.3V-plus.sym +N 47800 43200 48900 43200 4 +{ +T 47800 43300 5 10 1 1 0 0 1 +netname=cmp_rail +} +N 47800 43600 48900 43600 4 +{ +T 47800 43700 5 10 1 1 0 0 1 +netname=cmp_ldo_in +} +C 48900 43000 1 0 0 opamp-dual.sym +{ +T 50000 44300 5 10 0 0 0 0 1 +device=IC +T 50000 44900 5 10 0 0 0 0 1 +symversion=0.1 +T 48900 43000 5 10 0 1 0 0 1 +slot=2 +T 48900 43000 5 10 0 1 0 0 1 +loadstatus=smt +T 48900 43000 5 10 0 1 0 0 1 +vendor=digikey +T 48900 43000 5 10 0 1 0 0 1 +vendor_part_number=497-11133-1-ND +T 48900 43000 5 10 0 1 0 0 1 +footprint=8ufson2x2 +T 49700 43700 5 10 1 1 0 0 1 +refdes=U15 +T 49700 43000 5 10 1 1 0 0 1 +value=LM293 +} +C 49300 42700 1 0 0 gnd.sym +N 49900 43400 50400 43400 4 +N 50400 43400 50400 42200 4 +C 42900 45500 1 0 0 resistor.sym +{ +T 43200 45900 5 10 0 0 0 0 1 +device=RESISTOR +T 43300 45900 5 10 1 1 180 0 1 +refdes=R10 +T 43700 45900 5 10 1 1 180 0 1 +value=549 +T 42900 45500 5 10 0 0 90 0 1 +footprint=0402 +T 42900 45500 5 10 0 0 90 0 1 +vendor_part_number=P549LCT-ND +T 42900 45500 5 10 0 0 0 0 1 +vendor=digikey +T 42900 45500 5 10 0 1 0 0 1 +loadstatus=smt +} +C 49200 42100 1 0 0 resistor.sym +{ +T 49500 42500 5 10 0 0 0 0 1 +device=RESISTOR +T 49600 42500 5 10 1 1 180 0 1 +refdes=R11 +T 50000 42500 5 10 1 1 180 0 1 +value=549 +T 49200 42100 5 10 0 0 90 0 1 +footprint=0402 +T 49200 42100 5 10 0 0 90 0 1 +vendor_part_number=P549LCT-ND +T 49200 42100 5 10 0 0 0 0 1 +vendor=digikey +T 49200 42100 5 10 0 1 0 0 1 +loadstatus=smt +} diff --git a/gafrc b/gafrc new file mode 100644 index 0000000..9e10ee9 --- /dev/null +++ b/gafrc @@ -0,0 +1,3 @@ +; empty the library path and populate it with only our own symbols +(reset-component-library) +(load "../altusmetrum/gafrc") diff --git a/project b/project new file mode 100644 index 0000000..f2624a7 --- /dev/null +++ b/project @@ -0,0 +1,12 @@ +# List all the schematics to be netlisted and laid out on the pc board +schematics easymega.sch + +# for an output-name of foo, gsch2pcb generates files foo.net, foo.pcb, +# and foo.new.pcb. if there is no output name specified, the file names +# are derived from the first listed schematic... +output-name easymega + +elements-dir ../altusmetrum/packages + +# stick to newlib elements, don't use the older/odder m4 stuff +skip-m4