+C 41100 67300 1 90 0 capacitor.sym
+{
+T 40400 67500 5 10 0 0 90 0 1
+device=CAPACITOR
+T 40200 67500 5 10 0 0 90 0 1
+symversion=0.1
+T 41100 67300 5 10 0 0 0 0 1
+footprint=0402
+T 40700 68100 5 10 1 1 180 0 1
+refdes=C101
+T 40300 67400 5 10 1 1 0 0 1
+value=0.1uF
+}
+N 42300 65400 42300 64500 4
+N 42400 64600 42300 64600 4
+N 42400 65400 42300 65400 4
+C 40700 68200 1 0 0 3.3V-plus.sym
+N 42400 68200 40900 68200 4
+N 40900 67300 40900 64600 4
+N 40900 64600 42300 64600 4
+C 41600 66900 1 90 0 capacitor.sym
+{
+T 40900 67100 5 10 0 0 90 0 1
+device=CAPACITOR
+T 40700 67100 5 10 0 0 90 0 1
+symversion=0.1
+T 41600 66900 5 10 0 0 0 0 1
+footprint=0402
+T 41900 67700 5 10 1 1 180 0 1
+refdes=C102
+T 41500 67000 5 10 1 1 0 0 1
+value=1uF
+}
+N 42400 67800 41400 67800 4
+N 41400 66900 41400 64600 4
+N 45800 67000 44700 67000 4
+{
+T 45750 67100 5 10 1 1 0 6 1
+netname=miso1
+}
+N 45800 67400 44700 67400 4
+{
+T 45750 67500 5 10 1 1 0 6 1
+netname=mosi1
+}
+N 45800 67800 44700 67800 4
+{
+T 45750 67900 5 10 1 1 0 6 1
+netname=sck1
+}
+N 45800 68200 44700 68200 4
+{
+T 45700 68300 5 10 1 1 0 6 1
+netname=cs_accel
+}
+C 42200 64200 1 0 0 gnd.sym
+N 42400 65000 42300 65000 4
+C 44700 64500 1 0 0 nc-right.sym
+{
+T 44800 65000 5 10 0 0 0 0 1
+value=NoConnection
+T 44800 65200 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 44700 64900 1 0 0 nc-right.sym
+{
+T 44800 65400 5 10 0 0 0 0 1
+value=NoConnection
+T 44800 65600 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 44700 65300 1 0 0 nc-right.sym
+{
+T 44800 65800 5 10 0 0 0 0 1
+value=NoConnection
+T 44800 66000 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 42400 64400 1 0 0 ADXL375.sym
+{
+T 42395 63595 5 10 0 1 0 0 1
+footprint=lga14
+T 43595 68595 5 10 1 1 0 0 1
+device=ADXL375
+T 42695 68595 5 10 1 1 0 0 1
+refdes=U3
+}
+N 45800 66200 44700 66200 4
+{
+T 45750 66300 5 10 1 1 0 6 1
+netname=accel_int2
+}
+N 45800 66600 44700 66600 4
+{
+T 45750 66700 5 10 1 1 0 6 1
+netname=accel_int1
+}
+N 41400 67800 41400 68200 4
+N 46000 70300 47100 70300 4
+{
+T 46700 70400 5 10 1 1 0 0 1
+netname=sck1
+}
+N 46000 69900 47100 69900 4
+{
+T 46600 70000 5 10 1 1 0 0 1
+netname=mosi1
+}
+C 41000 72700 1 0 0 3.3V-plus.sym
+N 41200 72700 43300 72700 4
+C 41400 71800 1 90 0 capacitor.sym
+{
+T 40700 72000 5 10 0 0 90 0 1
+device=CAPACITOR
+T 40500 72000 5 10 0 0 90 0 1
+symversion=0.1
+T 41400 71800 5 10 0 1 0 0 1
+footprint=0402
+T 41100 72500 5 10 1 1 180 0 1
+refdes=C301
+T 40700 72000 5 10 1 1 0 0 1
+value=0.1uF
+}
+C 42000 71100 1 90 0 capacitor.sym
+{
+T 41300 71300 5 10 0 0 90 0 1
+device=CAPACITOR
+T 41100 71300 5 10 0 0 90 0 1
+symversion=0.1
+T 42000 71100 5 10 0 1 0 0 1
+footprint=0402
+T 41700 71800 5 10 1 1 180 0 1
+refdes=C303
+T 41300 71300 5 10 1 1 0 0 1
+value=10nF
+}
+C 42600 70400 1 90 0 capacitor.sym
+{
+T 41900 70600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 41700 70600 5 10 0 0 90 0 1
+symversion=0.1
+T 42600 70400 5 10 0 1 0 0 1
+footprint=0402
+T 42300 71100 5 10 1 1 180 0 1
+refdes=C302
+T 41900 70600 5 10 1 1 0 0 1
+value=0.1uF
+}
+N 41200 69900 43300 69900 4
+N 41200 69900 41200 71800 4
+C 42500 69600 1 0 0 gnd.sym
+N 46000 71900 47100 71900 4
+{
+T 46500 72000 5 10 1 1 0 0 1
+netname=gyro_int
+}
+N 41800 71100 41800 69900 4
+N 42400 71500 42400 71300 4
+N 42400 70400 42400 69900 4
+N 46000 71100 47100 71100 4
+{
+T 46500 71200 5 10 1 1 0 0 1
+netname=cs_gyro
+}
+N 46000 70700 47100 70700 4
+{
+T 46600 70800 5 10 1 1 0 0 1
+netname=miso1
+}
+C 42800 71000 1 0 0 nc-left.sym
+{
+T 42800 71400 5 10 0 0 0 0 1
+value=NoConnection
+T 42800 71800 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 42800 70600 1 0 0 nc-left.sym
+{
+T 42800 71000 5 10 0 0 0 0 1
+value=NoConnection
+T 42800 71400 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 43300 69700 1 0 0 MPU9250.sym
+{
+T 44595 71895 5 10 0 1 0 0 1
+device=IC
+T 43300 69700 5 10 0 1 0 0 1
+footprint=ufqfpn24
+T 43595 73095 5 10 1 1 0 0 1
+refdes=U12
+T 44795 73095 5 10 1 1 0 0 1
+value=MPU-9250
+}
+N 43300 70300 43100 70300 4
+N 43100 70300 43100 69900 4
+N 43300 71500 42400 71500 4
+N 41800 72300 43300 72300 4
+N 41800 72000 41800 72700 4
+N 43300 71900 43100 71900 4
+N 43100 71900 43100 72300 4
+C 47600 72000 1 0 0 gnd.sym
+N 46000 72300 47700 72300 4
+T 77500 40800 9 10 1 0 0 0 2
+ Copyright 2018 by Bdale Garbee
+Licensed under the TAPR Open Hardware License, http://www.tapr.org/OHL
+C 64300 65800 1 0 0 nc-right.sym
+{
+T 64400 66300 5 10 0 0 0 0 1
+value=NoConnection
+T 64400 66500 5 10 0 0 0 0 1
+device=DRC_Directive
+}
projects / hw / easymega / commitdiff