X-Git-Url: https://git.gag.com/?p=fw%2Fstlink;a=blobdiff_plain;f=src%2Fstlink-common.h;fp=src%2Fstlink-common.h;h=6fcb2194e10cc35fc9b63fcf1718983376ed4260;hp=155c6c003083e5e3fe45c4b253ccb67d3370e222;hb=7d9f4129abd300c9bb0cb3d9b86a5856cb2b3fb7;hpb=5cd3ad39badef8f04b3380dfe2dfc82fc8b1b4ca

diff --git a/src/stlink-common.h b/src/stlink-common.h
index 155c6c0..6fcb219 100644
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -81,10 +81,18 @@ extern "C" {
 #define CM3_REG_FP_COMP0 0xE0002008
 
 /* cortex core ids */
+    // TODO clean this up...
 #define STM32VL_CORE_ID 0x1ba01477
 #define STM32L_CORE_ID 0x2ba01477
 #define STM32F4_CORE_ID 0x2ba01477
-    
+#define CORE_M3_R1 0x1BA00477
+#define CORE_M3_R2 0x4BA00477
+#define CORE_M4_R0 0x2BA01477
+
+/*
+ * Chip IDs are explained in the appropriate programming manual for the
+ * DBGMCU_IDCODE register (0xE0042000)
+ */
 // stm32 chipids, only lower 12 bits..
 #define STM32_CHIPID_F1_MEDIUM 0x410
 #define STM32_CHIPID_F2 0x411
@@ -101,17 +109,6 @@ extern "C" {
 #define STM32_FLASH_BASE 0x08000000
 #define STM32_SRAM_BASE 0x20000000
 
-/*
- * Chip IDs are explained in the appropriate programming manual for the
- * DBGMCU_IDCODE register (0xE0042000)
- */
-#define CORE_M3_R1 0x1BA00477
-#define CORE_M3_R2 0x4BA00477
-#define CORE_M4_R0 0x2BA01477
-
-/* using chip id for F4 ident, since core id is same as F1 */
-#define STM32F4_CHIP_ID 0x413
-
 /* Cortex™-M3 Technical Reference Manual */
 /* Debug Halting Control and Status Register */
 #define DHCSR 0xe000edf0