CoreIF for F2/F4 is not different, use CPUID to distinguish. F4 errata seems to give...

[fw/stlink] / src / stlink-common.h

diff --git a/src/stlink-common.h b/src/stlink-common.h
index 5534b6f32619890d1655bf386a114e0e15c55091..155c6c003083e5e3fe45c4b253ccb67d3370e222 100644 (file)
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -70,6 +70,10 @@ extern "C" {
     // TODO - possible poor names...
 #define STLINK_SWD_ENTER 0x30
 #define STLINK_SWD_READCOREID 0x32  // TBD
+#define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
+#define STLINK_JTAG_READDEBUG_32BIT 0x36
+#define STLINK_JTAG_DRIVE_NRST 0x3c
+#define STLINK_JTAG_DRIVE_NRST 0x3c
 
 // cortex m3 technical reference manual
 #define CM3_REG_CPUID 0xE000ED00
@@ -97,6 +101,22 @@ extern "C" {
 #define STM32_FLASH_BASE 0x08000000
 #define STM32_SRAM_BASE 0x20000000
 
+/*
+ * Chip IDs are explained in the appropriate programming manual for the
+ * DBGMCU_IDCODE register (0xE0042000)
+ */
+#define CORE_M3_R1 0x1BA00477
+#define CORE_M3_R2 0x4BA00477
+#define CORE_M4_R0 0x2BA01477
+
+/* using chip id for F4 ident, since core id is same as F1 */
+#define STM32F4_CHIP_ID 0x413
+
+/* Cortex™-M3 Technical Reference Manual */
+/* Debug Halting Control and Status Register */
+#define DHCSR 0xe000edf0
+#define DBGKEY 0xa05f0000
+
 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
 #define C_BUF_LEN 32
 
@@ -143,8 +163,8 @@ extern "C" {
         {
             .chip_id = 0x413,
                     .description = "F4 device",
-                    .flash_size_reg = 0x1FFF7A10,
-                    .flash_pagesize = 0x20000,
+                    .flash_size_reg = 0x1FFF7A10,  //RM0090 error same as unique ID
+                    .flash_pagesize = 0x4000,
                     .sram_size = 0x30000,
                     .bootrom_base = 0x1fff0000,
                     .bootrom_size = 0x7800
@@ -256,10 +276,13 @@ extern "C" {
         void (*exit_dfu_mode) (stlink_t * stl);
         void (*core_id) (stlink_t * stl);
         void (*reset) (stlink_t * stl);
+        void (*jtag_reset) (stlink_t * stl, int value);
         void (*run) (stlink_t * stl);
         void (*status) (stlink_t * stl);
         void (*version) (stlink_t *sl);
+        uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
         void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
+        void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
         void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
         void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
         void (*read_all_regs) (stlink_t *sl, reg * regp);
@@ -283,10 +306,15 @@ extern "C" {
         // transport layer verboseness: 0 for no debug info, 10 for lots
         int verbose;
         uint32_t core_id;
+        uint32_t chip_id;
         int core_stat;
 
 #define STM32_FLASH_PGSZ 1024
 #define STM32L_FLASH_PGSZ 256
+
+#define STM32F4_FLASH_PGSZ 16384
+#define STM32F4_FLASH_SIZE (128 * 1024 * 8)
+
         stm32_addr_t flash_base;
         size_t flash_size;
         size_t flash_pgsz;
@@ -314,10 +342,13 @@ extern "C" {
     void stlink_close(stlink_t *sl);
     uint32_t stlink_core_id(stlink_t *sl);
     void stlink_reset(stlink_t *sl);
+    void stlink_jtag_reset(stlink_t *sl, int value);
     void stlink_run(stlink_t *sl);
     void stlink_status(stlink_t *sl);
     void stlink_version(stlink_t *sl);
+    uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
     void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
+    void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
     void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
     void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
     void stlink_read_all_regs(stlink_t *sl, reg *regp);
@@ -332,14 +363,17 @@ extern "C" {
     int stlink_erase_flash_mass(stlink_t* sl);
     int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
     int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
+    int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
+    int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length);
     
     // PUBLIC
-    uint16_t stlink_chip_id(stlink_t *sl);
+    uint32_t stlink_chip_id(stlink_t *sl);
     void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
 
     // privates, publics, the rest....
     // TODO sort what is private, and what is not
-    int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t page);
+    int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
+    uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
     uint16_t read_uint16(const unsigned char *c, const int pt);
     void stlink_core_stat(stlink_t *sl);
     void stlink_print_data(stlink_t *sl);