}
static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
- stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
- return read_uint32(sl->q_buf, 0) & 0xff;
+ return stlink_read_debug32(sl, FLASH_WRPR) & 0xff;
}
static inline uint32_t read_flash_wrpr(stlink_t *sl) {
- stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
- return read_uint32(sl->q_buf, 0);
+ return stlink_read_debug32(sl, FLASH_WRPR);
}
static inline uint32_t read_flash_obr(stlink_t *sl) {
- stlink_read_mem32(sl, FLASH_OBR, sizeof (uint32_t));
- return read_uint32(sl->q_buf, 0);
+ return stlink_read_debug32(sl, FLASH_OBR);
}
static inline uint32_t read_flash_cr(stlink_t *sl) {
+ uint32_t res;
if(sl->chip_id==STM32F4_CHIP_ID)
- stlink_read_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+ res = stlink_read_debug32(sl, FLASH_F4_CR);
else
- stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ res = stlink_read_debug32(sl, FLASH_CR);
#if DEBUG_FLASH
- fprintf(stdout, "CR:0x%x\n", *(uint32_t*) sl->q_buf);
+ fprintf(stdout, "CR:0x%x\n", res);
#endif
- return read_uint32(sl->q_buf, 0);
+ return res;
}
static inline unsigned int is_flash_locked(stlink_t *sl) {
the FPEC block until next reset.
*/
if(sl->chip_id==STM32F4_CHIP_ID) {
- write_uint32(sl->q_buf, FLASH_KEY1);
- stlink_write_mem32(sl, FLASH_F4_KEYR, sizeof (uint32_t));
- write_uint32(sl->q_buf, FLASH_KEY2);
- stlink_write_mem32(sl, FLASH_F4_KEYR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
+ stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
}
else {
- write_uint32(sl->q_buf, FLASH_KEY1);
- stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
- write_uint32(sl->q_buf, FLASH_KEY2);
- stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
+ stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
}
}
static void lock_flash(stlink_t *sl) {
if(sl->chip_id==STM32F4_CHIP_ID) {
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_F4_CR, n);
}
else {
/* write to 1 only. reset by hw at unlock sequence */
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_CR, n);
}
}
if(sl->chip_id==STM32F4_CHIP_ID) {
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_CR_PG);
- write_uint32(sl->q_buf, x);
- stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_F4_CR, x);
}
else {
const uint32_t n = 1 << FLASH_CR_PG;
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_CR, n);
}
}
static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
- write_uint32(sl->q_buf, n);
if(sl->chip_id==STM32F4_CHIP_ID)
- stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_F4_CR, n);
else
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_CR, n);
}
static void set_flash_cr_per(stlink_t *sl) {
const uint32_t n = 1 << FLASH_CR_PER;
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_CR, n);
}
static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_CR, n);
}
static void set_flash_cr_mer(stlink_t *sl) {
const uint32_t n = 1 << FLASH_CR_MER;
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_CR, n);
}
static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER);
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_CR, n);
}
static void set_flash_cr_strt(stlink_t *sl) {
{
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_F4_CR_STRT);
- write_uint32(sl->q_buf, x);
- stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_F4_CR, x);
}
else {
/* assume come on the flash_cr_per path */
const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT);
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_CR, n);
}
}
static inline uint32_t read_flash_acr(stlink_t *sl) {
- stlink_read_mem32(sl, FLASH_ACR, sizeof (uint32_t));
- return read_uint32(sl->q_buf, 0);
+ return stlink_read_debug32(sl, FLASH_ACR);
}
static inline uint32_t read_flash_sr(stlink_t *sl) {
+ uint32_t res;
if(sl->chip_id==STM32F4_CHIP_ID)
- stlink_read_mem32(sl, FLASH_F4_SR, sizeof (uint32_t));
+ res = stlink_read_debug32(sl, FLASH_F4_SR);
else
- stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t));
+ res = stlink_read_debug32(sl, FLASH_SR);
//fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
- return read_uint32(sl->q_buf, 0);
+ return res;
}
static inline unsigned int is_flash_busy(stlink_t *sl) {
static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_SR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_SR, n);
}
static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
}
static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_AR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_AR, n);
}
static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
#if DEBUG_FLASH
fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
#endif
- write_uint32(sl->q_buf, x);
- stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_F4_CR, x);
}
#if DEBUG_FLASH
fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
#endif
- write_uint32(sl->q_buf, x);
- stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_F4_CR, x);
}
#if 0 /* todo */
void stlink_exit_debug_mode(stlink_t *sl) {
DLOG("*** stlink_exit_debug_mode ***\n");
+ stlink_write_debug32(sl, DHCSR, DBGKEY);
sl->backend->exit_debug_mode(sl);
}
}
uint32_t stlink_chip_id(stlink_t *sl) {
- stlink_read_mem32(sl, 0xE0042000, 4);
- uint32_t chip_id = sl->q_buf[0] | (sl->q_buf[1] << 8) | (sl->q_buf[2] << 16) |
- (sl->q_buf[3] << 24);
+ uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000);
return chip_id;
}
* @param cpuid pointer to the result object
*/
void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
- stlink_read_mem32(sl, CM3_REG_CPUID, 4);
- uint32_t raw = read_uint32(sl->q_buf, 0);
+ uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID);
cpuid->implementer_id = (raw >> 24) & 0x7f;
cpuid->variant = (raw >> 20) & 0xf;
cpuid->part = (raw >> 4) & 0xfff;
} else if ((chip_id & 0xFFF) == STM32_CHIPID_F4) {
sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID
} else {
- stlink_read_mem32(sl, params->flash_size_reg, 4);
- uint32_t flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8);
+ uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff;
sl->flash_size = flash_size * 1024;
}
sl->flash_pgsz = params->flash_pagesize;
sl->sys_base = params->bootrom_base;
sl->sys_size = params->bootrom_size;
- ILOG("Device connected is: %s\n", params->description);
+ ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
// TODO make note of variable page size here.....
ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
sl->backend->reset(sl);
}
+void stlink_jtag_reset(stlink_t *sl, int value) {
+ DLOG("*** stlink_jtag_reset ***\n");
+ sl->backend->jtag_reset(sl, value);
+}
+
void stlink_run(stlink_t *sl) {
DLOG("*** stlink_run ***\n");
sl->backend->run(sl);
}
}
+uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) {
+ uint32_t data = sl->backend->read_debug32(sl, addr);
+ DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
+ return data;
+}
+
+void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
+ DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
+ sl->backend->write_debug32(sl, addr, data);
+}
+
void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
if (len % 4 != 0) {
int error = -1;
size_t off;
+ int num_zero = 0;
const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
if (fd == -1) {
for (off = 0; off < size; off += 1024) {
size_t read_size = 1024;
size_t rounded_size;
+ size_t index;
if ((off + read_size) > size)
read_size = size - off;
stlink_read_mem32(sl, addr + off, rounded_size);
+ for(index = 0; index < read_size; index ++) {
+ if (sl->q_buf[index] == 0)
+ num_zero ++;
+ else
+ num_zero = 0;
+ }
if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
fprintf(stderr, "write() != read_size\n");
goto on_error;
}
}
+ /* Ignore NULL Bytes at end of file */
+ ftruncate(fd, size - num_zero);
+
/* success */
error = 0;
uint32_t val;
/* disable pecr protection */
- write_uint32(sl->q_buf, 0x89abcdef);
- stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
- write_uint32(sl->q_buf, 0x02030405);
- stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
+ stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
+ stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
/* check pecr.pelock is cleared */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0);
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 0))
{
WLOG("pecr.pelock not clear (%#x)\n", val);
}
/* unlock program memory */
- write_uint32(sl->q_buf, 0x8c9daebf);
- stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
- write_uint32(sl->q_buf, 0x13141516);
- stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
+ stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
+ stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
/* check pecr.prglock is cleared */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0);
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 1))
{
WLOG("pecr.prglock not clear (%#x)\n", val);
/* unused: unlock the option byte block */
#if 0
- write_uint32(sl->q_buf, 0xfbead9c8);
- stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t));
- write_uint32(sl->q_buf, 0x24252627);
- stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t));
+ stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8);
+ stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627);
/* check pecr.optlock is cleared */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0);
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 2))
{
fprintf(stderr, "pecr.prglock not clear\n");
/* set pecr.{erase,prog} */
val |= (1 << 9) | (1 << 3);
- write_uint32(sl->q_buf, val);
- stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
#if 0 /* fix_to_be_confirmed */
TEXANE: ok, if experience says so and it works for you, we comment
it. If someone has a problem, please drop an email.
*/
- while (1)
+ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
{
- stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
- if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ;
}
#endif /* fix_to_be_confirmed */
/* write 0 to the first word of the page to be erased */
- memset(sl->q_buf, 0, sizeof(uint32_t));
- stlink_write_mem32(sl, flashaddr, sizeof(uint32_t));
+ stlink_write_debug32(sl, flashaddr, 0);
/* MP: It is better to wait for clearing the busy bit after issuing
page erase command, even though PM0062 recommends to wait before it.
Test shows that a few iterations is performed in the following loop
before busy bit is cleared.*/
- while (1)
+ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
{
- stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
- if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break;
}
/* reset lock bits */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
- write_uint32(sl->q_buf, val);
- stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
+ | (1 << 0) | (1 << 1) | (1 << 2);
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
}
else if (sl->core_id == STM32VL_CORE_ID)
{
#define PROGRESS_CHUNK_SIZE 0x1000
/* write a word in program memory */
for (off = 0; off < len; off += sizeof(uint32_t)) {
+ uint32_t data;
if (sl->verbose >= 1) {
if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) {
/* show progress. writing procedure is slow
}
}
- memcpy(sl->q_buf, (const void*)(base + off), sizeof(uint32_t));
- stlink_write_mem32(sl, addr + off, sizeof(uint32_t));
+ write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
+ stlink_write_debug32(sl, addr + off, data);
/* wait for sr.busy to be cleared */
wait_flash_busy(sl);
#endif /* todo: check write operation */
/* disable pecr protection */
- write_uint32(sl->q_buf, 0x89abcdef);
- stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
- write_uint32(sl->q_buf, 0x02030405);
- stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
+ stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
+ stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
/* check pecr.pelock is cleared */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0);
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 0)) {
fprintf(stderr, "pecr.pelock not clear\n");
return -1;
}
/* unlock program memory */
- write_uint32(sl->q_buf, 0x8c9daebf);
- stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
- write_uint32(sl->q_buf, 0x13141516);
- stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
+ stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
+ stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
/* check pecr.prglock is cleared */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0);
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 1)) {
fprintf(stderr, "pecr.prglock not clear\n");
return -1;
/* write a word in program memory */
for (off = 0; off < len; off += sizeof(uint32_t)) {
+ uint32_t data;
if (sl->verbose >= 1) {
if ((off & (sl->flash_pgsz - 1)) == 0) {
/* show progress. writing procedure is slow
}
}
- memcpy(sl->q_buf, (const void*)(base + off), sizeof(uint32_t));
- stlink_write_mem32(sl, addr + off, sizeof(uint32_t));
+ write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
+ stlink_write_debug32(sl, addr + off, data);
/* wait for sr.busy to be cleared */
- while (1) {
- stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
- if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ;
+ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
}
#if 0 /* todo: check redo write operation */
/* check written bytes. todo: should be on a per page basis. */
- stlink_read_mem32(sl, addr + off, sizeof(uint32_t));
- if (memcmp(sl->q_buf, base + off, sizeof(uint32_t))) {
+ data = stlink_read_debug32(sl, addr + off);
+ if (data == *(uint32_t*)(base + off)) {
/* re erase the page and redo the write operation */
uint32_t page;
uint32_t val;
page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0));
/* reset lock bits */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
- write_uint32(sl->q_buf, val);
- stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
+ | (1 << 0) | (1 << 1) | (1 << 2);
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
stlink_erase_flash_page(sl, page);
#endif /* todo: check redo write operation */
}
/* reset lock bits */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
- write_uint32(sl->q_buf, val);
- stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
+ | (1 << 0) | (1 << 1) | (1 << 2);
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
} else if (sl->core_id == STM32VL_CORE_ID) {
ILOG("Starting Flash write for VL core id\n");
/* flash loader initialization */
int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
/* write the file in flash at addr */
int err;
+ unsigned int num_zero = 0, index;
mapped_file_t mf = MAPPED_FILE_INITIALIZER;
if (map_file(&mf, path) == -1) {
WLOG("map_file() == -1\n");
return -1;
}
+ for(index = 0; index < mf.len; index ++) {
+ if (mf.base[index] == 0)
+ num_zero ++;
+ else
+ num_zero = 0;
+ }
+ if(num_zero != 0) {
+ ILOG("Ignoring %d bytes of Zeros at end of file\n",num_zero);
+ mf.len -= num_zero;
+ }
err = stlink_write_flash(sl, addr, mf.base, mf.len);
unmap_file(&mf);
return err;
projects / fw / stlink / blobdiff