}
uint32_t stlink_chip_id(stlink_t *sl) {
- stlink_read_mem32(sl, 0xE0042000, 4);
- uint32_t chip_id = sl->q_buf[0] | (sl->q_buf[1] << 8) | (sl->q_buf[2] << 16) |
- (sl->q_buf[3] << 24);
+ uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000);
return chip_id;
}
* @param cpuid pointer to the result object
*/
void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
- stlink_read_mem32(sl, CM3_REG_CPUID, 4);
- uint32_t raw = read_uint32(sl->q_buf, 0);
+ uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID);
cpuid->implementer_id = (raw >> 24) & 0x7f;
cpuid->variant = (raw >> 20) & 0xf;
cpuid->part = (raw >> 4) & 0xfff;
} else if ((chip_id & 0xFFF) == STM32_CHIPID_F4) {
sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID
} else {
- stlink_read_mem32(sl, params->flash_size_reg, 4);
- uint32_t flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8);
+ uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff;
sl->flash_size = flash_size * 1024;
}
sl->flash_pgsz = params->flash_pagesize;
#endif /* fix_to_be_confirmed */
/* write 0 to the first word of the page to be erased */
- stlink_write_mem32(sl, flashaddr, 0);
+ stlink_write_debug32(sl, flashaddr, 0);
/* MP: It is better to wait for clearing the busy bit after issuing
page erase command, even though PM0062 recommends to wait before it.
}
write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
- stlink_write_mem32(sl, addr + off, data);
+ stlink_write_debug32(sl, addr + off, data);
/* wait for sr.busy to be cleared */
- while (stlink_read_debug32(sl, STM32L_FLASH_SR & (1 << 0)) != 0) {
+ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
}
#if 0 /* todo: check redo write operation */