-
+#define DEBUG_FLASH 0
#include <stdarg.h>
#include <stdio.h>
#define FLASH_CR_STRT 6
#define FLASH_CR_LOCK 7
+
+//32L = 32F1 same CoreID as 32F4!
+#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
+#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
+#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
+#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
+#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
+#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
+#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
+#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
+#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
+#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
+#define FLASH_L1_FPRG 10
+#define FLASH_L1_PROG 3
+
+
+//STM32F4
+#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
+#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
+#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
+#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
+#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
+#define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14)
+#define FLASH_F4_CR_STRT 16
+#define FLASH_F4_CR_LOCK 31
+#define FLASH_F4_CR_SER 1
+#define FLASH_F4_CR_SNB 3
+#define FLASH_F4_CR_SNB_MASK 0x38
+#define FLASH_F4_SR_BSY 16
+
+
void write_uint32(unsigned char* buf, uint32_t ui) {
if (!is_bigendian()) { // le -> le (don't swap)
buf[0] = ((unsigned char*) &ui)[0];
}
static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
- stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
- return (*(uint32_t*) sl->q_buf) & 0xff;
+ return stlink_read_debug32(sl, FLASH_WRPR) & 0xff;
}
static inline uint32_t read_flash_wrpr(stlink_t *sl) {
- stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
- return *(uint32_t*) sl->q_buf;
+ return stlink_read_debug32(sl, FLASH_WRPR);
}
static inline uint32_t read_flash_obr(stlink_t *sl) {
- stlink_read_mem32(sl, FLASH_OBR, sizeof (uint32_t));
- return *(uint32_t*) sl->q_buf;
+ return stlink_read_debug32(sl, FLASH_OBR);
}
static inline uint32_t read_flash_cr(stlink_t *sl) {
- stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t));
- return *(uint32_t*) sl->q_buf;
+ uint32_t res;
+ if(sl->chip_id==STM32F4_CHIP_ID)
+ res = stlink_read_debug32(sl, FLASH_F4_CR);
+ else
+ res = stlink_read_debug32(sl, FLASH_CR);
+#if DEBUG_FLASH
+ fprintf(stdout, "CR:0x%x\n", res);
+#endif
+ return res;
}
static inline unsigned int is_flash_locked(stlink_t *sl) {
/* return non zero for true */
- return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
+ if(sl->chip_id==STM32F4_CHIP_ID)
+ return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
+ else
+ return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
}
static void unlock_flash(stlink_t *sl) {
an invalid sequence results in a definitive lock of
the FPEC block until next reset.
*/
+ if(sl->chip_id==STM32F4_CHIP_ID) {
+ stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
+ stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
+ }
+ else {
+ stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
+ stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
+ }
- write_uint32(sl->q_buf, FLASH_KEY1);
- stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
-
- write_uint32(sl->q_buf, FLASH_KEY2);
- stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
}
static int unlock_flash_if(stlink_t *sl) {
return -1;
}
}
- ILOG("Successfully unlocked flash\n");
+ DLOG("Successfully unlocked flash\n");
return 0;
}
static void lock_flash(stlink_t *sl) {
- /* write to 1 only. reset by hw at unlock sequence */
-
- const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
-
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ if(sl->chip_id==STM32F4_CHIP_ID) {
+ const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
+ stlink_write_debug32(sl, FLASH_F4_CR, n);
+ }
+ else {
+ /* write to 1 only. reset by hw at unlock sequence */
+ const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
+ stlink_write_debug32(sl, FLASH_CR, n);
+ }
}
+
static void set_flash_cr_pg(stlink_t *sl) {
- const uint32_t n = 1 << FLASH_CR_PG;
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ if(sl->chip_id==STM32F4_CHIP_ID) {
+ uint32_t x = read_flash_cr(sl);
+ x |= (1 << FLASH_CR_PG);
+ stlink_write_debug32(sl, FLASH_F4_CR, x);
+ }
+ else {
+ const uint32_t n = 1 << FLASH_CR_PG;
+ stlink_write_debug32(sl, FLASH_CR, n);
+ }
}
static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ if(sl->chip_id==STM32F4_CHIP_ID)
+ stlink_write_debug32(sl, FLASH_F4_CR, n);
+ else
+ stlink_write_debug32(sl, FLASH_CR, n);
}
static void set_flash_cr_per(stlink_t *sl) {
const uint32_t n = 1 << FLASH_CR_PER;
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_CR, n);
}
static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_CR, n);
}
static void set_flash_cr_mer(stlink_t *sl) {
- const uint32_t n = 1 << FLASH_CR_MER;
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ if(sl->chip_id == STM32F4_CHIP_ID)
+ stlink_write_debug32(sl, FLASH_F4_CR,
+ stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
+ else
+ stlink_write_debug32(sl, FLASH_CR,
+ stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER));
}
static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
- const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER);
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ if(sl->chip_id == STM32F4_CHIP_ID)
+ stlink_write_debug32(sl, FLASH_F4_CR,
+ stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
+ else
+ stlink_write_debug32(sl, FLASH_CR,
+ stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER));
}
static void set_flash_cr_strt(stlink_t *sl) {
- /* assume come on the flash_cr_per path */
- const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT);
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
+ if(sl->chip_id == STM32F4_CHIP_ID)
+ {
+ uint32_t x = read_flash_cr(sl);
+ x |= (1 << FLASH_F4_CR_STRT);
+ stlink_write_debug32(sl, FLASH_F4_CR, x);
+ }
+ else {
+ stlink_write_debug32(
+ sl, FLASH_CR,
+ stlink_read_debug32(sl,FLASH_CR) |(1 << FLASH_CR_STRT) );
+ }
}
static inline uint32_t read_flash_acr(stlink_t *sl) {
- stlink_read_mem32(sl, FLASH_ACR, sizeof (uint32_t));
- return *(uint32_t*) sl->q_buf;
+ return stlink_read_debug32(sl, FLASH_ACR);
}
static inline uint32_t read_flash_sr(stlink_t *sl) {
- stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t));
- return *(uint32_t*) sl->q_buf;
+ uint32_t res;
+ if(sl->chip_id==STM32F4_CHIP_ID)
+ res = stlink_read_debug32(sl, FLASH_F4_SR);
+ else
+ res = stlink_read_debug32(sl, FLASH_SR);
+ //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
+ return res;
}
static inline unsigned int is_flash_busy(stlink_t *sl) {
- return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
+ if(sl->chip_id==STM32F4_CHIP_ID)
+ return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
+ else
+ return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
}
static void wait_flash_busy(stlink_t *sl) {
;
}
+static void wait_flash_busy_progress(stlink_t *sl) {
+ int i = 0;
+ fprintf(stdout, "Mass erasing");
+ fflush(stdout);
+ while (is_flash_busy(sl))
+ {
+ usleep(10000);
+ i++;
+ if (i % 100 == 0) {
+ fprintf(stdout, ".");
+ fflush(stdout);
+ }
+ }
+ fprintf(stdout, "\n");
+}
+
static inline unsigned int is_flash_eop(stlink_t *sl) {
return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
}
static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_SR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_SR, n);
}
static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
}
static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
- write_uint32(sl->q_buf, n);
- stlink_write_mem32(sl, FLASH_AR, sizeof (uint32_t));
+ stlink_write_debug32(sl, FLASH_AR, n);
+}
+
+static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
+ uint32_t x = read_flash_cr(sl);
+ x &= ~(0x03 << 8);
+ x |= (n << 8);
+#if DEBUG_FLASH
+ fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
+#endif
+ stlink_write_debug32(sl, FLASH_F4_CR, x);
+}
+
+
+static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
+ uint32_t x = read_flash_cr(sl);
+ x &= ~FLASH_F4_CR_SNB_MASK;
+ x |= (n << FLASH_F4_CR_SNB);
+ x |= (1 << FLASH_F4_CR_SER);
+#if DEBUG_FLASH
+ fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
+#endif
+ stlink_write_debug32(sl, FLASH_F4_CR, x);
}
#if 0 /* todo */
void stlink_exit_debug_mode(stlink_t *sl) {
DLOG("*** stlink_exit_debug_mode ***\n");
+ stlink_write_debug32(sl, DHCSR, DBGKEY);
sl->backend->exit_debug_mode(sl);
}
return sl->core_id;
}
-uint16_t stlink_chip_id(stlink_t *sl) {
- stlink_read_mem32(sl, 0xE0042000, 4);
- uint32_t chip_id = sl->q_buf[0] | (sl->q_buf[1] << 8) | (sl->q_buf[2] << 16) |
- (sl->q_buf[3] << 24);
+uint32_t stlink_chip_id(stlink_t *sl) {
+ uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000);
return chip_id;
}
* @param cpuid pointer to the result object
*/
void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
- stlink_read_mem32(sl, CM3_REG_CPUID, 4);
- uint32_t raw = read_uint32(sl->q_buf, 0);
+ uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID);
cpuid->implementer_id = (raw >> 24) & 0x7f;
cpuid->variant = (raw >> 20) & 0xf;
cpuid->part = (raw >> 4) & 0xfff;
*/
int stlink_load_device_params(stlink_t *sl) {
ILOG("Loading device parameters....\n");
- chip_params_t *params = NULL;
+ const chip_params_t *params = NULL;
+ sl->core_id = stlink_core_id(sl);
uint32_t chip_id = stlink_chip_id(sl);
- sl->chip_id = chip_id;
- for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
- if(devices[i].chip_id == (chip_id & 0xFFF)) {
- params = &devices[i];
- break;
- }
- }
+
+ sl->chip_id = chip_id & 0xfff;
+ /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
+ if (sl->chip_id == 0x411) {
+ uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00);
+ if((cpuid & 0xfff0) == 0xc240)
+ sl->chip_id = 0x413;
+ }
+
+ for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
+ if(devices[i].chip_id == sl->chip_id) {
+ params = &devices[i];
+ break;
+ }
+ }
if (params == NULL) {
WLOG("unknown chip id! %#x\n", chip_id);
return -1;
sl->sram_base = STM32_SRAM_BASE;
// read flash size from hardware, if possible...
- if ((chip_id & 0xFFF) == STM32_CHIPID_F2) {
+ if (sl->chip_id == STM32_CHIPID_F2) {
sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible?
+ } else if (sl->chip_id == STM32_CHIPID_F4) {
+ sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID
} else {
- stlink_read_mem32(sl, params->flash_size_reg, 4);
- uint32_t flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8);
+ uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff;
sl->flash_size = flash_size * 1024;
}
sl->flash_pgsz = params->flash_pagesize;
sl->sys_base = params->bootrom_base;
sl->sys_size = params->bootrom_size;
- sl->core_id = stlink_core_id(sl);
-
- ILOG("Device connected is: %s\n", params->description);
+ ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
+ // TODO make note of variable page size here.....
ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
sl->flash_pgsz);
sl->backend->reset(sl);
}
+void stlink_jtag_reset(stlink_t *sl, int value) {
+ DLOG("*** stlink_jtag_reset ***\n");
+ sl->backend->jtag_reset(sl, value);
+}
+
void stlink_run(stlink_t *sl) {
DLOG("*** stlink_run ***\n");
sl->backend->run(sl);
}
}
+uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) {
+ uint32_t data = sl->backend->read_debug32(sl, addr);
+ DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
+ return data;
+}
+
+void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
+ DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
+ sl->backend->write_debug32(sl, addr, data);
+}
+
void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
if (len % 4 != 0) {
void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
DLOG("*** stlink_write_mem8 ***\n");
+ if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour
+ fprintf(stderr, "Error: Data length > 64: +%d byte.\n",
+ len);
+ return;
+ }
sl->backend->write_mem8(sl, addr, len);
}
}
void stlink_print_data(stlink_t * sl) {
- if (sl->q_len <= 0 || sl->verbose < 2)
+ if (sl->q_len <= 0 || sl->verbose < UDEBUG)
return;
if (sl->verbose > 2)
fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
mf->len = 0;
}
+/* Limit the block size to compare to 0x1800
+ Anything larger will stall the STLINK2
+ Maybe STLINK V1 needs smaller value!*/
static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
size_t off;
+ size_t n_cmp = sl->flash_pgsz;
+ if ( n_cmp > 0x1800)
+ n_cmp = 0x1800;
- for (off = 0; off < mf->len; off += sl->flash_pgsz) {
+ for (off = 0; off < mf->len; off += n_cmp) {
size_t aligned_size;
/* adjust last page size */
- size_t cmp_size = sl->flash_pgsz;
- if ((off + sl->flash_pgsz) > mf->len)
+ size_t cmp_size = n_cmp;
+ if ((off + n_cmp) > mf->len)
cmp_size = mf->len - off;
aligned_size = cmp_size;
/* success */
error = 0;
+ /* set stack*/
+ stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
+ /* Set PC to the reset routine*/
+ stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
+ stlink_run(sl);
on_error:
unmap_file(&mf);
int error = -1;
size_t off;
+ int num_empty = 0;
+ unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff;
const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
if (fd == -1) {
return -1;
}
+ if (size <1)
+ size = sl->flash_size;
+
+ if (size > sl->flash_size)
+ size = sl->flash_size;
+
/* do the copy by 1k blocks */
for (off = 0; off < size; off += 1024) {
size_t read_size = 1024;
size_t rounded_size;
+ size_t index;
if ((off + read_size) > size)
read_size = size - off;
stlink_read_mem32(sl, addr + off, rounded_size);
+ for(index = 0; index < read_size; index ++) {
+ if (sl->q_buf[index] == erased_pattern)
+ num_empty ++;
+ else
+ num_empty = 0;
+ }
if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
fprintf(stderr, "write() != read_size\n");
goto on_error;
}
}
+ /* Ignore NULL Bytes at end of file */
+ ftruncate(fd, size - num_empty);
+
/* success */
error = 0;
int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
/* write the buffer right after the loader */
- memcpy(sl->q_buf, buf, size);
- stlink_write_mem8(sl, fl->buf_addr, size);
+ size_t chunk = size & ~0x3;
+ size_t rem = size & 0x3;
+ if (chunk) {
+ memcpy(sl->q_buf, buf, chunk);
+ stlink_write_mem32(sl, fl->buf_addr, chunk);
+ }
+ if (rem) {
+ memcpy(sl->q_buf, buf+chunk, rem);
+ stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem);
+ }
return 0;
}
+uint32_t calculate_F4_sectornum(uint32_t flashaddr){
+ flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
+ if (flashaddr<0x4000) return (0);
+ else if(flashaddr<0x8000) return(1);
+ else if(flashaddr<0xc000) return(2);
+ else if(flashaddr<0x10000) return(3);
+ else if(flashaddr<0x20000) return(4);
+ else return(flashaddr/0x20000)+4;
+
+}
+
+uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
+ if(sl->chip_id == STM32F4_CHIP_ID) {
+ uint32_t sector=calculate_F4_sectornum(flashaddr);
+ if (sector<4) sl->flash_pgsz=0x4000;
+ else if(sector<5) sl->flash_pgsz=0x10000;
+ else sl->flash_pgsz=0x20000;
+ }
+ return (sl->flash_pgsz);
+}
+
/**
* Erase a page of flash, assumes sl is fully populated with things like chip/core ids
* @param sl stlink context
- * @param page
+ * @param flashaddr an address in the flash page to erase
* @return 0 on success -ve on failure
*/
-int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page)
+int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
{
- /* page an addr in the page to erase */
- ILOG("Erasing flash page at addr: %#x\n", page);
- if (sl->core_id == STM32L_CORE_ID)
+ if (sl->chip_id == STM32F4_CHIP_ID)
+ {
+ /* wait for ongoing op to finish */
+ wait_flash_busy(sl);
+
+ /* unlock if locked */
+ unlock_flash_if(sl);
+
+ /* select the page to erase */
+ // calculate the actual page from the address
+ uint32_t sector=calculate_F4_sectornum(flashaddr);
+
+ fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
+ write_flash_cr_snb(sl, sector);
+
+ /* start erase operation */
+ set_flash_cr_strt(sl);
+
+ /* wait for completion */
+ wait_flash_busy(sl);
+
+ /* relock the flash */
+ //todo: fails to program if this is in
+ lock_flash(sl);
+#if DEBUG_FLASH
+ fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
+#endif
+ }
+ else if (sl->core_id == STM32L_CORE_ID)
{
-#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
-#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
-#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
-#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
-#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
-#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
-#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
-#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
-#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x0c)
-#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
uint32_t val;
/* disable pecr protection */
- write_uint32(sl->q_buf, 0x89abcdef);
- stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
- write_uint32(sl->q_buf, 0x02030405);
- stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
+ stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
+ stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
/* check pecr.pelock is cleared */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0);
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 0))
{
WLOG("pecr.pelock not clear (%#x)\n", val);
}
/* unlock program memory */
- write_uint32(sl->q_buf, 0x8c9daebf);
- stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
- write_uint32(sl->q_buf, 0x13141516);
- stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
+ stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
+ stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
/* check pecr.prglock is cleared */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0);
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 1))
{
WLOG("pecr.prglock not clear (%#x)\n", val);
/* unused: unlock the option byte block */
#if 0
- write_uint32(sl->q_buf, 0xfbead9c8);
- stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t));
- write_uint32(sl->q_buf, 0x24252627);
- stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t));
+ stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8);
+ stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627);
/* check pecr.optlock is cleared */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0);
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
if (val & (1 << 2))
{
fprintf(stderr, "pecr.prglock not clear\n");
/* set pecr.{erase,prog} */
val |= (1 << 9) | (1 << 3);
- write_uint32(sl->q_buf, val);
- stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
+
+#if 0 /* fix_to_be_confirmed */
- /* wait for sr.busy to be cleared */
- while (1)
+ /* wait for sr.busy to be cleared
+ MP: Test shows that busy bit is not set here. Perhaps, PM0062 is
+ wrong and we do not need to wait here for clearing the busy bit.
+ TEXANE: ok, if experience says so and it works for you, we comment
+ it. If someone has a problem, please drop an email.
+ */
+ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
{
- stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
- if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ;
}
+#endif /* fix_to_be_confirmed */
+
/* write 0 to the first word of the page to be erased */
- memset(sl->q_buf, 0, sizeof(uint32_t));
- stlink_write_mem32(sl, page, sizeof(uint32_t));
+ stlink_write_debug32(sl, flashaddr, 0);
+
+ /* MP: It is better to wait for clearing the busy bit after issuing
+ page erase command, even though PM0062 recommends to wait before it.
+ Test shows that a few iterations is performed in the following loop
+ before busy bit is cleared.*/
+ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
+ {
+ }
/* reset lock bits */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
- write_uint32(sl->q_buf, val);
- stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
+ | (1 << 0) | (1 << 1) | (1 << 2);
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
}
else if (sl->core_id == STM32VL_CORE_ID)
{
set_flash_cr_per(sl);
/* select the page to erase */
- write_flash_ar(sl, page);
+ write_flash_ar(sl, flashaddr);
/* start erase operation, reset by hw with bsy bit */
set_flash_cr_strt(sl);
/* relock the flash */
lock_flash(sl);
}
+
else {
WLOG("unknown coreid: %x\n", sl->core_id);
return -1;
}
int stlink_erase_flash_mass(stlink_t *sl) {
- /* wait for ongoing op to finish */
- wait_flash_busy(sl);
-
- /* unlock if locked */
- unlock_flash_if(sl);
-
- /* set the mass erase bit */
- set_flash_cr_mer(sl);
-
- /* start erase operation, reset by hw with bsy bit */
- set_flash_cr_strt(sl);
-
- /* wait for completion */
- wait_flash_busy(sl);
-
- /* relock the flash */
- lock_flash(sl);
-
- /* todo: verify the erased memory */
-
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
+ /* erase each page */
+ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
+ for (i = 0; i < num_pages; i++) {
+ /* addr must be an addr inside the page */
+ stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz;
+ if (stlink_erase_flash_page(sl, addr) == -1) {
+ WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr);
+ return -1;
+ }
+ fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages);
+ fflush(stdout);
+ }
+ fprintf(stdout, "\n");
+ }
+ else {
+ /* wait for ongoing op to finish */
+ wait_flash_busy(sl);
+
+ /* unlock if locked */
+ unlock_flash_if(sl);
+
+ /* set the mass erase bit */
+ set_flash_cr_mer(sl);
+
+ /* start erase operation, reset by hw with bsy bit */
+ set_flash_cr_strt(sl);
+
+ /* wait for completion */
+ wait_flash_busy_progress(sl);
+
+ /* relock the flash */
+ lock_flash(sl);
+
+ /* todo: verify the erased memory */
+ }
return 0;
}
return res;
}
+/**
+ * Verify addr..addr+len is binary identical to base...base+len
+ * @param sl stlink context
+ * @param address stm device address
+ * @param data host side buffer to check against
+ * @param length how much
+ * @return 0 for success, -ve for failure
+ */
+int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
+ size_t off;
+ if (sl->chip_id == STM32_CHIPID_F4) {
+ DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n");
+ return 0;
+ }
+ ILOG("Starting verification of write complete\n");
+ for (off = 0; off < length; off += sl->flash_pgsz) {
+ size_t aligned_size;
+
+ /* adjust last page size */
+ size_t cmp_size = sl->flash_pgsz;
+ if ((off + sl->flash_pgsz) > length)
+ cmp_size = length - off;
+
+ aligned_size = cmp_size;
+ if (aligned_size & (4 - 1))
+ aligned_size = (cmp_size + 4) & ~(4 - 1);
+
+ stlink_read_mem32(sl, address + off, aligned_size);
+
+ if (memcmp(sl->q_buf, data + off, cmp_size)) {
+ WLOG("Verification of flash failed at offset: %zd\n", off);
+ return -1;
+ }
+ }
+ ILOG("Flash written and verified! jolly good!\n");
+ return 0;
+
+}
+
+int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages)
+{
+ unsigned int count;
+ uint32_t val;
+ flash_loader_t fl;
+
+ ILOG("Starting Half page flash write for STM32L core id\n");
+ /* flash loader initialization */
+ if (init_flash_loader(sl, &fl) == -1) {
+ WLOG("init_flash_loader() == -1\n");
+ return -1;
+ }
+ /* Unlock already done */
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ val |= (1 << FLASH_L1_FPRG);
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
+
+ val |= (1 << FLASH_L1_PROG);
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
+ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {}
+
+#define L1_WRITE_BLOCK_SIZE 0x80
+ for (count = 0; count < num_half_pages; count ++) {
+ if (run_flash_loader(sl, &fl, addr + count * L1_WRITE_BLOCK_SIZE, base + count * L1_WRITE_BLOCK_SIZE, L1_WRITE_BLOCK_SIZE) == -1) {
+ WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * L1_WRITE_BLOCK_SIZE);
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG));
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
+ return -1;
+ }
+ /* wait for sr.busy to be cleared */
+ if (sl->verbose >= 1) {
+ /* show progress. writing procedure is slow
+ and previous errors are misleading */
+ fprintf(stdout, "\r%3u/%u halfpages written", count, num_half_pages);
+ fflush(stdout);
+ }
+ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
+ }
+ }
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ val &= ~(1 << FLASH_L1_PROG);
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ val &= ~(1 << FLASH_L1_FPRG);
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
+
+ return 0;
+}
int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) {
size_t off;
ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n",
len, len, addr, addr);
/* check addr range is inside the flash */
+ stlink_calculate_pagesize(sl, addr);
if (addr < sl->flash_base) {
WLOG("addr too low %#x < %#x\n", addr, sl->flash_base);
return -1;
stlink_core_id(sl);
/* erase each page */
int page_count = 0;
- for (off = 0; off < len; off += sl->flash_pgsz) {
+ for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) {
/* addr must be an addr inside the page */
if (stlink_erase_flash_page(sl, addr + off) == -1) {
WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off);
return -1;
}
+ fprintf(stdout,"\rFlash page at addr: 0x%08lx erased",
+ (unsigned long)addr + off);
+ fflush(stdout);
page_count++;
}
+ fprintf(stdout,"\n");
ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
page_count, sl->flash_pgsz, sl->flash_pgsz);
- if (sl->core_id == STM32L_CORE_ID)
- {
- /* use fast word write. todo: half page. */
+ if (sl->chip_id == STM32F4_CHIP_ID) {
+ /* todo: check write operation */
+
+ /* First unlock the cr */
+ unlock_flash_if(sl);
+
+ /* TODO: Check that Voltage range is 2.7 - 3.6 V */
+ /* set parallelisim to 32 bit*/
+ write_flash_cr_psiz(sl, 2);
+
+ /* set programming mode */
+ set_flash_cr_pg(sl);
+
+#define PROGRESS_CHUNK_SIZE 0x1000
+ /* write a word in program memory */
+ for (off = 0; off < len; off += sizeof(uint32_t)) {
+ uint32_t data;
+ if (sl->verbose >= 1) {
+ if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) {
+ /* show progress. writing procedure is slow
+ and previous errors are misleading */
+ const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1;
+ const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE;
+ fprintf(stdout, "Writing %ukB chunk %u out of %u\n", PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount);
+ }
+ }
+
+ write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
+ stlink_write_debug32(sl, addr + off, data);
+
+ /* wait for sr.busy to be cleared */
+ wait_flash_busy(sl);
+
+ }
+ /* Relock flash */
+ lock_flash(sl);
+
+#if 0 /* todo: debug mode */
+ fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl));
+#endif
+
+
+
+ } //STM32F4END
- uint32_t val;
+ else if (sl->core_id == STM32L_CORE_ID) {
+ /* use fast word write. todo: half page. */
+ uint32_t val;
#if 0 /* todo: check write operation */
- uint32_t nwrites = sl->flash_pgsz;
+ uint32_t nwrites = sl->flash_pgsz;
- redo_write:
+ redo_write:
#endif /* todo: check write operation */
- /* disable pecr protection */
- write_uint32(sl->q_buf, 0x89abcdef);
- stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
- write_uint32(sl->q_buf, 0x02030405);
- stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t));
-
- /* check pecr.pelock is cleared */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0);
- if (val & (1 << 0))
- {
- fprintf(stderr, "pecr.pelock not clear\n");
- return -1;
- }
+ /* disable pecr protection */
+ stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
+ stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
+
+ /* check pecr.pelock is cleared */
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ if (val & (1 << 0)) {
+ fprintf(stderr, "pecr.pelock not clear\n");
+ return -1;
+ }
+
+ /* unlock program memory */
+ stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
+ stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
+
+ /* check pecr.prglock is cleared */
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
+ if (val & (1 << 1)) {
+ fprintf(stderr, "pecr.prglock not clear\n");
+ return -1;
+ }
+ off = 0;
+ if (len > L1_WRITE_BLOCK_SIZE) {
+ if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){
+ /* This may happen on a blank device! */
+ WLOG("\nwrite_half_pages failed == -1\n");
+ }
+ else{
+ off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE;
+ }
+ }
- /* unlock program memory */
- write_uint32(sl->q_buf, 0x8c9daebf);
- stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
- write_uint32(sl->q_buf, 0x13141516);
- stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t));
-
- /* check pecr.prglock is cleared */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0);
- if (val & (1 << 1))
- {
- fprintf(stderr, "pecr.prglock not clear\n");
- return -1;
- }
+ /* write remainingword in program memory */
+ for ( ; off < len; off += sizeof(uint32_t)) {
+ uint32_t data;
+ if (off > 254)
+ fprintf(stdout, "\r");
- /* write a word in program memory */
- for (off = 0; off < len; off += sizeof(uint32_t))
- {
- if (sl->verbose >= 1)
- {
- if ((off & (sl->flash_pgsz - 1)) == 0)
- {
- /* show progress. writing procedure is slow
- and previous errors are misleading */
- const uint32_t pgnum = off / sl->flash_pgsz;
- const uint32_t pgcount = len / sl->flash_pgsz;
- fprintf(stdout, "%u pages written out of %u\n", pgnum, pgcount);
- }
- }
+ if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) {
+ fprintf(stdout, "\r%3u/%u pages written",
+ off/sl->flash_pgsz, len/sl->flash_pgsz);
+ fflush(stdout);
+ }
- memcpy(sl->q_buf, (const void*)(base + off), sizeof(uint32_t));
- stlink_write_mem32(sl, addr + off, sizeof(uint32_t));
+ write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
+ stlink_write_debug32(sl, addr + off, data);
- /* wait for sr.busy to be cleared */
- while (1)
- {
- stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t));
- if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ;
- }
+ /* wait for sr.busy to be cleared */
+ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
+ }
#if 0 /* todo: check redo write operation */
- /* check written bytes. todo: should be on a per page basis. */
- stlink_read_mem32(sl, addr + off, sizeof(uint32_t));
- if (memcmp(sl->q_buf, base + off, sizeof(uint32_t)))
- {
- /* re erase the page and redo the write operation */
- uint32_t page;
- uint32_t val;
+ /* check written bytes. todo: should be on a per page basis. */
+ data = stlink_read_debug32(sl, addr + off);
+ if (data == *(uint32_t*)(base + off)) {
+ /* re erase the page and redo the write operation */
+ uint32_t page;
+ uint32_t val;
- /* fail if successive write count too low */
- if (nwrites < sl->flash_pgsz) {
- fprintf(stderr, "writes operation failure count too high, aborting\n");
- return -1;
- }
+ /* fail if successive write count too low */
+ if (nwrites < sl->flash_pgsz) {
+ fprintf(stderr, "writes operation failure count too high, aborting\n");
+ return -1;
+ }
- nwrites = 0;
+ nwrites = 0;
- /* assume addr aligned */
- if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1);
- page = addr + off;
+ /* assume addr aligned */
+ if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1);
+ page = addr + off;
- fprintf(stderr, "invalid write @%x(%x): %x != %x. retrying.\n",
- page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0));
+ fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n",
+ page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0));
- /* reset lock bits */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
- write_uint32(sl->q_buf, val);
- stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ /* reset lock bits */
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
+ | (1 << 0) | (1 << 1) | (1 << 2);
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
- stlink_erase_flash_page(sl, page);
+ stlink_erase_flash_page(sl, page);
- goto redo_write;
- }
+ goto redo_write;
+ }
- /* increment successive writes counter */
- ++nwrites;
+ /* increment successive writes counter */
+ ++nwrites;
#endif /* todo: check redo write operation */
-
- }
-
- /* reset lock bits */
- stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
- val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2);
- write_uint32(sl->q_buf, val);
- stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t));
+ }
+ fprintf(stdout, "\n");
+ /* reset lock bits */
+ val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
+ | (1 << 0) | (1 << 1) | (1 << 2);
+ stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
} else if (sl->core_id == STM32VL_CORE_ID) {
ILOG("Starting Flash write for VL core id\n");
/* flash loader initialization */
return -1;
}
- /* write each page. above WRITE_BLOCK_SIZE fails? */
-#define WRITE_BLOCK_SIZE 0x40
int write_block_count = 0;
- for (off = 0; off < len; off += WRITE_BLOCK_SIZE) {
- ILOG("Writing flash block %d of size %d (%#x)\n", write_block_count,
- WRITE_BLOCK_SIZE, WRITE_BLOCK_SIZE);
+ for (off = 0; off < len; off += sl->flash_pgsz) {
/* adjust last write size */
- size_t size = WRITE_BLOCK_SIZE;
- if ((off + WRITE_BLOCK_SIZE) > len) size = len - off;
+ size_t size = sl->flash_pgsz;
+ if ((off + sl->flash_pgsz) > len) size = len - off;
/* unlock and set programming mode */
unlock_flash_if(sl);
return -1;
}
lock_flash(sl);
- DLOG("Finished writing block %d\n", write_block_count++);
+ if (sl->verbose >= 1) {
+ /* show progress. writing procedure is slow
+ and previous errors are misleading */
+ fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz);
+ fflush(stdout);
+ }
}
+ fprintf(stdout, "\n");
} else {
WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id);
return -1;
}
-
- ILOG("Starting verification of write complete\n");
- for (off = 0; off < len; off += sl->flash_pgsz) {
- size_t aligned_size;
-
- /* adjust last page size */
- size_t cmp_size = sl->flash_pgsz;
- if ((off + sl->flash_pgsz) > len)
- cmp_size = len - off;
-
- aligned_size = cmp_size;
- if (aligned_size & (4 - 1))
- aligned_size = (cmp_size + 4) & ~(4 - 1);
-
- stlink_read_mem32(sl, addr + off, aligned_size);
-
- if (memcmp(sl->q_buf, base + off, cmp_size))
- return -1;
- }
- ILOG("Flash written and verified! jolly good!\n");
- return 0;
+
+ return stlink_verify_write_flash(sl, addr, base, len);
}
/**
int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
/* write the file in flash at addr */
int err;
+ unsigned int num_empty = 0, index;
+ unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff;
mapped_file_t mf = MAPPED_FILE_INITIALIZER;
if (map_file(&mf, path) == -1) {
WLOG("map_file() == -1\n");
return -1;
}
+ for(index = 0; index < mf.len; index ++) {
+ if (mf.base[index] == erased_pattern)
+ num_empty ++;
+ else
+ num_empty = 0;
+ }
+ if(num_empty != 0) {
+ ILOG("Ignoring %d bytes of Zeros at end of file\n",num_empty);
+ mf.len -= num_empty;
+ }
err = stlink_write_flash(sl, addr, mf.base, mf.len);
+ /* set stack*/
+ stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
+ /* Set PC to the reset routine*/
+ stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
+ stlink_run(sl);
unmap_file(&mf);
return err;
}
int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
reg rr;
+ int i = 0;
DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size);
// FIXME This can never return -1
if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
stlink_write_reg(sl, target, 0); /* target */
stlink_write_reg(sl, fl->buf_addr, 1); /* source */
stlink_write_reg(sl, count, 2); /* count (32 bits words) */
- stlink_write_reg(sl, 0, 3); /* output count */
stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
} else if (sl->core_id == STM32VL_CORE_ID) {
stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
} else {
- fprintf(stderr, "unknown coreid: %x\n", sl->core_id);
+ fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);
return -1;
}
stlink_run(sl);
/* wait until done (reaches breakpoint) */
- while (is_core_halted(sl) == 0) ;
+ while ((is_core_halted(sl) == 0) && (i <1000))
+ {
+ i++;
+ }
+ if ( i > 999) {
+ fprintf(stderr, "run error\n");
+ return -1;
+ }
+
/* check written byte count */
if (sl->core_id == STM32L_CORE_ID) {
} else {
- fprintf(stderr, "unknown coreid: %x\n", sl->core_id);
+ fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);
return -1;
}
projects / fw / stlink / blobdiff