}
static void set_flash_cr_mer(stlink_t *sl) {
- const uint32_t n = 1 << FLASH_CR_MER;
- stlink_write_debug32(sl, FLASH_CR, n);
+ if(sl->chip_id == STM32F4_CHIP_ID)
+ stlink_write_debug32(sl, FLASH_F4_CR,
+ stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
+ else
+ stlink_write_debug32(sl, FLASH_CR,
+ stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER));
}
static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
- const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER);
- stlink_write_debug32(sl, FLASH_CR, n);
+ if(sl->chip_id == STM32F4_CHIP_ID)
+ stlink_write_debug32(sl, FLASH_F4_CR,
+ stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
+ else
+ stlink_write_debug32(sl, FLASH_CR,
+ stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER));
}
static void set_flash_cr_strt(stlink_t *sl) {
stlink_write_debug32(sl, FLASH_F4_CR, x);
}
else {
- /* assume come on the flash_cr_per path */
- const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT);
- stlink_write_debug32(sl, FLASH_CR, n);
+ stlink_write_debug32(
+ sl, FLASH_CR,
+ stlink_read_debug32(sl,FLASH_CR) |(1 << FLASH_CR_STRT) );
}
}
;
}
+static void wait_flash_busy_progress(stlink_t *sl) {
+ int i = 0;
+ fprintf(stdout, "Mass erasing");
+ fflush(stdout);
+ while (is_flash_busy(sl))
+ {
+ usleep(10000);
+ i++;
+ if (i % 100 == 0) {
+ fprintf(stdout, ".");
+ fflush(stdout);
+ }
+ }
+ fprintf(stdout, "\n");
+}
+
static inline unsigned int is_flash_eop(stlink_t *sl) {
return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
}
int stlink_load_device_params(stlink_t *sl) {
ILOG("Loading device parameters....\n");
const chip_params_t *params = NULL;
-
sl->core_id = stlink_core_id(sl);
uint32_t chip_id = stlink_chip_id(sl);
- /* Fix chip_id for F4 rev A errata */
- if (((chip_id & 0xFFF) == 0x411) && (sl->core_id == CORE_M4_R0)) {
- chip_id = 0x413;
+ sl->chip_id = chip_id & 0xfff;
+ /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
+ if (sl->chip_id == 0x411) {
+ uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00);
+ if((cpuid & 0xfff0) == 0xc240)
+ sl->chip_id = 0x413;
}
- sl->chip_id = chip_id & 0xfff;
- for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
- if(devices[i].chip_id == sl->chip_id) {
- params = &devices[i];
- break;
- }
- }
+ for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
+ if(devices[i].chip_id == sl->chip_id) {
+ params = &devices[i];
+ break;
+ }
+ }
if (params == NULL) {
WLOG("unknown chip id! %#x\n", chip_id);
return -1;
mf->len = 0;
}
+/* Limit the block size to compare to 0x1800
+ Anything larger will stall the STLINK2
+ Maybe STLINK V1 needs smaller value!*/
static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
size_t off;
+ size_t n_cmp = sl->flash_pgsz;
+ if ( n_cmp > 0x1800)
+ n_cmp = 0x1800;
- for (off = 0; off < mf->len; off += sl->flash_pgsz) {
+ for (off = 0; off < mf->len; off += n_cmp) {
size_t aligned_size;
/* adjust last page size */
- size_t cmp_size = sl->flash_pgsz;
- if ((off + sl->flash_pgsz) > mf->len)
+ size_t cmp_size = n_cmp;
+ if ((off + n_cmp) > mf->len)
cmp_size = mf->len - off;
aligned_size = cmp_size;
}
int stlink_erase_flash_mass(stlink_t *sl) {
- if (sl->chip_id == STM32_CHIPID_F4) {
- DLOG("(FIXME) Mass erase of STM32F4\n");
- }
- else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
+ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
/* erase each page */
int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
for (i = 0; i < num_pages; i++) {
fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages);
fflush(stdout);
}
+ fprintf(stdout, "\n");
}
else {
/* wait for ongoing op to finish */
set_flash_cr_strt(sl);
/* wait for completion */
- wait_flash_busy(sl);
+ wait_flash_busy_progress(sl);
/* relock the flash */
lock_flash(sl);
unsigned int count;
uint32_t val;
flash_loader_t fl;
-
+
ILOG("Starting Half page flash write for STM32L core id\n");
/* flash loader initialization */
if (init_flash_loader(sl, &fl) == -1) {
while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
}
}
- fprintf(stdout, "\n");
val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
val &= ~(1 << FLASH_L1_PROG);
stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
fprintf(stderr, "pecr.prglock not clear\n");
return -1;
}
+ off = 0;
if (len > L1_WRITE_BLOCK_SIZE) {
if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){
+ /* This may happen on a blank device! */
WLOG("\nwrite_half_pages failed == -1\n");
- return -1;
- }
- }
+ }
+ else{
+ off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE;
+ }
+ }
/* write remainingword in program memory */
- for (off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; off < len; off += sizeof(uint32_t)) {
+ for ( ; off < len; off += sizeof(uint32_t)) {
uint32_t data;
+ if (off > 254)
+ fprintf(stdout, "\r");
+
+ if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) {
+ fprintf(stdout, "\r%3u/%u pages written",
+ off/sl->flash_pgsz, len/sl->flash_pgsz);
+ fflush(stdout);
+ }
+
write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
stlink_write_debug32(sl, addr + off, data);
stlink_run(sl);
/* wait until done (reaches breakpoint) */
- while ((is_core_halted(sl) == 0) && (i <10000))
+ while ((is_core_halted(sl) == 0) && (i <1000))
{
i++;
}
- if ( i > 9999) {
+ if ( i > 999) {
fprintf(stderr, "run error\n");
return -1;
}